diff options
Diffstat (limited to 'arch/arm/include/asm/arch-exynos')
30 files changed, 5918 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/adc.h b/arch/arm/include/asm/arch-exynos/adc.h new file mode 100644 index 0000000..c0aa580 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/adc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * MyungJoo Ham <myungjoo.ham@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_ADC_H_ +#define __ASM_ARM_ARCH_ADC_H_ + +#ifndef __ASSEMBLY__ +struct s5p_adc { + unsigned int adccon; + unsigned int adctsc; + unsigned int adcdly; + unsigned int adcdat0; + unsigned int adcdat1; + unsigned int adcupdn; + unsigned int adcclrint; + unsigned int adcmux; + unsigned int adcclrintpndnup; +}; +#endif + +#endif /* __ASM_ARM_ARCH_ADC_H_ */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h new file mode 100644 index 0000000..73f8063 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 +#define BPLL 5 + +enum pll_src_bit { + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, +}; + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); +unsigned long get_pwm_clk(void); +unsigned long get_uart_clk(int dev_index); +unsigned long get_mmc_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_lcd_clk(void); +void set_lcd_clk(void); +void set_mipi_clk(void); +void set_i2s_clk_source(void); +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); +int set_epll_clk(unsigned long rate); +int set_spi_clk(int periph_id, unsigned int rate); + +/** + * get the clk frequency of the required peripheral + * + * @param peripheral Peripheral id + * + * @return frequency of the peripheral clk + */ +unsigned long clock_get_periph_rate(int peripheral); + +#endif diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h new file mode 100644 index 0000000..9b56b4e --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -0,0 +1,909 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +#ifndef __ASSEMBLY__ +struct exynos4_clock { + unsigned char res1[0x4200]; + unsigned int src_leftbus; + unsigned char res2[0x1fc]; + unsigned int mux_stat_leftbus; + unsigned char res4[0xfc]; + unsigned int div_leftbus; + unsigned char res5[0xfc]; + unsigned int div_stat_leftbus; + unsigned char res6[0x1fc]; + unsigned int gate_ip_leftbus; + unsigned char res7[0x1fc]; + unsigned int clkout_leftbus; + unsigned int clkout_leftbus_div_stat; + unsigned char res8[0x37f8]; + unsigned int src_rightbus; + unsigned char res9[0x1fc]; + unsigned int mux_stat_rightbus; + unsigned char res10[0xfc]; + unsigned int div_rightbus; + unsigned char res11[0xfc]; + unsigned int div_stat_rightbus; + unsigned char res12[0x1fc]; + unsigned int gate_ip_rightbus; + unsigned char res13[0x1fc]; + unsigned int clkout_rightbus; + unsigned int clkout_rightbus_div_stat; + unsigned char res14[0x3608]; + unsigned int epll_lock; + unsigned char res15[0xc]; + unsigned int vpll_lock; + unsigned char res16[0xec]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned char res17[0x8]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned char res18[0xe8]; + unsigned int src_top0; + unsigned int src_top1; + unsigned char res19[0x8]; + unsigned int src_cam; + unsigned int src_tv; + unsigned int src_mfc; + unsigned int src_g3d; + unsigned int src_image; + unsigned int src_lcd0; + unsigned int src_lcd1; + unsigned int src_maudio; + unsigned int src_fsys; + unsigned char res20[0xc]; + unsigned int src_peril0; + unsigned int src_peril1; + unsigned char res21[0xb8]; + unsigned int src_mask_top; + unsigned char res22[0xc]; + unsigned int src_mask_cam; + unsigned int src_mask_tv; + unsigned char res23[0xc]; + unsigned int src_mask_lcd0; + unsigned int src_mask_lcd1; + unsigned int src_mask_maudio; + unsigned int src_mask_fsys; + unsigned char res24[0xc]; + unsigned int src_mask_peril0; + unsigned int src_mask_peril1; + unsigned char res25[0xb8]; + unsigned int mux_stat_top; + unsigned char res26[0x14]; + unsigned int mux_stat_mfc; + unsigned int mux_stat_g3d; + unsigned int mux_stat_image; + unsigned char res27[0xdc]; + unsigned int div_top; + unsigned char res28[0xc]; + unsigned int div_cam; + unsigned int div_tv; + unsigned int div_mfc; + unsigned int div_g3d; + unsigned int div_image; + unsigned int div_lcd0; + unsigned int div_lcd1; + unsigned int div_maudio; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned int div_fsys3; + unsigned int div_peril0; + unsigned int div_peril1; + unsigned int div_peril2; + unsigned int div_peril3; + unsigned int div_peril4; + unsigned int div_peril5; + unsigned char res29[0x18]; + unsigned int div2_ratio; + unsigned char res30[0x8c]; + unsigned int div_stat_top; + unsigned char res31[0xc]; + unsigned int div_stat_cam; + unsigned int div_stat_tv; + unsigned int div_stat_mfc; + unsigned int div_stat_g3d; + unsigned int div_stat_image; + unsigned int div_stat_lcd0; + unsigned int div_stat_lcd1; + unsigned int div_stat_maudio; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned int div_stat_fsys3; + unsigned int div_stat_peril0; + unsigned int div_stat_peril1; + unsigned int div_stat_peril2; + unsigned int div_stat_peril3; + unsigned int div_stat_peril4; + unsigned int div_stat_peril5; + unsigned char res32[0x18]; + unsigned int div2_stat; + unsigned char res33[0x29c]; + unsigned int gate_ip_cam; + unsigned int gate_ip_tv; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned int gate_ip_image; + unsigned int gate_ip_lcd0; + unsigned int gate_ip_lcd1; + unsigned char res34[0x4]; + unsigned int gate_ip_fsys; + unsigned char res35[0x8]; + unsigned int gate_ip_gps; + unsigned int gate_ip_peril; + unsigned char res36[0xc]; + unsigned int gate_ip_perir; + unsigned char res37[0xc]; + unsigned int gate_block; + unsigned char res38[0x8c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res39[0x37f8]; + unsigned int src_dmc; + unsigned char res40[0xfc]; + unsigned int src_mask_dmc; + unsigned char res41[0xfc]; + unsigned int mux_stat_dmc; + unsigned char res42[0xfc]; + unsigned int div_dmc0; + unsigned int div_dmc1; + unsigned char res43[0xf8]; + unsigned int div_stat_dmc0; + unsigned int div_stat_dmc1; + unsigned char res44[0x2f8]; + unsigned int gate_ip_dmc; + unsigned char res45[0xfc]; + unsigned int clkout_cmu_dmc; + unsigned int clkout_cmu_dmc_div_stat; + unsigned char res46[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res47[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res48[0x18]; + unsigned int dvcidx_map; + unsigned char res49[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res50[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res51[0x2f78]; + unsigned int apll_lock; + unsigned char res52[0x4]; + unsigned int mpll_lock; + unsigned char res53[0xf4]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res54[0xf0]; + unsigned int src_cpu; + unsigned char res55[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res56[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res57[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res58[0x3f8]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res59[0x5f8]; + unsigned int armclk_stopctrl; + unsigned int atclk_stopctrl; + unsigned char res60[0x8]; + unsigned int parityfail_status; + unsigned int parityfail_clear; + unsigned char res61[0xe8]; + unsigned int apll_con0_l8; + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res62[0xdc]; + unsigned int apll_con1_l8; + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res63[0xe0]; + unsigned int div_iem_l8; + unsigned int div_iem_l7; + unsigned int div_iem_l6; + unsigned int div_iem_l5; + unsigned int div_iem_l4; + unsigned int div_iem_l3; + unsigned int div_iem_l2; + unsigned int div_iem_l1; +}; + +struct exynos4x12_clock { + unsigned char res1[0x4200]; + unsigned int src_leftbus; + unsigned char res2[0x1fc]; + unsigned int mux_stat_leftbus; + unsigned char res3[0xfc]; + unsigned int div_leftbus; + unsigned char res4[0xfc]; + unsigned int div_stat_leftbus; + unsigned char res5[0x1fc]; + unsigned int gate_ip_leftbus; + unsigned char res6[0x12c]; + unsigned int gate_ip_image; + unsigned char res7[0xcc]; + unsigned int clkout_leftbus; + unsigned int clkout_leftbus_div_stat; + unsigned char res8[0x37f8]; + unsigned int src_rightbus; + unsigned char res9[0x1fc]; + unsigned int mux_stat_rightbus; + unsigned char res10[0xfc]; + unsigned int div_rightbus; + unsigned char res11[0xfc]; + unsigned int div_stat_rightbus; + unsigned char res12[0x1fc]; + unsigned int gate_ip_rightbus; + unsigned char res13[0x15c]; + unsigned int gate_ip_perir; + unsigned char res14[0x9c]; + unsigned int clkout_rightbus; + unsigned int clkout_rightbus_div_stat; + unsigned char res15[0x3608]; + unsigned int epll_lock; + unsigned char res16[0xc]; + unsigned int vpll_lock; + unsigned char res17[0xec]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res18[0x4]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned int vpll_con2; + unsigned char res19[0xe4]; + unsigned int src_top0; + unsigned int src_top1; + unsigned char res20[0x8]; + unsigned int src_cam; + unsigned int src_tv; + unsigned int src_mfc; + unsigned int src_g3d; + unsigned char res21[0x4]; + unsigned int src_lcd; + unsigned int src_isp; + unsigned int src_maudio; + unsigned int src_fsys; + unsigned char res22[0xc]; + unsigned int src_peril0; + unsigned int src_peril1; + unsigned int src_cam1; + unsigned char res23[0xb4]; + unsigned int src_mask_top; + unsigned char res24[0xc]; + unsigned int src_mask_cam; + unsigned int src_mask_tv; + unsigned char res25[0xc]; + unsigned int src_mask_lcd; + unsigned int src_mask_isp; + unsigned int src_mask_maudio; + unsigned int src_mask_fsys; + unsigned char res26[0xc]; + unsigned int src_mask_peril0; + unsigned int src_mask_peril1; + unsigned char res27[0xb8]; + unsigned int mux_stat_top0; + unsigned int mux_stat_top1; + unsigned char res28[0x10]; + unsigned int mux_stat_mfc; + unsigned int mux_stat_g3d; + unsigned char res29[0x28]; + unsigned int mux_stat_cam1; + unsigned char res30[0xb4]; + unsigned int div_top; + unsigned char res31[0xc]; + unsigned int div_cam; + unsigned int div_tv; + unsigned int div_mfc; + unsigned int div_g3d; + unsigned char res32[0x4]; + unsigned int div_lcd; + unsigned int div_isp; + unsigned int div_maudio; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned int div_fsys3; + unsigned int div_peril0; + unsigned int div_peril1; + unsigned int div_peril2; + unsigned int div_peril3; + unsigned int div_peril4; + unsigned int div_peril5; + unsigned int div_cam1; + unsigned char res33[0x14]; + unsigned int div2_ratio; + unsigned char res34[0x8c]; + unsigned int div_stat_top; + unsigned char res35[0xc]; + unsigned int div_stat_cam; + unsigned int div_stat_tv; + unsigned int div_stat_mfc; + unsigned int div_stat_g3d; + unsigned char res36[0x4]; + unsigned int div_stat_lcd; + unsigned int div_stat_isp; + unsigned int div_stat_maudio; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned int div_stat_fsys3; + unsigned int div_stat_peril0; + unsigned int div_stat_peril1; + unsigned int div_stat_peril2; + unsigned int div_stat_peril3; + unsigned int div_stat_peril4; + unsigned int div_stat_peril5; + unsigned int div_stat_cam1; + unsigned char res37[0x14]; + unsigned int div2_stat; + unsigned char res38[0x29c]; + unsigned int gate_ip_cam; + unsigned int gate_ip_tv; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned char res39[0x4]; + unsigned int gate_ip_lcd; + unsigned int gate_ip_isp; + unsigned char res40[0x4]; + unsigned int gate_ip_fsys; + unsigned char res41[0x8]; + unsigned int gate_ip_gps; + unsigned int gate_ip_peril; + unsigned char res42[0xc]; + unsigned char res43[0x4]; + unsigned char res44[0xc]; + unsigned int gate_block; + unsigned char res45[0x8c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res46[0x3600]; + unsigned int mpll_lock; + unsigned char res47[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res48[0xf0]; + unsigned int src_dmc; + unsigned char res49[0xfc]; + unsigned int src_mask_dmc; + unsigned char res50[0xfc]; + unsigned int mux_stat_dmc; + unsigned char res51[0xfc]; + unsigned int div_dmc0; + unsigned int div_dmc1; + unsigned char res52[0xf8]; + unsigned int div_stat_dmc0; + unsigned int div_stat_dmc1; + unsigned char res53[0xf8]; + unsigned int gate_bus_dmc0; + unsigned int gate_bus_dmc1; + unsigned char res54[0x1f8]; + unsigned int gate_ip_dmc0; + unsigned int gate_ip_dmc1; + unsigned char res55[0xf8]; + unsigned int clkout_cmu_dmc; + unsigned int clkout_cmu_dmc_div_stat; + unsigned char res56[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res57[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res58[0x18]; + unsigned int dvcidx_map; + unsigned char res59[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res60[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res61[0x8]; + unsigned int dmc_freq_ctrl; + unsigned int dmc_pause_ctrl; + unsigned int dddrphy_lock_ctrl; + unsigned int c2c_state; + unsigned char res62[0x2f60]; + unsigned int apll_lock; + unsigned char res63[0x8]; + unsigned char res64[0xf4]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res65[0xf8]; + unsigned int src_cpu; + unsigned char res66[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res67[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res68[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res69[0x2f8]; + unsigned int clk_gate_ip_cpu; + unsigned char res70[0xfc]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res71[0x5f8]; + unsigned int armclk_stopctrl; + unsigned int atclk_stopctrl; + unsigned char res72[0x10]; + unsigned char res73[0x8]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res74[0xd8]; + unsigned int apll_con0_l8; + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res75[0xdc]; + unsigned int apll_con1_l8; + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res76[0xe0]; + unsigned int div_iem_l8; + unsigned int div_iem_l7; + unsigned int div_iem_l6; + unsigned int div_iem_l5; + unsigned int div_iem_l4; + unsigned int div_iem_l3; + unsigned int div_iem_l2; + unsigned int div_iem_l1; + unsigned char res77[0xe0]; + unsigned int l2_status; + unsigned char res78[0xc]; + unsigned int cpu_status; + unsigned char res79[0xc]; + unsigned int ptm_status; + unsigned char res80[0x2edc]; + unsigned int div_isp0; + unsigned int div_isp1; + unsigned char res81[0xf8]; + unsigned int div_stat_isp0; + unsigned int div_stat_isp1; + unsigned char res82[0x3f8]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res83[0x1f8]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_ispd_div_stat; + unsigned char res84[0xf8]; + unsigned int cmu_isp_spar0; + unsigned int cmu_isp_spar1; + unsigned int cmu_isp_spar2; + unsigned int cmu_isp_spar3; +}; + +struct exynos5_clock { + unsigned int apll_lock; + unsigned char res1[0xfc]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res2[0xf8]; + unsigned int src_cpu; + unsigned char res3[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res4[0xfc]; + unsigned int div_cpu0; + unsigned int div_cpu1; + unsigned char res5[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res6[0x1f8]; + unsigned int gate_sclk_cpu; + unsigned char res7[0x1fc]; + unsigned int clkout_cmu_cpu; + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res8[0x5f8]; + unsigned int armclk_stopctrl; + unsigned char res9[0x0c]; + unsigned int parityfail_status; + unsigned int parityfail_clear; + unsigned char res10[0x8]; + unsigned int pwr_ctrl; + unsigned int pwr_ctr2; + unsigned char res11[0xd8]; + unsigned int apll_con0_l8; + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res12[0xdc]; + unsigned int apll_con1_l8; + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res13[0xe0]; + unsigned int div_iem_l8; + unsigned int div_iem_l7; + unsigned int div_iem_l6; + unsigned int div_iem_l5; + unsigned int div_iem_l4; + unsigned int div_iem_l3; + unsigned int div_iem_l2; + unsigned int div_iem_l1; + unsigned char res14[0x2ce0]; + unsigned int mpll_lock; + unsigned char res15[0xfc]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res16[0xf8]; + unsigned int src_core0; + unsigned int src_core1; + unsigned char res17[0xf8]; + unsigned int src_mask_core; + unsigned char res18[0x100]; + unsigned int mux_stat_core1; + unsigned char res19[0xf8]; + unsigned int div_core0; + unsigned int div_core1; + unsigned int div_sysrgt; + unsigned char res20[0xf4]; + unsigned int div_stat_core0; + unsigned int div_stat_core1; + unsigned int div_stat_sysrgt; + unsigned char res21[0x2f4]; + unsigned int gate_ip_core; + unsigned int gate_ip_sysrgt; + unsigned char res22[0x8]; + unsigned int c2c_monitor; + unsigned char res23[0xec]; + unsigned int clkout_cmu_core; + unsigned int clkout_cmu_core_div_stat; + unsigned char res24[0x5f8]; + unsigned int dcgidx_map0; + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res25[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res26[0x18]; + unsigned int dvcidx_map; + unsigned char res27[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res28[0x18]; + unsigned int dvsemclk_en; + unsigned int maxperf; + unsigned char res29[0xf78]; + unsigned int c2c_config; + unsigned char res30[0x24fc]; + unsigned int div_acp; + unsigned char res31[0xfc]; + unsigned int div_stat_acp; + unsigned char res32[0x1fc]; + unsigned int gate_ip_acp; + unsigned char res33[0xfc]; + unsigned int div_syslft; + unsigned char res34[0xc]; + unsigned int div_stat_syslft; + unsigned char res35[0x1c]; + unsigned int gate_ip_syslft; + unsigned char res36[0xcc]; + unsigned int clkout_cmu_acp; + unsigned int clkout_cmu_acp_div_stat; + unsigned char res37[0x8]; + unsigned int ufmc_config; + unsigned char res38[0x38ec]; + unsigned int div_isp0; + unsigned int div_isp1; + unsigned int div_isp2; + unsigned char res39[0xf4]; + unsigned int div_stat_isp0; + unsigned int div_stat_isp1; + unsigned int div_stat_isp2; + unsigned char res40[0x3f4]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res41[0xf8]; + unsigned int gate_sclk_isp; + unsigned char res42[0xc]; + unsigned int mcuisp_pwr_ctrl; + unsigned char res43[0xec]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_isp_div_stat; + unsigned char res44[0x3618]; + unsigned int cpll_lock; + unsigned char res45[0xc]; + unsigned int epll_lock; + unsigned char res46[0xc]; + unsigned int vpll_lock; + unsigned char res47[0xc]; + unsigned int gpll_lock; + unsigned char res48[0xcc]; + unsigned int cpll_con0; + unsigned int cpll_con1; + unsigned char res49[0x8]; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res50[0x4]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned int vpll_con2; + unsigned char res51[0x4]; + unsigned int gpll_con0; + unsigned int gpll_con1; + unsigned char res52[0xb8]; + unsigned int src_top0; + unsigned int src_top1; + unsigned int src_top2; + unsigned int src_top3; + unsigned int src_gscl; + unsigned char res53[0x8]; + unsigned int src_disp1_0; + unsigned char res54[0x10]; + unsigned int src_mau; + unsigned int src_fsys; + unsigned int src_gen; + unsigned char res55[0x4]; + unsigned int src_peric0; + unsigned int src_peric1; + unsigned char res56[0x18]; + unsigned int sclk_src_isp; + unsigned char res57[0x9c]; + unsigned int src_mask_top; + unsigned char res58[0xc]; + unsigned int src_mask_gscl; + unsigned char res59[0x8]; + unsigned int src_mask_disp1_0; + unsigned char res60[0x4]; + unsigned int src_mask_mau; + unsigned char res61[0x8]; + unsigned int src_mask_fsys; + unsigned int src_mask_gen; + unsigned char res62[0x8]; + unsigned int src_mask_peric0; + unsigned int src_mask_peric1; + unsigned char res63[0x18]; + unsigned int src_mask_isp; + unsigned char res67[0x9c]; + unsigned int mux_stat_top0; + unsigned int mux_stat_top1; + unsigned int mux_stat_top2; + unsigned int mux_stat_top3; + unsigned char res68[0xf0]; + unsigned int div_top0; + unsigned int div_top1; + unsigned char res69[0x8]; + unsigned int div_gscl; + unsigned char res70[0x8]; + unsigned int div_disp1_0; + unsigned char res71[0xc]; + unsigned int div_gen; + unsigned char res72[0x4]; + unsigned int div_mau; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned char res73[0x4]; + unsigned int div_peric0; + unsigned int div_peric1; + unsigned int div_peric2; + unsigned int div_peric3; + unsigned int div_peric4; + unsigned int div_peric5; + unsigned char res74[0x10]; + unsigned int sclk_div_isp; + unsigned char res75[0xc]; + unsigned int div2_ratio0; + unsigned int div2_ratio1; + unsigned char res76[0x8]; + unsigned int div4_ratio; + unsigned char res77[0x6c]; + unsigned int div_stat_top0; + unsigned int div_stat_top1; + unsigned char res78[0x8]; + unsigned int div_stat_gscl; + unsigned char res79[0x8]; + unsigned int div_stat_disp1_0; + unsigned char res80[0xc]; + unsigned int div_stat_gen; + unsigned char res81[0x4]; + unsigned int div_stat_mau; + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned char res82[0x4]; + unsigned int div_stat_peric0; + unsigned int div_stat_peric1; + unsigned int div_stat_peric2; + unsigned int div_stat_peric3; + unsigned int div_stat_peric4; + unsigned int div_stat_peric5; + unsigned char res83[0x10]; + unsigned int sclk_div_stat_isp; + unsigned char res84[0xc]; + unsigned int div2_stat0; + unsigned int div2_stat1; + unsigned char res85[0x8]; + unsigned int div4_stat; + unsigned char res86[0x184]; + unsigned int gate_top_sclk_disp1; + unsigned int gate_top_sclk_gen; + unsigned char res87[0xc]; + unsigned int gate_top_sclk_mau; + unsigned int gate_top_sclk_fsys; + unsigned char res88[0xc]; + unsigned int gate_top_sclk_peric; + unsigned char res89[0x1c]; + unsigned int gate_top_sclk_isp; + unsigned char res90[0xac]; + unsigned int gate_ip_gscl; + unsigned char res91[0x4]; + unsigned int gate_ip_disp1; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned int gate_ip_gen; + unsigned char res92[0xc]; + unsigned int gate_ip_fsys; + unsigned char res93[0x8]; + unsigned int gate_ip_peric; + unsigned char res94[0xc]; + unsigned int gate_ip_peris; + unsigned char res95[0x1c]; + unsigned int gate_block; + unsigned char res96[0x1c]; + unsigned int mcuiop_pwr_ctrl; + unsigned char res97[0x5c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res98[0x37f8]; + unsigned int src_lex; + unsigned char res99[0x1fc]; + unsigned int mux_stat_lex; + unsigned char res100[0xfc]; + unsigned int div_lex; + unsigned char res101[0xfc]; + unsigned int div_stat_lex; + unsigned char res102[0x1fc]; + unsigned int gate_ip_lex; + unsigned char res103[0x1fc]; + unsigned int clkout_cmu_lex; + unsigned int clkout_cmu_lex_div_stat; + unsigned char res104[0x3af8]; + unsigned int div_r0x; + unsigned char res105[0xfc]; + unsigned int div_stat_r0x; + unsigned char res106[0x1fc]; + unsigned int gate_ip_r0x; + unsigned char res107[0x1fc]; + unsigned int clkout_cmu_r0x; + unsigned int clkout_cmu_r0x_div_stat; + unsigned char res108[0x3af8]; + unsigned int div_r1x; + unsigned char res109[0xfc]; + unsigned int div_stat_r1x; + unsigned char res110[0x1fc]; + unsigned int gate_ip_r1x; + unsigned char res111[0x1fc]; + unsigned int clkout_cmu_r1x; + unsigned int clkout_cmu_r1x_div_stat; + unsigned char res112[0x3608]; + unsigned int bpll_lock; + unsigned char res113[0xfc]; + unsigned int bpll_con0; + unsigned int bpll_con1; + unsigned char res114[0xe8]; + unsigned int src_cdrex; + unsigned char res115[0x1fc]; + unsigned int mux_stat_cdrex; + unsigned char res116[0xfc]; + unsigned int div_cdrex; + unsigned char res117[0xfc]; + unsigned int div_stat_cdrex; + unsigned char res118[0x2fc]; + unsigned int gate_ip_cdrex; + unsigned char res119[0x10]; + unsigned int dmc_freq_ctrl; + unsigned char res120[0x4]; + unsigned int drex2_pause; + unsigned char res121[0xe0]; + unsigned int clkout_cmu_cdrex; + unsigned int clkout_cmu_cdrex_div_stat; + unsigned char res122[0x8]; + unsigned int lpddr3phy_ctrl; + unsigned int lpddr3phy_con0; + unsigned int lpddr3phy_con1; + unsigned int lpddr3phy_con2; + unsigned int lpddr3phy_con3; + unsigned int pll_div2_sel; + unsigned char res123[0xf5d8]; +}; + +/* structure for epll configuration used in audio clock configuration */ +struct set_epll_con_val { + unsigned int freq_out; /* frequency out */ + unsigned int en_lock_det; /* enable lock detect */ + unsigned int m_div; /* m divider value */ + unsigned int p_div; /* p divider value */ + unsigned int s_div; /* s divider value */ + unsigned int k_dsm; /* k value of delta signal modulator */ +}; +#endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ +#define TIMEOUT_EPLL_LOCK 1000 + +#define AUDIO_0_RATIO_MASK 0x0f +#define AUDIO_1_RATIO_MASK 0x0f + +#define AUDIO1_SEL_MASK 0xf +#define CLK_SRC_SCLK_EPLL 0x7 + +/* CON0 bit-fields */ +#define EPLL_CON0_MDIV_MASK 0x1ff +#define EPLL_CON0_PDIV_MASK 0x3f +#define EPLL_CON0_SDIV_MASK 0x7 +#define EPLL_CON0_MDIV_SHIFT 16 +#define EPLL_CON0_PDIV_SHIFT 8 +#define EPLL_CON0_SDIV_SHIFT 0 +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 +#define EPLL_CON0_LOCK_DET_EN_MASK 1 + +#define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 +#endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h new file mode 100644 index 0000000..1ff231b --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -0,0 +1,245 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _EXYNOS4_CPU_H +#define _EXYNOS4_CPU_H + +#define DEVICE_NOT_AVAILABLE 0 + +#define EXYNOS_CPU_NAME "Exynos" +#define EXYNOS4_ADDR_BASE 0x10000000 + +/* EXYNOS4 Common*/ +#define EXYNOS4_I2C_SPACING 0x10000 + +#define EXYNOS4_GPIO_PART3_BASE 0x03860000 +#define EXYNOS4_PRO_ID 0x10000000 +#define EXYNOS4_SYSREG_BASE 0x10010000 +#define EXYNOS4_POWER_BASE 0x10020000 +#define EXYNOS4_SWRESET 0x10020400 +#define EXYNOS4_CLOCK_BASE 0x10030000 +#define EXYNOS4_SYSTIMER_BASE 0x10050000 +#define EXYNOS4_WATCHDOG_BASE 0x10060000 +#define EXYNOS4_TZPC_BASE 0x10110000 +#define EXYNOS4_MIU_BASE 0x10600000 +#define EXYNOS4_DMC_CTRL_BASE 0x10400000 +#define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4_FIMD_BASE 0x11C00000 +#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 +#define EXYNOS4_USBOTG_BASE 0x12480000 +#define EXYNOS4_MMC_BASE 0x12510000 +#define EXYNOS4_SROMC_BASE 0x12570000 +#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 +#define EXYNOS4_USBPHY_BASE 0x125B0000 +#define EXYNOS4_UART_BASE 0x13800000 +#define EXYNOS4_I2C_BASE 0x13860000 +#define EXYNOS4_ADC_BASE 0x13910000 +#define EXYNOS4_SPI_BASE 0x13920000 +#define EXYNOS4_PWMTIMER_BASE 0x139D0000 +#define EXYNOS4_MODEM_BASE 0x13A00000 +#define EXYNOS4_USBPHY_CONTROL 0x10020704 +#define EXYNOS4_I2S_BASE 0xE2100000 + +#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS4X12 */ +#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 +#define EXYNOS4X12_PRO_ID 0x10000000 +#define EXYNOS4X12_SYSREG_BASE 0x10010000 +#define EXYNOS4X12_POWER_BASE 0x10020000 +#define EXYNOS4X12_SWRESET 0x10020400 +#define EXYNOS4X12_USBPHY_CONTROL 0x10020704 +#define EXYNOS4X12_CLOCK_BASE 0x10030000 +#define EXYNOS4X12_SYSTIMER_BASE 0x10050000 +#define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_TZPC_BASE 0x10110000 +#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 +#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_FIMD_BASE 0x11C00000 +#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 +#define EXYNOS4X12_USBOTG_BASE 0x12480000 +#define EXYNOS4X12_MMC_BASE 0x12510000 +#define EXYNOS4X12_SROMC_BASE 0x12570000 +#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 +#define EXYNOS4X12_USBPHY_BASE 0x125B0000 +#define EXYNOS4X12_UART_BASE 0x13800000 +#define EXYNOS4X12_I2C_BASE 0x13860000 +#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 + +#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE + +/* EXYNOS5 Common*/ +#define EXYNOS5_I2C_SPACING 0x10000 + +#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_PRO_ID 0x10000000 +#define EXYNOS5_CLOCK_BASE 0x10010000 +#define EXYNOS5_POWER_BASE 0x10040000 +#define EXYNOS5_SWRESET 0x10040400 +#define EXYNOS5_SYSREG_BASE 0x10050000 +#define EXYNOS5_TZPC_BASE 0x10100000 +#define EXYNOS5_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_DMC_PHY_BASE 0x10C00000 +#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 +#define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 +#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 +#define EXYNOS5_USBPHY_BASE 0x12130000 +#define EXYNOS5_USBOTG_BASE 0x12140000 +#define EXYNOS5_MMC_BASE 0x12200000 +#define EXYNOS5_SROMC_BASE 0x12250000 +#define EXYNOS5_UART_BASE 0x12C00000 +#define EXYNOS5_I2C_BASE 0x12C60000 +#define EXYNOS5_SPI_BASE 0x12D20000 +#define EXYNOS5_I2S_BASE 0x12D60000 +#define EXYNOS5_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5_SPI_ISP_BASE 0x131A0000 +#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_FIMD_BASE 0x14400000 +#define EXYNOS5_DP_BASE 0x145B0000 + +#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE + +#ifndef __ASSEMBLY__ +#include <asm/io.h> +/* CPU detection macros */ +extern unsigned int s5p_cpu_id; +extern unsigned int s5p_cpu_rev; + +static inline int s5p_get_cpu_rev(void) +{ + return s5p_cpu_rev; +} + +static inline void s5p_set_cpu_id(void) +{ + unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + + switch (pro_id) { + case 0x200: + /* Exynos4210 EVT0 */ + s5p_cpu_id = 0x4210; + s5p_cpu_rev = 0; + break; + case 0x210: + /* Exynos4210 EVT1 */ + s5p_cpu_id = 0x4210; + break; + case 0x412: + /* Exynos4412 */ + s5p_cpu_id = 0x4412; + break; + case 0x520: + /* Exynos5250 */ + s5p_cpu_id = 0x5250; + break; + } +} + +static inline char *s5p_get_cpu_name(void) +{ + return EXYNOS_CPU_NAME; +} + +#define IS_SAMSUNG_TYPE(type, id) \ +static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \ +{ \ + return (s5p_cpu_id >> 12) == id; \ +} + +IS_SAMSUNG_TYPE(exynos4, 0x4) +IS_SAMSUNG_TYPE(exynos5, 0x5) + +#define IS_EXYNOS_TYPE(type, id) \ +static inline int __attribute__((no_instrument_function)) \ + proid_is_##type(void) \ +{ \ + return s5p_cpu_id == id; \ +} + +IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos4412, 0x4412) +IS_EXYNOS_TYPE(exynos5250, 0x5250) + +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int __attribute__((no_instrument_function)) \ + samsung_get_base_##device(void) \ +{ \ + if (cpu_is_exynos4()) { \ + if (proid_is_exynos4412()) \ + return EXYNOS4X12_##base; \ + return EXYNOS4_##base; \ + } else if (cpu_is_exynos5()) { \ + return EXYNOS5_##base; \ + } \ + return 0; \ +} + +SAMSUNG_BASE(adc, ADC_BASE) +SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) +SAMSUNG_BASE(dp, DP_BASE) +SAMSUNG_BASE(sysreg, SYSREG_BASE) +SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(i2c, I2C_BASE) +SAMSUNG_BASE(i2s, I2S_BASE) +SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) +SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) +SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) +SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) +SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) +SAMSUNG_BASE(pro_id, PRO_ID) +SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(modem, MODEM_BASE) +SAMSUNG_BASE(sromc, SROMC_BASE) +SAMSUNG_BASE(swreset, SWRESET) +SAMSUNG_BASE(timer, PWMTIMER_BASE) +SAMSUNG_BASE(uart, UART_BASE) +SAMSUNG_BASE(usb_phy, USBPHY_BASE) +SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) +SAMSUNG_BASE(usb_otg, USBOTG_BASE) +SAMSUNG_BASE(watchdog, WATCHDOG_BASE) +SAMSUNG_BASE(power, POWER_BASE) +SAMSUNG_BASE(spi, SPI_BASE) +SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) +SAMSUNG_BASE(tzpc, TZPC_BASE) +SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) +SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) +#endif + +#endif /* _EXYNOS4_CPU_H */ diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h new file mode 100644 index 0000000..f65c676 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -0,0 +1,320 @@ +#ifndef __DMC_H__ +#define __DMC_H__ + +#ifndef __ASSEMBLY__ +struct exynos4_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int memconfig0; + unsigned int memconfig1; + unsigned int directcmd; + unsigned int prechconfig; + unsigned int phycontrol0; + unsigned int phycontrol1; + unsigned int phycontrol2; + unsigned int phycontrol3; + unsigned int pwrdnconfig; + unsigned char res1[0x4]; + unsigned int timingref; + unsigned int timingrow; + unsigned int timingdata; + unsigned int timingpower; + unsigned int phystatus; + unsigned int phyzqcontrol; + unsigned int chip0status; + unsigned int chip1status; + unsigned int arefstatus; + unsigned int mrstatus; + unsigned int phytest0; + unsigned int phytest1; + unsigned int qoscontrol0; + unsigned int qosconfig0; + unsigned int qoscontrol1; + unsigned int qosconfig1; + unsigned int qoscontrol2; + unsigned int qosconfig2; + unsigned int qoscontrol3; + unsigned int qosconfig3; + unsigned int qoscontrol4; + unsigned int qosconfig4; + unsigned int qoscontrol5; + unsigned int qosconfig5; + unsigned int qoscontrol6; + unsigned int qosconfig6; + unsigned int qoscontrol7; + unsigned int qosconfig7; + unsigned int qoscontrol8; + unsigned int qosconfig8; + unsigned int qoscontrol9; + unsigned int qosconfig9; + unsigned int qoscontrol10; + unsigned int qosconfig10; + unsigned int qoscontrol11; + unsigned int qosconfig11; + unsigned int qoscontrol12; + unsigned int qosconfig12; + unsigned int qoscontrol13; + unsigned int qosconfig13; + unsigned int qoscontrol14; + unsigned int qosconfig14; + unsigned int qoscontrol15; + unsigned int qosconfig15; + unsigned int qostimeout0; + unsigned int qostimeout1; + unsigned char res2[0x8]; + unsigned int ivcontrol; + unsigned char res3[0x8]; + unsigned int perevconfig; + unsigned char res4[0xDF00]; + unsigned int pmnc_ppc_a; + unsigned char res5[0xC]; + unsigned int cntens_ppc_a; + unsigned char res6[0xC]; + unsigned int cntenc_ppc_a; + unsigned char res7[0xC]; + unsigned int intens_ppc_a; + unsigned char res8[0xC]; + unsigned int intenc_ppc_a; + unsigned char res9[0xC]; + unsigned int flag_ppc_a; + unsigned char res10[0xAC]; + unsigned int ccnt_ppc_a; + unsigned char res11[0xC]; + unsigned int pmcnt0_ppc_a; + unsigned char res12[0xC]; + unsigned int pmcnt1_ppc_a; + unsigned char res13[0xC]; + unsigned int pmcnt2_ppc_a; + unsigned char res14[0xC]; + unsigned int pmcnt3_ppc_a; + unsigned char res15[0xEBC]; + unsigned int pmnc_ppc_m; + unsigned char res16[0xC]; + unsigned int cntens_ppc_m; + unsigned char res17[0xC]; + unsigned int cntenc_ppc_m; + unsigned char res18[0xC]; + unsigned int intens_ppc_m; + unsigned char res19[0xC]; + unsigned int intenc_ppc_m; + unsigned char res20[0xC]; + unsigned int flag_ppc_m; + unsigned char res21[0xAC]; + unsigned int ccnt_ppc_m; + unsigned char res22[0xC]; + unsigned int pmcnt0_ppc_m; + unsigned char res23[0xC]; + unsigned int pmcnt1_ppc_m; + unsigned char res24[0xC]; + unsigned int pmcnt2_ppc_m; + unsigned char res25[0xC]; + unsigned int pmcnt3_ppc_m; +}; + +struct exynos5_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int memconfig0; + unsigned int memconfig1; + unsigned int directcmd; + unsigned int prechconfig; + unsigned int phycontrol0; + unsigned char res1[0xc]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow; + unsigned int timingdata; + unsigned int timingpower; + unsigned int phystatus; + unsigned char res2[0x4]; + unsigned int chipstatus_ch0; + unsigned int chipstatus_ch1; + unsigned char res3[0x4]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x14]; + unsigned int ivcontrol; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x8]; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res22[0xc]; + unsigned int wrlvl_config; + unsigned char res23[0xc]; + unsigned int perevcontrol; + unsigned int perev0config; + unsigned int perev1config; + unsigned int perev2config; + unsigned int perev3config; + unsigned char res24[0xdebc]; + unsigned int pmnc_ppc_a; + unsigned char res25[0xc]; + unsigned int cntens_ppc_a; + unsigned char res26[0xc]; + unsigned int cntenc_ppc_a; + unsigned char res27[0xc]; + unsigned int intens_ppc_a; + unsigned char res28[0xc]; + unsigned int intenc_ppc_a; + unsigned char res29[0xc]; + unsigned int flag_ppc_a; + unsigned char res30[0xac]; + unsigned int ccnt_ppc_a; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc_a; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc_a; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc_a; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc_a; +}; + +struct exynos5_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned char res1[4]; + unsigned int phy_con6; + unsigned char res2[4]; + unsigned int phy_con8; + unsigned int phy_con9; + unsigned int phy_con10; + unsigned char res3[4]; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned int phy_con35; + unsigned int phy_con36; + unsigned int phy_con37; + unsigned int phy_con38; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + +enum ddr_mode { + DDR_MODE_DDR2, + DDR_MODE_DDR3, + DDR_MODE_LPDDR2, + DDR_MODE_LPDDR3, + + DDR_MODE_COUNT, +}; + +enum mem_manuf { + MEM_MANUF_AUTODETECT, + MEM_MANUF_ELPIDA, + MEM_MANUF_SAMSUNG, + + MEM_MANUF_COUNT, +}; + +/* CONCONTROL register fields */ +#define CONCONTROL_DFI_INIT_START_SHIFT 28 +#define CONCONTROL_RD_FETCH_SHIFT 12 +#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) +#define CONCONTROL_AREF_EN_SHIFT 5 + +/* PRECHCONFIG register field */ +#define PRECHCONFIG_TP_CNT_SHIFT 24 + +/* PWRDNCONFIG register field */ +#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 +#define PWRDNCONFIG_DSREF_CYC_SHIFT 16 + +/* PHY_CON0 register fields */ +#define PHY_CON0_T_WRRDCMD_SHIFT 17 +#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) +#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 + +/* PHY_CON1 register fields */ +#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 + +/* PHY_CON12 register fields */ +#define PHY_CON12_CTRL_START_POINT_SHIFT 24 +#define PHY_CON12_CTRL_INC_SHIFT 16 +#define PHY_CON12_CTRL_FORCE_SHIFT 8 +#define PHY_CON12_CTRL_START_SHIFT 6 +#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) +#define PHY_CON12_CTRL_DLL_ON_SHIFT 5 +#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) +#define PHY_CON12_CTRL_REF_SHIFT 1 + +/* PHY_CON16 register fields */ +#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 +#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) + +#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 +#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) + +#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) + +/* PHY_CON42 register fields */ +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) + +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 +#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) + +#endif +#endif diff --git a/arch/arm/include/asm/arch-exynos/dp.h b/arch/arm/include/asm/arch-exynos/dp.h new file mode 100644 index 0000000..69c65f7 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dp.h @@ -0,0 +1,751 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_DP_H_ +#define __ASM_ARM_ARCH_DP_H_ + +#ifndef __ASSEMBLY__ + +struct exynos_dp { + unsigned char res1[0x10]; + unsigned int tx_version; + unsigned int tx_sw_reset; + unsigned int func_en1; + unsigned int func_en2; + unsigned int video_ctl1; + unsigned int video_ctl2; + unsigned int video_ctl3; + unsigned int video_ctl4; + unsigned int color_blue_cb; + unsigned int color_green_y; + unsigned int color_red_cr; + unsigned int video_ctl8; + unsigned char res2[0x4]; + unsigned int video_ctl10; + unsigned int total_ln_cfg_l; + unsigned int total_ln_cfg_h; + unsigned int active_ln_cfg_l; + unsigned int active_ln_cfg_h; + unsigned int vfp_cfg; + unsigned int vsw_cfg; + unsigned int vbp_cfg; + unsigned int total_pix_cfg_l; + unsigned int total_pix_cfg_h; + unsigned int active_pix_cfg_l; + unsigned int active_pix_cfg_h; + unsigned int hfp_cfg_l; + unsigned int hfp_cfg_h; + unsigned int hsw_cfg_l; + unsigned int hsw_cfg_h; + unsigned int hbp_cfg_l; + unsigned int hbp_cfg_h; + unsigned int video_status; + unsigned int total_ln_sta_l; + unsigned int total_ln_sta_h; + unsigned int active_ln_sta_l; + unsigned int active_ln_sta_h; + + unsigned int vfp_sta; + unsigned int vsw_sta; + unsigned int vbp_sta; + + unsigned int total_pix_sta_l; + unsigned int total_pix_sta_h; + unsigned int active_pix_sta_l; + unsigned int active_pix_sta_h; + + unsigned int hfp_sta_l; + unsigned int hfp_sta_h; + unsigned int hsw_sta_l; + unsigned int hsw_sta_h; + unsigned int hbp_sta_l; + unsigned int hbp_sta_h; + + unsigned char res3[0x288]; + + unsigned int lane_map; + unsigned char res4[0x10]; + unsigned int analog_ctl1; + unsigned int analog_ctl2; + unsigned int analog_ctl3; + + unsigned int pll_filter_ctl1; + unsigned int amp_tuning_ctl; + unsigned char res5[0xc]; + + unsigned int aux_hw_retry_ctl; + unsigned char res6[0x2c]; + unsigned int int_state; + unsigned int common_int_sta1; + unsigned int common_int_sta2; + unsigned int common_int_sta3; + unsigned int common_int_sta4; + unsigned char res7[0x8]; + + unsigned int int_sta; + unsigned char res8[0x1c]; + unsigned int int_ctl; + unsigned char res9[0x200]; + unsigned int sys_ctl1; + unsigned int sys_ctl2; + unsigned int sys_ctl3; + unsigned int sys_ctl4; + unsigned int vid_ctl; + unsigned char res10[0x2c]; + unsigned int pkt_send_ctl; + unsigned char res[0x4]; + unsigned int hdcp_ctl; + unsigned char res11[0x34]; + unsigned int link_bw_set; + + unsigned int lane_count_set; + unsigned int training_ptn_set; + unsigned int ln0_link_training_ctl; + unsigned int ln1_link_training_ctl; + unsigned int ln2_link_training_ctl; + unsigned int ln3_link_training_ctl; + unsigned int dn_spread_ctl; + unsigned int hw_link_training_ctl; + unsigned char res12[0x1c]; + + unsigned int debug_ctl; + unsigned int hpd_deglitch_l; + unsigned int hpd_deglitch_h; + + unsigned char res13[0x14]; + unsigned int link_debug_ctl; + + unsigned char res14[0x1c]; + + unsigned int m_vid0; + unsigned int m_vid1; + unsigned int m_vid2; + unsigned int n_vid0; + unsigned int n_vid1; + unsigned int n_vid2; + unsigned int m_vid_mon; + unsigned int pll_ctl; + unsigned int phy_pd; + unsigned int phy_test; + unsigned char res15[0x8]; + + unsigned int video_fifo_thrd; + unsigned char res16[0x8]; + unsigned int audio_margin; + + unsigned int dn_spread_ctl1; + unsigned int dn_spread_ctl2; + unsigned char res17[0x18]; + unsigned int m_cal_ctl; + unsigned int m_vid_gen_filter_th; + unsigned char res18[0x10]; + unsigned int m_aud_gen_filter_th; + unsigned char res50[0x4]; + + unsigned int aux_ch_sta; + unsigned int aux_err_num; + unsigned int aux_ch_defer_ctl; + unsigned int aux_rx_comm; + unsigned int buffer_data_ctl; + + unsigned int aux_ch_ctl1; + unsigned int aux_addr_7_0; + unsigned int aux_addr_15_8; + unsigned int aux_addr_19_16; + unsigned int aux_ch_ctl2; + unsigned char res19[0x18]; + unsigned int buf_data0; + unsigned char res20[0x3c]; + + unsigned int soc_general_ctl; + unsigned char res21[0x8c]; + unsigned int crc_con; + unsigned int crc_result; + unsigned char res22[0x8]; + + unsigned int common_int_mask1; + unsigned int common_int_mask2; + unsigned int common_int_mask3; + unsigned int common_int_mask4; + unsigned int int_sta_mask1; + unsigned int int_sta_mask2; + unsigned int int_sta_mask3; + unsigned int int_sta_mask4; + unsigned int int_sta_mask; + unsigned int crc_result2; + unsigned int scrambler_reset_cnt; + + unsigned int pn_inv; + unsigned int psr_config; + unsigned int psr_command0; + unsigned int psr_command1; + unsigned int psr_crc_mon0; + unsigned int psr_crc_mon1; + + unsigned char res24[0x30]; + unsigned int phy_bist_ctrl; + unsigned char res25[0xc]; + unsigned int phy_ctrl; + unsigned char res26[0x1c]; + unsigned int test_pattern_gen_en; + unsigned int test_pattern_gen_ctrl; +}; + +#endif /* __ASSEMBLY__ */ + +/* For DP VIDEO CTL 1 */ +#define VIDEO_EN_MASK (0x01 << 7) +#define VIDEO_MUTE_MASK (0x01 << 6) + +/* For DP VIDEO CTL 4 */ +#define VIDEO_BIST_MASK (0x1 << 3) + +/* EXYNOS_DP_ANALOG_CTL_1 */ +#define SEL_BG_NEW_BANDGAP (0x0 << 6) +#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6) +#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4) +#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4) +#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4) +#define SWING_A_30PER_G_INCREASE (0x1 << 3) +#define SWING_A_30PER_G_NORMAL (0x0 << 3) + +/* EXYNOS_DP_ANALOG_CTL_2 */ +#define CPREG_BLEED (0x1 << 4) +#define SEL_24M (0x1 << 3) +#define TX_DVDD_BIT_1_0000V (0x3 << 0) +#define TX_DVDD_BIT_1_0625V (0x4 << 0) +#define TX_DVDD_BIT_1_1250V (0x5 << 0) + +/* EXYNOS_DP_ANALOG_CTL_3 */ +#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5) +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5) +#define SEL_CURRENT_DEFAULT (0x0 << 3) +#define VCO_BIT_000_MICRO (0x0 << 0) +#define VCO_BIT_200_MICRO (0x1 << 0) +#define VCO_BIT_300_MICRO (0x2 << 0) +#define VCO_BIT_400_MICRO (0x3 << 0) +#define VCO_BIT_500_MICRO (0x4 << 0) +#define VCO_BIT_600_MICRO (0x5 << 0) +#define VCO_BIT_700_MICRO (0x6 << 0) +#define VCO_BIT_900_MICRO (0x7 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4) +#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4) +#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4) +#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4) +#define TX_CUR1_1X (0x0 << 2) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR1_3X (0x2 << 2) +#define TX_CUR_1_MA (0x0 << 0) +#define TX_CUR_2_MA (0x1 << 0) +#define TX_CUR_3_MA (0x2 << 0) +#define TX_CUR_4_MA (0x3 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_2 */ +#define CH3_AMP_0_MV (0x3 << 12) +#define CH2_AMP_0_MV (0x3 << 8) +#define CH1_AMP_0_MV (0x3 << 4) +#define CH0_AMP_0_MV (0x3 << 0) + +/* EXYNOS_DP_PLL_CTL */ +#define DP_PLL_PD (0x1 << 7) +#define DP_PLL_RESET (0x1 << 6) +#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) +#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) +#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) + +/* EXYNOS_DP_INT_CTL */ +#define SOFT_INT_CTRL (0x1 << 2) +#define INT_POL (0x1 << 0) + +/* DP TX SW RESET */ +#define RESET_DP_TX (0x01 << 0) + +/* DP FUNC_EN_1 */ +#define MASTER_VID_FUNC_EN_N (0x1 << 7) +#define SLAVE_VID_FUNC_EN_N (0x1 << 5) +#define AUD_FIFO_FUNC_EN_N (0x1 << 4) +#define AUD_FUNC_EN_N (0x1 << 3) +#define HDCP_FUNC_EN_N (0x1 << 2) +#define CRC_FUNC_EN_N (0x1 << 1) +#define SW_FUNC_EN_N (0x1 << 0) + +/* DP FUNC_EN_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* EXYNOS_DP_PHY_PD */ +#define PHY_PD (0x1 << 5) +#define AUX_PD (0x1 << 4) +#define CH3_PD (0x1 << 3) +#define CH2_PD (0x1 << 2) +#define CH1_PD (0x1 << 1) +#define CH0_PD (0x1 << 0) + +/* EXYNOS_DP_COMMON_INT_STA_1 */ +#define VSYNC_DET (0x1 << 7) +#define PLL_LOCK_CHG (0x1 << 6) +#define SPDIF_ERR (0x1 << 5) +#define SPDIF_UNSTBL (0x1 << 4) +#define VID_FORMAT_CHG (0x1 << 3) +#define AUD_CLK_CHG (0x1 << 2) +#define VID_CLK_CHG (0x1 << 1) +#define SW_INT (0x1 << 0) + +/* EXYNOS_DP_DEBUG_CTL */ +#define PLL_LOCK (0x1 << 4) +#define F_PLL_LOCK (0x1 << 3) +#define PLL_LOCK_CTRL (0x1 << 2) + +/* EXYNOS_DP_FUNC_EN_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* EXYNOS_DP_COMMON_INT_STA_4 */ +#define PSR_ACTIVE (0x1 << 7) +#define PSR_INACTIVE (0x1 << 6) +#define SPDIF_BI_PHASE_ERR (0x1 << 5) +#define HOTPLUG_CHG (0x1 << 2) +#define HPD_LOST (0x1 << 1) +#define PLUG (0x1 << 0) + +/* EXYNOS_DP_INT_STA */ +#define INT_HPD (0x1 << 6) +#define HW_TRAINING_FINISH (0x1 << 5) +#define RPLY_RECEIV (0x1 << 1) +#define AUX_ERR (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* EXYNOS_DP_AUX_HW_RETRY_CTL */ +#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) +#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) +#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) +#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) +#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) +#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) +#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) + +/* EXYNOS_DP_AUX_CH_DEFER_CTL */ +#define DEFER_CTRL_EN (0x1 << 7) +#define DEFER_COUNT(x) (((x) & 0x7f) << 0) + +#define COMMON_INT_MASK_1 (0) +#define COMMON_INT_MASK_2 (0) +#define COMMON_INT_MASK_3 (0) +#define COMMON_INT_MASK_4 (0) +#define INT_STA_MASK (0) + +/* EXYNOS_DP_BUFFER_DATA_CTL */ +#define BUF_CLR (0x1 << 7) +#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) + +/* EXYNOS_DP_AUX_ADDR_7_0 */ +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) + +/* EXYNOS_DP_AUX_ADDR_15_8 */ +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) + +/* EXYNOS_DP_AUX_ADDR_19_16 */ +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) + +/* EXYNOS_DP_AUX_CH_CTL_1 */ +#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) +#define AUX_TX_COMM_MASK (0xf << 0) +#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) +#define AUX_TX_COMM_MOT (0x1 << 2) +#define AUX_TX_COMM_WRITE (0x0 << 0) +#define AUX_TX_COMM_READ (0x1 << 0) + +/* EXYNOS_DP_AUX_CH_CTL_2 */ +#define ADDR_ONLY (0x1 << 1) +#define AUX_EN (0x1 << 0) + +/* EXYNOS_DP_AUX_CH_STA */ +#define AUX_BUSY (0x1 << 4) +#define AUX_STATUS_MASK (0xf << 0) + +/* EXYNOS_DP_AUX_RX_COMM */ +#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) +#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) + +/* EXYNOS_DP_PHY_TEST */ +#define MACRO_RST (0x1 << 5) +#define CH1_TEST (0x1 << 1) +#define CH0_TEST (0x1 << 0) + +/* EXYNOS_DP_TRAINING_PTN_SET */ +#define SCRAMBLER_TYPE (0x1 << 9) +#define HW_LINK_TRAINING_PATTERN (0x1 << 8) +#define SCRAMBLING_DISABLE (0x1 << 5) +#define SCRAMBLING_ENABLE (0x0 << 5) +#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) +#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) +#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) +#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) +#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) +#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) + +/* EXYNOS_DP_TOTAL_LINE_CFG */ +#define TOTAL_LINE_CFG_L(x) ((x) & 0xff) +#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff) +#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff) +#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff) +#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff) +#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) +#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff) +#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) + +#define H_F_PORCH_CFG_L(x) ((x) & 0xff) +#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) +#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff) +#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) +#define H_B_PORCH_CFG_L(x) ((x) & 0xff) +#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) + +/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5) +#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_0_SHIFT (3) +#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2) +#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5) +#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_1_SHIFT (3) +#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2) +#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5) +#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_2_SHIFT (3) +#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2) +#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */ +#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5) +#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3) +#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3) +#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_3_SHIFT (3) +#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3) +#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3) +#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2) +#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0) +#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0) +#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3) +#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0) +#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_10 */ +#define FORMAT_SEL (0x1 << 4) +#define INTERACE_SCAN_CFG (0x1 << 2) +#define INTERACE_SCAN_CFG_SHIFT (2) +#define VSYNC_POLARITY_CFG (0x1 << 1) +#define V_S_POLARITY_CFG_SHIFT (1) +#define HSYNC_POLARITY_CFG (0x1 << 0) +#define H_S_POLARITY_CFG_SHIFT (0) + +/* EXYNOS_DP_SOC_GENERAL_CTL */ +#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) +#define AUDIO_MODE_MASTER_MODE (0x0 << 8) +#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) +#define VIDEO_MASTER_CLK_SEL (0x1 << 2) +#define VIDEO_MASTER_MODE_EN (0x1 << 1) +#define VIDEO_MODE_MASK (0x1 << 0) +#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) +#define VIDEO_MODE_MASTER_MODE (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_1 */ +#define VIDEO_EN (0x1 << 7) +#define HDCP_VIDEO_MUTE (0x1 << 6) + +/* EXYNOS_DP_VIDEO_CTL_2 */ +#define IN_D_RANGE_MASK (0x1 << 7) +#define IN_D_RANGE_SHIFT (7) +#define IN_D_RANGE_CEA (0x1 << 7) +#define IN_D_RANGE_VESA (0x0 << 7) +#define IN_BPC_MASK (0x7 << 4) +#define IN_BPC_SHIFT (4) +#define IN_BPC_12_BITS (0x3 << 4) +#define IN_BPC_10_BITS (0x2 << 4) +#define IN_BPC_8_BITS (0x1 << 4) +#define IN_BPC_6_BITS (0x0 << 4) +#define IN_COLOR_F_MASK (0x3 << 0) +#define IN_COLOR_F_SHIFT (0) +#define IN_COLOR_F_YCBCR444 (0x2 << 0) +#define IN_COLOR_F_YCBCR422 (0x1 << 0) +#define IN_COLOR_F_RGB (0x0 << 0) + +/* EXYNOS_DP_VIDEO_CTL_3 */ +#define IN_YC_COEFFI_MASK (0x1 << 7) +#define IN_YC_COEFFI_SHIFT (7) +#define IN_YC_COEFFI_ITU709 (0x1 << 7) +#define IN_YC_COEFFI_ITU601 (0x0 << 7) +#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_SHIFT (4) +#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) + +/* EXYNOS_DP_TEST_PATTERN_GEN_EN */ +#define TEST_PATTERN_GEN_EN (0x1 << 0) +#define TEST_PATTERN_GEN_DIS (0x0 << 0) + +/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */ +#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0) +#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0) +#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0) + +/* EXYNOS_DP_VIDEO_CTL_4 */ +#define BIST_EN (0x1 << 3) +#define BIST_WIDTH_MASK (0x1 << 2) +#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2) +#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2) +#define BIST_TYPE_MASK (0x3 << 0) +#define BIST_TYPE_COLOR_BAR (0x0 << 0) +#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0) +#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0) + +/* EXYNOS_DP_SYS_CTL_1 */ +#define DET_STA (0x1 << 2) +#define FORCE_DET (0x1 << 1) +#define DET_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_2 */ +#define CHA_CRI(x) (((x) & 0xf) << 4) +#define CHA_STA (0x1 << 2) +#define FORCE_CHA (0x1 << 1) +#define CHA_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* EXYNOS_DP_SYS_CTL_4 */ +#define FIX_M_AUD (0x1 << 4) +#define ENHANCED (0x1 << 3) +#define FIX_M_VID (0x1 << 2) +#define M_VID_UPDATE_CTRL (0x3 << 0) + +/* EXYNOS_M_VID_X */ +#define M_VID0_CFG(x) ((x) & 0xff) +#define M_VID1_CFG(x) (((x) >> 8) & 0xff) +#define M_VID2_CFG(x) (((x) >> 16) & 0xff) + +/* EXYNOS_M_VID_X */ +#define N_VID0_CFG(x) ((x) & 0xff) +#define N_VID1_CFG(x) (((x) >> 8) & 0xff) +#define N_VID2_CFG(x) (((x) >> 16) & 0xff) + +/* DPCD_TRAINING_PATTERN_SET */ +#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) +#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) +#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) +#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) +#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) + +/* Definition for DPCD Register */ +#define DPCD_DPCD_REV (0x0000) +#define DPCD_MAX_LINK_RATE (0x0001) +#define DPCD_MAX_LANE_COUNT (0x0002) +#define DPCD_LINK_BW_SET (0x0100) +#define DPCD_LANE_COUNT_SET (0x0101) +#define DPCD_TRAINING_PATTERN_SET (0x0102) +#define DPCD_TRAINING_LANE0_SET (0x0103) +#define DPCD_LANE0_1_STATUS (0x0202) +#define DPCD_LN_ALIGN_UPDATED (0x0204) +#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) +#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) +#define DPCD_TEST_REQUEST (0x0218) +#define DPCD_TEST_RESPONSE (0x0260) +#define DPCD_TEST_EDID_CHECKSUM (0x0261) +#define DPCD_SINK_POWER_STATE (0x0600) + +/* DPCD_TEST_REQUEST */ +#define DPCD_TEST_EDID_READ (0x1 << 2) + +/* DPCD_TEST_RESPONSE */ +#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) + +/* DPCD_SINK_POWER_STATE */ +#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) +#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) + +/* I2C EDID Chip ID, Slave Address */ +#define I2C_EDID_DEVICE_ADDR (0x50) +#define I2C_E_EDID_DEVICE_ADDR (0x30) +#define EDID_BLOCK_LENGTH (0x80) +#define EDID_HEADER_PATTERN (0x00) +#define EDID_EXTENSION_FLAG (0x7e) +#define EDID_CHECKSUM (0x7f) + +/* DPCD_LANE0_1_STATUS */ +#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6) +#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5) +#define DPCD_LANE1_CR_DONE (0x1 << 4) +#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2) +#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1) +#define DPCD_LANE0_CR_DONE (0x1 << 0) + +/* DPCD_ADJUST_REQUEST_LANE0_1 */ +#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6) +#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6) +#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4) +#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4) +#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2) +#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2) +#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0) + +/* DPCD_ADJUST_REQUEST_LANE2_3 */ +#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6) +#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6) +#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4) +#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4) +#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2) +#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2) +#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0) + +/* DPCD_LANE_COUNT_SET */ +#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) +#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f) + +/* DPCD_LANE_ALIGN__STATUS_UPDATED */ +#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) +#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) +#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) + +/* DPCD_TRAINING_LANE0_SET */ +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3) +#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0) +#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0) + +#define DPCD_REQ_ADJ_SWING (0x00) +#define DPCD_REQ_ADJ_EMPHASIS (0x01) + +#define DP_LANE_STAT_CR_DONE (0x01 << 0) +#define DP_LANE_STAT_CE_DONE (0x01 << 1) +#define DP_LANE_STAT_SYM_LOCK (0x01 << 2) + +#endif diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h new file mode 100644 index 0000000..ff16361 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dp_info.h @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DP_INFO_H +#define _DP_INFO_H + +#define msleep(a) udelay(a * 1000) + +#define DP_TIMEOUT_LOOP_COUNT 100 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +#define EXYNOS_DP_SUCCESS 0 + +enum { + DP_DISABLE, + DP_ENABLE, +}; + +struct edp_disp_info { + char *name; + unsigned int h_total; + unsigned int h_res; + unsigned int h_sync_width; + unsigned int h_back_porch; + unsigned int h_front_porch; + unsigned int v_total; + unsigned int v_res; + unsigned int v_sync_width; + unsigned int v_back_porch; + unsigned int v_front_porch; + + unsigned int v_sync_rate; +}; + +struct edp_link_train_info { + unsigned int lt_status; + + unsigned int ep_loop; + unsigned int cr_loop[4]; + +}; + +struct edp_video_info { + unsigned int master_mode; + unsigned int bist_mode; + unsigned int bist_pattern; + + unsigned int h_sync_polarity; + unsigned int v_sync_polarity; + unsigned int interlaced; + + unsigned int color_space; + unsigned int dynamic_range; + unsigned int ycbcr_coeff; + unsigned int color_depth; +}; + +struct edp_device_info { + struct edp_disp_info disp_info; + struct edp_link_train_info lt_info; + struct edp_video_info video_info; + + /*below info get from panel during training*/ + unsigned char lane_bw; + unsigned char lane_cnt; + unsigned char dpcd_rev; + /*support enhanced frame cap */ + unsigned char dpcd_efc; +}; + +enum analog_power_block { + AUX_BLOCK, + CH0_BLOCK, + CH1_BLOCK, + CH2_BLOCK, + CH3_BLOCK, + ANALOG_TOTAL, + POWER_ALL +}; + +enum pll_status { + PLL_UNLOCKED = 0, + PLL_LOCKED +}; + +enum { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +enum { + VESA, + CEA +}; + +enum { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +enum { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +enum { + DP_LANE_BW_1_62 = 0x06, + DP_LANE_BW_2_70 = 0x0a, +}; + +enum { + DP_LANE_CNT_1 = 1, + DP_LANE_CNT_2 = 2, + DP_LANE_CNT_4 = 4, +}; + +enum { + DP_DPCD_REV_10 = 0x10, + DP_DPCD_REV_11 = 0x11, +}; + +enum { + DP_LT_NONE, + DP_LT_START, + DP_LT_CR, + DP_LT_ET, + DP_LT_FINISHED, + DP_LT_FAIL, +}; + +enum { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +enum { + PRBS7, + D10_2, + TRAINING_PTN1, + TRAINING_PTN2, + DP_NONE +}; + +enum { + VOLTAGE_LEVEL_0, + VOLTAGE_LEVEL_1, + VOLTAGE_LEVEL_2, + VOLTAGE_LEVEL_3, +}; + +enum pattern_type { + NO_PATTERN, + COLOR_RAMP, + BALCK_WHITE_V_LINES, + COLOR_SQUARE, + INVALID_PATTERN, + COLORBAR_32, + COLORBAR_64, + WHITE_GRAY_BALCKBAR_32, + WHITE_GRAY_BALCKBAR_64, + MOBILE_WHITEBAR_32, + MOBILE_WHITEBAR_64 +}; + +enum { + CALCULATED_M, + REGISTER_M +}; + +enum { + VIDEO_TIMING_FROM_CAPTURE, + VIDEO_TIMING_FROM_REGISTER +}; + + +struct exynos_dp_platform_data { + struct edp_device_info *edp_dev_info; +}; + +#ifdef CONFIG_EXYNOS_DP +unsigned int exynos_init_dp(void); +#else +unsigned int exynos_init_dp(void) +{ + return 0; +} +#endif + +void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd); + +#endif /* _DP_INFO_H */ diff --git a/arch/arm/include/asm/arch-exynos/dsim.h b/arch/arm/include/asm/arch-exynos/dsim.h new file mode 100644 index 0000000..e148aca --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dsim.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_DSIM_H_ +#define __ASM_ARM_ARCH_DSIM_H_ + +#ifndef __ASSEMBLY__ + +struct exynos_mipi_dsim { + unsigned int status; + unsigned int swrst; + unsigned int clkctrl; + unsigned int timeout; + unsigned int config; + unsigned int escmode; + unsigned int mdresol; + unsigned int mvporch; + unsigned int mhporch; + unsigned int msync; + unsigned int sdresol; + unsigned int intsrc; + unsigned int intmsk; + unsigned int pkthdr; + unsigned int payload; + unsigned int rxfifo; + unsigned int fifothld; + unsigned int fifoctrl; + unsigned int memacchr; + unsigned int pllctrl; + unsigned int plltmr; + unsigned int phyacchr; + unsigned int phyacchr1; +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Bit Definitions + */ +/* DSIM_STATUS */ +#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_PLL_STABLE (1 << 31) + +/* DSIM_SWRST */ +#define DSIM_FUNCRST (1 << 16) +#define DSIM_SWRST (1 << 0) + +/* EXYNOS_DSIM_TIMEOUT */ +#define DSIM_LPDR_TOUT_SHIFT (0) +#define DSIM_BTA_TOUT_SHIFT (16) + +/* EXYNOS_DSIM_CLKCTRL */ +#define DSIM_LANE_ESC_CLKEN_SHIFT (19) +#define DSIM_BYTE_CLKEN_SHIFT (24) +#define DSIM_BYTE_CLK_SRC_SHIFT (25) +#define DSIM_PLL_BYPASS_SHIFT (27) +#define DSIM_ESC_CLKEN_SHIFT (28) +#define DSIM_TX_REQUEST_HSCLK_SHIFT (31) +#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \ + DSIM_LANE_ESC_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT) +#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT) +#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT) + +/* EXYNOS_DSIM_CONFIG */ +#define DSIM_NUM_OF_DATALANE_SHIFT (5) +#define DSIM_SUBPIX_SHIFT (8) +#define DSIM_MAINPIX_SHIFT (12) +#define DSIM_SUBVC_SHIFT (16) +#define DSIM_MAINVC_SHIFT (18) +#define DSIM_HSA_MODE_SHIFT (20) +#define DSIM_HBP_MODE_SHIFT (21) +#define DSIM_HFP_MODE_SHIFT (22) +#define DSIM_HSE_MODE_SHIFT (23) +#define DSIM_AUTO_MODE_SHIFT (24) +#define DSIM_VIDEO_MODE_SHIFT (25) +#define DSIM_BURST_MODE_SHIFT (26) +#define DSIM_EOT_PACKET_SHIFT (28) +#define DSIM_AUTO_FLUSH_SHIFT (29) +#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) + +#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT) + +/* EXYNOS_DSIM_ESCMODE */ +#define DSIM_TX_LPDT_SHIFT (6) +#define DSIM_CMD_LPDT_SHIFT (7) +#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT) +#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT) +#define DSIM_STOP_STATE_CNT_SHIFT (21) +#define DSIM_FORCE_STOP_STATE_SHIFT (20) + +/* EXYNOS_DSIM_MDRESOL */ +#define DSIM_MAIN_STAND_BY (1 << 31) +#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) + +/* EXYNOS_DSIM_MVPORCH */ +#define DSIM_CMD_ALLOW_SHIFT (28) +#define DSIM_STABLE_VFP_SHIFT (16) +#define DSIM_MAIN_VBP_SHIFT (0) +#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT) +#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT) +#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT) + +/* EXYNOS_DSIM_MHPORCH */ +#define DSIM_MAIN_HFP_SHIFT (16) +#define DSIM_MAIN_HBP_SHIFT (0) +#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT) +#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT) + +/* EXYNOS_DSIM_MSYNC */ +#define DSIM_MAIN_VSA_SHIFT (22) +#define DSIM_MAIN_HSA_SHIFT (0) +#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT) +#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT) + +/* EXYNOS_DSIM_SDRESOL */ +#define DSIM_SUB_STANDY_SHIFT (31) +#define DSIM_SUB_VRESOL_SHIFT (16) +#define DSIM_SUB_HRESOL_SHIFT (0) +#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT) +#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT) +#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) + +/* EXYNOS_DSIM_INTSRC */ +#define INTSRC_FRAME_DONE (1 << 24) +#define INTSRC_PLL_STABLE (1 << 31) +#define INTSRC_SWRST_RELEASE (1 << 30) + +/* EXYNOS_DSIM_INTMSK */ +#define INTMSK_FRAME_DONE (1 << 24) + +/* EXYNOS_DSIM_FIFOCTRL */ +#define SFR_HEADER_EMPTY (1 << 22) + +/* EXYNOS_DSIM_PKTHDR */ +#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0) +#define DSIM_PKTHDR_DAT0(x) ((x) << 8) +#define DSIM_PKTHDR_DAT1(x) ((x) << 16) + +/* EXYNOS_DSIM_PHYACCHR */ +#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) +#define DSIM_AFC_CTL_SHIFT (5) +#define DSIM_AFC_EN (1 << 14) + +/* EXYNOS_DSIM_PHYACCHR1 */ +#define DSIM_DPDN_SWAP_DATA_SHIFT (0) + +/* EXYNOS_DSIM_PLLCTRL */ +#define DSIM_SCALER_SHIFT (1) +#define DSIM_MAIN_SHIFT (4) +#define DSIM_PREDIV_SHIFT (13) +#define DSIM_PRECTRL_SHIFT (20) +#define DSIM_PLL_EN_SHIFT (23) +#define DSIM_FREQ_BAND_SHIFT (24) +#define DSIM_ZEROCTRL_SHIFT (28) + +#endif diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h new file mode 100644 index 0000000..3b147b8 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DWMCI_CLKSEL 0x09C +#define DWMCI_SHIFT_0 0x0 +#define DWMCI_SHIFT_1 0x1 +#define DWMCI_SHIFT_2 0x2 +#define DWMCI_SHIFT_3 0x3 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h new file mode 100644 index 0000000..8aeff8a --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -0,0 +1,66 @@ +/* + * SAMSUNG EXYNOS USB HOST EHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam <gautam.vivek@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_ARM_ARCH_EHCI_H__ +#define __ASM_ARM_ARCH_EHCI_H__ + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct exynos_usb_phy { + unsigned int usbphyctrl0; + unsigned int usbphytune0; + unsigned int reserved1[2]; + unsigned int hsicphyctrl1; + unsigned int hsicphytune1; + unsigned int reserved2[2]; + unsigned int hsicphyctrl2; + unsigned int hsicphytune2; + unsigned int reserved3[2]; + unsigned int ehcictrl; + unsigned int ohcictrl; + unsigned int usbotgsys; + unsigned int reserved4; + unsigned int usbotgtune; +}; + +/* Switch on the VBUS power. */ +int board_usb_vbus_init(void); + +#endif /* __ASM_ARM_ARCH_EHCI_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h new file mode 100644 index 0000000..01445af --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/fb.h @@ -0,0 +1,471 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aint with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_FB_H_ +#define __ASM_ARM_ARCH_FB_H_ + +#ifndef __ASSEMBLY__ +struct exynos_fb { + unsigned int vidcon0; + unsigned int vidcon1; + unsigned int vidcon2; + unsigned int vidcon3; + unsigned int vidtcon0; + unsigned int vidtcon1; + unsigned int vidtcon2; + unsigned int vidtcon3; + unsigned int wincon0; + unsigned int wincon1; + unsigned int wincon2; + unsigned int wincon3; + unsigned int wincon4; + + unsigned int winshmap; + unsigned int res1; + + unsigned int winchmap2; + unsigned int vidosd0a; + unsigned int vidosd0b; + unsigned int vidosd0c; + unsigned int res2; + + unsigned int vidosd1a; + unsigned int vidosd1b; + unsigned int vidosd1c; + unsigned int vidosd1d; + + unsigned int vidosd2a; + unsigned int vidosd2b; + unsigned int vidosd2c; + unsigned int vidosd2d; + + unsigned int vidosd3a; + unsigned int vidosd3b; + unsigned int vidosd3c; + unsigned int res3; + + unsigned int vidosd4a; + unsigned int vidosd4b; + unsigned int vidosd4c; + unsigned int res4[5]; + + unsigned int vidw00add0b0; + unsigned int vidw00add0b1; + unsigned int vidw01add0b0; + unsigned int vidw01add0b1; + + unsigned int vidw02add0b0; + unsigned int vidw02add0b1; + unsigned int vidw03add0b0; + unsigned int vidw03add0b1; + unsigned int vidw04add0b0; + unsigned int vidw04add0b1; + unsigned int res5[2]; + + unsigned int vidw00add1b0; + unsigned int vidw00add1b1; + unsigned int vidw01add1b0; + unsigned int vidw01add1b1; + + unsigned int vidw02add1b0; + unsigned int vidw02add1b1; + unsigned int vidw03add1b0; + unsigned int vidw03add1b1; + + unsigned int vidw04add1b0; + unsigned int vidw04add1b1; + unsigned int res7[2]; + + unsigned int vidw00add2; + unsigned int vidw01add2; + unsigned int vidw02add2; + unsigned int vidw03add2; + unsigned int vidw04add2; + unsigned int res8[7]; + + unsigned int vidintcon0; + unsigned int vidintcon1; + unsigned int res9[1]; + + unsigned int w1keycon0; + unsigned int w1keycon1; + unsigned int w2keycon0; + unsigned int w2keycon1; + unsigned int w3keycon0; + unsigned int w3keycon1; + unsigned int w4keycon0; + unsigned int w4keycon1; + + unsigned int w1keyalpha; + unsigned int w2keyalpha; + unsigned int w3keyalpha; + unsigned int w4keyalpha; + + unsigned int dithmode; + unsigned int res10[2]; + + unsigned int win0map; + unsigned int win1map; + unsigned int win2map; + unsigned int win3map; + unsigned int win4map; + unsigned int res11[1]; + + unsigned int wpalcon_h; + unsigned int wpalcon_l; + + unsigned int trigcon; + unsigned int res12[2]; + + unsigned int i80ifcona0; + unsigned int i80ifcona1; + unsigned int i80ifconb0; + unsigned int i80ifconb1; + + unsigned int colorgaincon; + unsigned int res13[2]; + + unsigned int ldi_cmdcon0; + unsigned int ldi_cmdcon1; + unsigned int res14[1]; + + /* To be updated */ + + unsigned char res15[156]; + unsigned int dualrgb; + unsigned char res16[16]; + unsigned int dp_mie_clkcon; +}; +#endif + +/* LCD IF register offset */ +#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0 +#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000 + +static inline unsigned int exynos_fimd_get_base_offset(void) +{ + if (cpu_is_exynos5()) + return EXYNOS5_LCD_IF_BASE_OFFSET; + else + return EXYNOS4_LCD_IF_BASE_OFFSET; +} + +/* + * Register offsets +*/ +#define EXYNOS_WINCON(x) (x * 0x04) +#define EXYNOS_VIDOSD(x) (x * 0x10) +#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08) +#define EXYNOS_BUFFER_SIZE(x) (x * 0x04) + +/* + * Bit Definitions +*/ + +/* VIDCON0 */ +#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30) +#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30) +#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29) +#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29) +#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29) +#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26) +#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26) +#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26) +#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26) +#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) +#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26) +#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17) +#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17) +#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17) +#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17) +#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17) +#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17) +#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16) +#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16) +#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16) +#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) +#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5) +#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5) +#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5) +#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4) +#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4) +#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4) +#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2) +#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2) +#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2) +#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1) +#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1) +#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0) +#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0) + +/* VIDCON1 */ +#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) +#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7) +#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6) +#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6) +#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5) +#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5) +#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4) +#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4) + +/* VIDCON2 */ +#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23) +#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23) +#define EXYNOS_VIDCON2_EN601_MASK (1 << 23) +#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15) +#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15) +#define EXYNOS_VIDCON2_WB_MASK (1 << 15) +#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) +#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) +#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8) +#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8) +#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8) +#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7) +#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7) +#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7) + +/* PRTCON */ +#define EXYNOS_PRTCON_UPDATABLE (0 << 11) +#define EXYNOS_PRTCON_PROTECT (1 << 11) + +/* VIDTCON0 */ +#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) +#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) +#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON1 */ +#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) +#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) +#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON2 */ +#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23) +#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22) + +/* Window 0~4 Control - WINCONx */ +#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) +#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22) +#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22) +#define EXYNOS_WINCON_BUFSEL_0 (0 << 20) +#define EXYNOS_WINCON_BUFSEL_1 (1 << 20) +#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20) +#define EXYNOS_WINCON_BUFSEL_SHIFT (20) +#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19) +#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19) +#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19) +#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18) +#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18) +#define EXYNOS_WINCON_BITSWP_SHIFT (18) +#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17) +#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17) +#define EXYNOS_WINCON_BYTESWP_SHIFT (17) +#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16) +#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16) +#define EXYNOS_WINCON_HAWSWP_SHIFT (16) +#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15) +#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15) +#define EXYNOS_WINCON_WSWP_SHIFT (15) +#define EXYNOS_WINCON_INRGB_RGB (0 << 13) +#define EXYNOS_WINCON_INRGB_YUV (1 << 13) +#define EXYNOS_WINCON_INRGB_MASK (1 << 13) +#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9) +#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9) +#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9) +#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9) +#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7) +#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7) +#define EXYNOS_WINCON_BLD_PLANE (0 << 6) +#define EXYNOS_WINCON_BLD_PIXEL (1 << 6) +#define EXYNOS_WINCON_BLD_MASK (1 << 6) +#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2) +#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2) +#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2) +#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2) +#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2) +#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2) +#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2) +#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2) +#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2) +#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2) +#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2) +#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2) +#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2) +#define EXYNOS_WINCON_BPPMODE_SHIFT (2) +#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1) +#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1) +#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1) +#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0) +#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0) + +/* WINCON1 special */ +#define EXYNOS_WINCON1_VP_DISABLE (0 << 24) +#define EXYNOS_WINCON1_VP_ENABLE (1 << 24) +#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23) +#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23) +#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23) + +/* WINSHMAP */ +#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) +#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x)) +#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x)) +#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x)) + +/* VIDOSDxA, VIDOSDxB */ +#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) +#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23) +#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22) + +/* VIDOSD0C, VIDOSDxD */ +#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) + +/* VIDOSDxC (1~4) */ +#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) +#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) +#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) +#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) +#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) +#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) +#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12) +#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0) + +/* Start Address */ +#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24) +#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) + +/* End Address */ +#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) + +/* Buffer Size */ +#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) +#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) +#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27) +#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26) + +/* WIN Color Map */ +#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff) + +/* VIDINTCON0 */ +#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) +#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) +#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) +#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) +#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) +#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) +#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15) +#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) +#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) +#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) +#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) +#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) +#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) +#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) +#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) +#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1) +#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1) +#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0) +#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0) +#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0) + +/* VIDINTCON1 */ +#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5) +#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2) +#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1) +#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0) + +/* WINMAP */ +#define EXYNOS_WINMAP_ENABLE (1 << 24) + +/* WxKEYCON0 (1~4) */ +#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26) +#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26) +#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25) +#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25) +#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24) +#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24) +#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) + +/* WxKEYCON1 (1~4) */ +#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) + +/* DUALRGB */ +#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0) +#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0) +#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0) +#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0) +#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2) +#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2) +#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4) +#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16) +#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16) +#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18) + +/* I80IFCONA0 and I80IFCONA1 */ +#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16) +#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12) +#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8) +#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4) +#define EXYNOS_RSPOL_LOW (0 << 2) +#define EXYNOS_RSPOL_HIGH (1 << 2) +#define EXYNOS_I80IFEN_DISABLE (0 << 0) +#define EXYNOS_I80IFEN_ENABLE (1 << 0) + +/* TRIGCON */ +#define EXYNOS_I80SOFT_TRIG_EN (1 << 0) +#define EXYNOS_I80START_TRIG (1 << 1) +#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) + +/* DP_MIE_CLKCON */ +#define EXYNOS_DP_MIE_DISABLE (0 << 0) +#define EXYNOS_DP_CLK_ENABLE (1 << 1) +#define EXYNOS_MIE_CLK_ENABLE (3 << 0) + +#endif /* _REGS_FB_H */ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h new file mode 100644 index 0000000..cfe1024 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -0,0 +1,334 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#ifndef __ASSEMBLY__ +struct s5p_gpio_bank { + unsigned int con; + unsigned int dat; + unsigned int pull; + unsigned int drv; + unsigned int pdn_con; + unsigned int pdn_pull; + unsigned char res1[8]; +}; + +struct exynos4_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank e2; + struct s5p_gpio_bank e3; + struct s5p_gpio_bank e4; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; +}; + +struct exynos4_gpio_part2 { + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res1[80]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + +struct exynos5_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank a2; + struct s5p_gpio_bank b0; + struct s5p_gpio_bank b1; + struct s5p_gpio_bank b2; + struct s5p_gpio_bank b3; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank c2; + struct s5p_gpio_bank c3; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res1[0x3]; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank res2[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos5_gpio_part2 { + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; +}; + +struct exynos5_gpio_part3 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + +struct exynos5_gpio_part4 { + struct s5p_gpio_bank z; +}; + +/* functions */ +void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); +void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); +void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); +unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); +void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); +void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 + +#define exynos4_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \ + EXYNOS4_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \ + EXYNOS4_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) + +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + +#define exynos5_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ + EXYNOS5_GPIO_PART1_BASE)->bank)) \ + - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \ + EXYNOS5_GPIO_PART2_BASE)->bank)) \ + - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) + +#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \ + EXYNOS5_GPIO_PART3_BASE)->bank)) \ + - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) + +static inline unsigned int s5p_gpio_base(int nr) +{ + if (cpu_is_exynos5()) { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return EXYNOS5_GPIO_PART1_BASE; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART2_BASE; + else + return EXYNOS5_GPIO_PART3_BASE; + + } else if (cpu_is_exynos4()) { + if (nr < EXYNOS4_GPIO_PART1_MAX) + return EXYNOS4_GPIO_PART1_BASE; + else + return EXYNOS4_GPIO_PART2_BASE; + } + + return 0; +} + +static inline unsigned int s5p_gpio_part_max(int nr) +{ + if (cpu_is_exynos5()) { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART1_MAX; + else + return EXYNOS5_GPIO_PART2_MAX; + + } else if (cpu_is_exynos4()) { + if (nr < EXYNOS4_GPIO_PART1_MAX) + return 0; + else + return EXYNOS4_GPIO_PART1_MAX; + } + + return 0; +} +#endif + +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x3 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_3X 0x1 +#define GPIO_DRV_2X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 +#endif diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h new file mode 100644 index 0000000..2326ca0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar <rcsekar@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __I2S_REGS_H__ +#define __I2S_REGS_H__ + +#define CON_TXFIFO_FULL (1 << 8) +#define CON_TXCH_PAUSE (1 << 4) +#define CON_ACTIVE (1 << 0) + +#define MOD_BLCP_SHIFT 24 +#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) +#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) +#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) +#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) + +#define MOD_BLC_16BIT (0 << 13) +#define MOD_BLC_8BIT (1 << 13) +#define MOD_BLC_24BIT (2 << 13) +#define MOD_BLC_MASK (3 << 13) + +#define MOD_SLAVE (1 << 11) +#define MOD_MASK (3 << 8) +#define MOD_LR_LLOW (0 << 7) +#define MOD_LR_RLOW (1 << 7) +#define MOD_SDF_IIS (0 << 5) +#define MOD_SDF_MSB (1 << 5) +#define MOD_SDF_LSB (2 << 5) +#define MOD_SDF_MASK (3 << 5) +#define MOD_RCLK_256FS (0 << 3) +#define MOD_RCLK_512FS (1 << 3) +#define MOD_RCLK_384FS (2 << 3) +#define MOD_RCLK_768FS (3 << 3) +#define MOD_RCLK_MASK (3 << 3) +#define MOD_BCLK_32FS (0 << 1) +#define MOD_BCLK_48FS (1 << 1) +#define MOD_BCLK_16FS (2 << 1) +#define MOD_BCLK_24FS (3 << 1) +#define MOD_BCLK_MASK (3 << 1) + +#define MOD_CDCLKCON (1 << 12) + +#define FIC_TXFLUSH (1 << 15) +#define FIC_RXFLUSH (1 << 7) + +#endif /* __I2S_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h new file mode 100644 index 0000000..c1c9a35 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DSIM_H +#define _DSIM_H + +#include <linux/list.h> +#include <linux/fb.h> + +#define PANEL_NAME_SIZE (32) + +enum mipi_dsim_interface_type { + DSIM_COMMAND, + DSIM_VIDEO +}; + +enum mipi_dsim_virtual_ch_no { + DSIM_VIRTUAL_CH_0, + DSIM_VIRTUAL_CH_1, + DSIM_VIRTUAL_CH_2, + DSIM_VIRTUAL_CH_3 +}; + +enum mipi_dsim_burst_mode_type { + DSIM_NON_BURST_SYNC_EVENT, + DSIM_BURST_SYNC_EVENT, + DSIM_NON_BURST_SYNC_PULSE, + DSIM_BURST, + DSIM_NON_VIDEO_MODE +}; + +enum mipi_dsim_no_of_data_lane { + DSIM_DATA_LANE_1, + DSIM_DATA_LANE_2, + DSIM_DATA_LANE_3, + DSIM_DATA_LANE_4 +}; + +enum mipi_dsim_byte_clk_src { + DSIM_PLL_OUT_DIV8, + DSIM_EXT_CLK_DIV8, + DSIM_EXT_CLK_BYPASS +}; + +enum mipi_dsim_pixel_format { + DSIM_CMD_3BPP, + DSIM_CMD_8BPP, + DSIM_CMD_12BPP, + DSIM_CMD_16BPP, + DSIM_VID_16BPP_565, + DSIM_VID_18BPP_666PACKED, + DSIM_18BPP_666LOOSELYPACKED, + DSIM_24BPP_888 +}; + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* + * struct mipi_dsim_config - interface for configuring mipi-dsi controller. + * + * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse. + * @eot_disable: enable or disable EoT packet in HS mode. + * @auto_vertical_cnt: specifies auto vertical count mode. + * in Video mode, the vertical line transition uses line counter + * configured by VSA, VBP, and Vertical resolution. + * If this bit is set to '1', the line counter does not use VSA and VBP + * registers.(in command mode, this variable is ignored) + * @hse: set horizontal sync event mode. + * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC + * start packet to MIPI DSI slave at MIPI DSI spec1.1r02. + * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area + * (in mommand mode, this variable is ignored) + * @hfp: specifies HFP disable mode. + * if this variable is set, DSI master ignores HFP area in VIDEO mode. + * (in command mode, this variable is ignored) + * @hbp: specifies HBP disable mode. + * if this variable is set, DSI master ignores HBP area in VIDEO mode. + * (in command mode, this variable is ignored) + * @hsa: specifies HSA disable mode. + * if this variable is set, DSI master ignores HSA area in VIDEO mode. + * (in command mode, this variable is ignored) + * @e_interface: specifies interface to be used.(CPU or RGB interface) + * @e_virtual_ch: specifies virtual channel number that main or + * sub diaplsy uses. + * @e_pixel_format: specifies pixel stream format for main or sub display. + * @e_burst_mode: selects Burst mode in Video mode. + * in Non-burst mode, RGB data area is filled with RGB data and NULL + * packets, according to input bandwidth of RGB interface. + * In Burst mode, RGB data area is filled with RGB data only. + * @e_no_data_lane: specifies data lane count to be used by Master. + * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8) + * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. + * @pll_stable_time: specifies the PLL Timer for stability of the ganerated + * clock(System clock cycle base) + * if the timer value goes to 0x00000000, the clock stable bit of status + * and interrupt register is set. + * @esc_clk: specifies escape clock frequency for getting the escape clock + * prescaler value. + * @stop_holding_cnt: specifies the interval value between transmitting + * read packet(or write "set_tear_on" command) and BTA request. + * after transmitting read packet or write "set_tear_on" command, + * BTA requests to D-PHY automatically. this counter value specifies + * the interval between them. + * @bta_timeout: specifies the timer for BTA. + * this register specifies time out from BTA request to change + * the direction with respect to Tx escape clock. + * @rx_timeout: specifies the timer for LP Rx mode timeout. + * this register specifies time out on how long RxValid deasserts, + * after RxLpdt asserts with respect to Tx escape clock. + * - RxValid specifies Rx data valid indicator. + * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode. + * - RxValid and RxLpdt specifies signal from D-PHY. + */ +struct mipi_dsim_config { + unsigned char auto_flush; + unsigned char eot_disable; + + unsigned char auto_vertical_cnt; + unsigned char hse; + unsigned char hfp; + unsigned char hbp; + unsigned char hsa; + + enum mipi_dsim_interface_type e_interface; + enum mipi_dsim_virtual_ch_no e_virtual_ch; + enum mipi_dsim_pixel_format e_pixel_format; + enum mipi_dsim_burst_mode_type e_burst_mode; + enum mipi_dsim_no_of_data_lane e_no_data_lane; + enum mipi_dsim_byte_clk_src e_byte_clk; + + /* + * =========================================== + * | P | M | S | MHz | + * ------------------------------------------- + * | 3 | 100 | 3 | 100 | + * | 3 | 100 | 2 | 200 | + * | 3 | 63 | 1 | 252 | + * | 4 | 100 | 1 | 300 | + * | 4 | 110 | 1 | 330 | + * | 12 | 350 | 1 | 350 | + * | 3 | 100 | 1 | 400 | + * | 4 | 150 | 1 | 450 | + * | 6 | 118 | 1 | 472 | + * | 3 | 120 | 1 | 480 | + * | 12 | 250 | 0 | 500 | + * | 4 | 100 | 0 | 600 | + * | 3 | 81 | 0 | 648 | + * | 3 | 88 | 0 | 704 | + * | 3 | 90 | 0 | 720 | + * | 3 | 100 | 0 | 800 | + * | 12 | 425 | 0 | 850 | + * | 4 | 150 | 0 | 900 | + * | 12 | 475 | 0 | 950 | + * | 6 | 250 | 0 | 1000 | + * ------------------------------------------- + */ + + /* + * pms could be calculated as the following. + * M * 24 / P * 2 ^ S = MHz + */ + unsigned char p; + unsigned short m; + unsigned char s; + + unsigned int pll_stable_time; + unsigned long esc_clk; + + unsigned short stop_holding_cnt; + unsigned char bta_timeout; + unsigned short rx_timeout; +}; + +/* + * struct mipi_dsim_device - global interface for mipi-dsi driver. + * + * @dsim_config: infomation for configuring mipi-dsi controller. + * @master_ops: callbacks to mipi-dsi operations. + * @dsim_lcd_dev: pointer to activated ddi device. + * (it would be registered by mipi-dsi driver.) + * @dsim_lcd_drv: pointer to activated_ddi driver. + * (it would be registered by mipi-dsi driver.) + * @state: specifies status of MIPI-DSI controller. + * the status could be RESET, INIT, STOP, HSCLKEN and ULPS. + * @data_lane: specifiec enabled data lane number. + * this variable would be set by driver according to e_no_data_lane + * automatically. + * @e_clk_src: select byte clock source. + * @pd: pointer to MIPI-DSI driver platform data. + */ +struct mipi_dsim_device { + struct mipi_dsim_config *dsim_config; + struct mipi_dsim_master_ops *master_ops; + struct mipi_dsim_lcd_device *dsim_lcd_dev; + struct mipi_dsim_lcd_driver *dsim_lcd_drv; + + unsigned int state; + unsigned int data_lane; + enum mipi_dsim_byte_clk_src e_clk_src; + + struct exynos_platform_mipi_dsim *pd; +}; + +/* + * struct exynos_platform_mipi_dsim - interface to platform data + * for mipi-dsi driver. + * + * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver. + * lcd panel driver searched would be actived. + * @dsim_config: pointer of structure for configuring mipi-dsi controller. + * @lcd_panel_info: pointer for lcd panel specific structure. + * this structure specifies width, height, timing and polarity and so on. + * @lcd_power: callback pointer for enabling or disabling lcd power. + * @mipi_power: callback pointer for enabling or disabling mipi power. + * @phy_enable: pointer to a callback controlling D-PHY enable/reset + */ +struct exynos_platform_mipi_dsim { + char lcd_panel_name[PANEL_NAME_SIZE]; + + struct mipi_dsim_config *dsim_config; + void *lcd_panel_info; + + int (*lcd_power)(void); + int (*mipi_power)(void); + void (*phy_enable)(unsigned int dev_index, unsigned int enable); +}; + +/* + * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations. + * + * @cmd_write: transfer command to lcd panel at LP mode. + * @cmd_read: read command from rx register. + * @get_dsim_frame_done: get the status that all screen data have been + * transferred to mipi-dsi. + * @clear_dsim_frame_done: clear frame done status. + * @get_fb_frame_done: get frame done status of display controller. + * @trigger: trigger display controller. + * - this one would be used only in case of CPU mode. + */ +struct mipi_dsim_master_ops { + int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1); + int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1); + int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim); + int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim); + + int (*get_fb_frame_done)(void); + void (*trigger)(struct fb_info *info); +}; + +/* + * device structure for mipi-dsi based lcd panel. + * + * @name: name of the device to use with this device, or an + * alias for that name. + * @id: id of device to be registered. + * @bus_id: bus id for identifing connected bus + * and this bus id should be same as id of mipi_dsim_device. + * @master: pointer to mipi-dsi master device object. + * @platform_data: lcd panel specific platform data. + */ +struct mipi_dsim_lcd_device { + char *name; + int id; + int bus_id; + int reverse_panel; + + struct mipi_dsim_device *master; + void *platform_data; +}; + +/* + * driver structure for mipi-dsi based lcd panel. + * + * this structure should be registered by lcd panel driver. + * mipi-dsi driver seeks lcd panel registered through name field + * and calls these callback functions in appropriate time. + * + * @name: name of the driver to use with this device, or an + * alias for that name. + * @id: id of driver to be registered. + * this id would be used for finding device object registered. + * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi + * dsi interface. + * @mipi_display_on: callback pointer for lcd panel display on. + */ +struct mipi_dsim_lcd_driver { + char *name; + int id; + + int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev); + void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev); +}; + +#ifdef CONFIG_EXYNOS_MIPI_DSIM +int exynos_mipi_dsi_init(void); +#else +static inline int exynos_mipi_dsi_init(void) +{ + return 0; +} +#endif + +/* + * register mipi_dsim_lcd_driver object defined by lcd panel driver + * to mipi-dsi driver. + */ +int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver + *lcd_drv); + +/* + * register mipi_dsim_lcd_device to mipi-dsi master. + */ +int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device + *lcd_dev); + +void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); + +/* panel driver init based on mipi dsi interface */ +void s6e8ax0_init(void); + +#endif /* _DSIM_H */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h new file mode 100644 index 0000000..afdfcf0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_MMC_H_ +#define __ASM_ARCH_MMC_H_ + +#define SDHCI_CONTROL2 0x80 +#define SDHCI_CONTROL3 0x84 +#define SDHCI_CONTROL4 0x8C + +#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) +#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) +#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) +#define SDHCI_CTRL2_SLCARDOUT (1 << 28) + +#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) +#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) +#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) + +#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) +#define SDHCI_CTRL2_LVLDAT_SHIFT (16) +#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) + +#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) +#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) +#define SDHCI_CTRL2_SDCDSEL (1 << 13) +#define SDHCI_CTRL2_SDSIGPC (1 << 12) +#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) + +#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) +#define SDHCI_CTRL2_DFCNT_SHIFT (9) + +#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) +#define SDHCI_CTRL2_RWAITMODE (1 << 7) +#define SDHCI_CTRL2_DISBUFRD (1 << 6) +#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) +#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) +#define SDHCI_CTRL2_PWRSYNC (1 << 3) +#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) +#define SDHCI_CTRL2_HWINITFIN (1 << 0) + +#define SDHCI_CTRL3_FCSEL3 (1 << 31) +#define SDHCI_CTRL3_FCSEL2 (1 << 23) +#define SDHCI_CTRL3_FCSEL1 (1 << 15) +#define SDHCI_CTRL3_FCSEL0 (1 << 7) + +#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) +#define SDHCI_CTRL4_DRIVE_SHIFT (16) + +int s5p_sdhci_init(u32 regbase, int index, int bus_width); + +static inline unsigned int s5p_mmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return s5p_sdhci_init(base, index, bus_width); +} +#endif diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h new file mode 100644 index 0000000..e5aed4b --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde <rajeshwari.s@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h new file mode 100644 index 0000000..014eebc --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan <a.kesavan@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h new file mode 100644 index 0000000..44ad8d3 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -0,0 +1,903 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Heungjun Kim <riverful.kim@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_POWER_H_ +#define __ASM_ARM_ARCH_POWER_H_ + +#ifndef __ASSEMBLY__ +struct exynos4_power { + unsigned int om_stat; + unsigned char res1[0x8]; + unsigned int rtc_clko_sel; + unsigned int gnss_rtc_out_ctrl; + unsigned char res2[0x1ec]; + unsigned int system_power_down_ctrl; + unsigned char res3[0x1]; + unsigned int system_power_down_option; + unsigned char res4[0x1f4]; + unsigned int swreset; + unsigned int rst_stat; + unsigned char res5[0x1f8]; + unsigned int wakeup_stat; + unsigned int eint_wakeup_mask; + unsigned int wakeup_mask; + unsigned char res6[0xf4]; + unsigned int hdmi_phy_control; + unsigned int usbdevice_phy_control; + unsigned int usbhost_phy_control; + unsigned int dac_phy_control; + unsigned int mipi_phy0_control; + unsigned int mipi_phy1_control; + unsigned int adc_phy_control; + unsigned int pcie_phy_control; + unsigned int sata_phy_control; + unsigned char res7[0xdc]; + unsigned int inform0; + unsigned int inform1; + unsigned int inform2; + unsigned int inform3; + unsigned int inform4; + unsigned int inform5; + unsigned int inform6; + unsigned int inform7; + unsigned char res8[0x1e0]; + unsigned int pmu_debug; + unsigned char res9[0x5fc]; + unsigned int arm_core0_sys_pwr_reg; + unsigned char res10[0xc]; + unsigned int arm_core1_sys_pwr_reg; + unsigned char res11[0x6c]; + unsigned int arm_common_sys_pwr_reg; + unsigned char res12[0x3c]; + unsigned int arm_cpu_l2_0_sys_pwr_reg; + unsigned int arm_cpu_l2_1_sys_pwr_reg; + unsigned char res13[0x38]; + unsigned int cmu_aclkstop_sys_pwr_reg; + unsigned int cmu_sclkstop_sys_pwr_reg; + unsigned char res14[0x4]; + unsigned int cmu_reset_sys_pwr_reg; + unsigned char res15[0x10]; + unsigned int apll_sysclk_sys_pwr_reg; + unsigned int mpll_sysclk_sys_pwr_reg; + unsigned int vpll_sysclk_sys_pwr_reg; + unsigned int epll_sysclk_sys_pwr_reg; + unsigned char res16[0x8]; + unsigned int cmu_clkstop_gps_alive_sys_pwr_reg; + unsigned int cmu_reset_gps_alive_sys_pwr_reg; + unsigned int cmu_clkstop_cam_sys_pwr_reg; + unsigned int cmu_clkstop_tv_sys_pwr_reg; + unsigned int cmu_clkstop_mfc_sys_pwr_reg; + unsigned int cmu_clkstop_g3d_sys_pwr_reg; + unsigned int cmu_clkstop_lcd0_sys_pwr_reg; + unsigned int cmu_clkstop_lcd1_sys_pwr_reg; + unsigned int cmu_clkstop_maudio_sys_pwr_reg; + unsigned int cmu_clkstop_gps_sys_pwr_reg; + unsigned int cmu_reset_cam_sys_pwr_reg; + unsigned int cmu_reset_tv_sys_pwr_reg; + unsigned int cmu_reset_mfc_sys_pwr_reg; + unsigned int cmu_reset_g3d_sys_pwr_reg; + unsigned int cmu_reset_lcd0_sys_pwr_reg; + unsigned int cmu_reset_lcd1_sys_pwr_reg; + unsigned int cmu_reset_maudio_sys_pwr_reg; + unsigned int cmu_reset_gps_sys_pwr_reg; + unsigned int top_bus_sys_pwr_reg; + unsigned int top_retention_sys_pwr_reg; + unsigned int top_pwr_sys_pwr_reg; + unsigned char res17[0x1c]; + unsigned int logic_reset_sys_pwr_reg; + unsigned char res18[0x14]; + unsigned int onenandxl_mem_sys_pwr_reg; + unsigned int modemif_mem_sys_pwr_reg; + unsigned char res19[0x4]; + unsigned int usbdevice_mem_sys_pwr_reg; + unsigned int sdmmc_mem_sys_pwr_reg; + unsigned int cssys_mem_sys_pwr_reg; + unsigned int secss_mem_sys_pwr_reg; + unsigned char res20[0x4]; + unsigned int pcie_mem_sys_pwr_reg; + unsigned int sata_mem_sys_pwr_reg; + unsigned char res21[0x18]; + unsigned int pad_retention_dram_sys_pwr_reg; + unsigned int pad_retention_maudio_sys_pwr_reg; + unsigned char res22[0x18]; + unsigned int pad_retention_gpio_sys_pwr_reg; + unsigned int pad_retention_uart_sys_pwr_reg; + unsigned int pad_retention_mmca_sys_pwr_reg; + unsigned int pad_retention_mmcb_sys_pwr_reg; + unsigned int pad_retention_ebia_sys_pwr_reg; + unsigned int pad_retention_ebib_sys_pwr_reg; + unsigned char res23[0x8]; + unsigned int pad_isolation_sys_pwr_reg; + unsigned char res24[0x1c]; + unsigned int pad_alv_sel_sys_pwr_reg; + unsigned char res25[0x1c]; + unsigned int xusbxti_sys_pwr_reg; + unsigned int xxti_sys_pwr_reg; + unsigned char res26[0x38]; + unsigned int ext_regulator_sys_pwr_reg; + unsigned char res27[0x3c]; + unsigned int gpio_mode_sys_pwr_reg; + unsigned char res28[0x3c]; + unsigned int gpio_mode_maudio_sys_pwr_reg; + unsigned char res29[0x3c]; + unsigned int cam_sys_pwr_reg; + unsigned int tv_sys_pwr_reg; + unsigned int mfc_sys_pwr_reg; + unsigned int g3d_sys_pwr_reg; + unsigned int lcd0_sys_pwr_reg; + unsigned int lcd1_sys_pwr_reg; + unsigned int maudio_sys_pwr_reg; + unsigned int gps_sys_pwr_reg; + unsigned int gps_alive_sys_pwr_reg; + unsigned char res30[0xc5c]; + unsigned int arm_core0_configuration; + unsigned int arm_core0_status; + unsigned int arm_core0_option; + unsigned char res31[0x74]; + unsigned int arm_core1_configuration; + unsigned int arm_core1_status; + unsigned int arm_core1_option; + unsigned char res32[0x37c]; + unsigned int arm_common_option; + unsigned char res33[0x1f4]; + unsigned int arm_cpu_l2_0_configuration; + unsigned int arm_cpu_l2_0_status; + unsigned char res34[0x18]; + unsigned int arm_cpu_l2_1_configuration; + unsigned int arm_cpu_l2_1_status; + unsigned char res35[0xa00]; + unsigned int pad_retention_maudio_option; + unsigned char res36[0xdc]; + unsigned int pad_retention_gpio_option; + unsigned char res37[0x1c]; + unsigned int pad_retention_uart_option; + unsigned char res38[0x1c]; + unsigned int pad_retention_mmca_option; + unsigned char res39[0x1c]; + unsigned int pad_retention_mmcb_option; + unsigned char res40[0x1c]; + unsigned int pad_retention_ebia_option; + unsigned char res41[0x1c]; + unsigned int pad_retention_ebib_option; + unsigned char res42[0x160]; + unsigned int ps_hold_control; + unsigned char res43[0xf0]; + unsigned int xusbxti_configuration; + unsigned int xusbxti_status; + unsigned char res44[0x14]; + unsigned int xusbxti_duration; + unsigned int xxti_configuration; + unsigned int xxti_status; + unsigned char res45[0x14]; + unsigned int xxti_duration; + unsigned char res46[0x1dc]; + unsigned int ext_regulator_duration; + unsigned char res47[0x5e0]; + unsigned int cam_configuration; + unsigned int cam_status; + unsigned int cam_option; + unsigned char res48[0x14]; + unsigned int tv_configuration; + unsigned int tv_status; + unsigned int tv_option; + unsigned char res49[0x14]; + unsigned int mfc_configuration; + unsigned int mfc_status; + unsigned int mfc_option; + unsigned char res50[0x14]; + unsigned int g3d_configuration; + unsigned int g3d_status; + unsigned int g3d_option; + unsigned char res51[0x14]; + unsigned int lcd0_configuration; + unsigned int lcd0_status; + unsigned int lcd0_option; + unsigned char res52[0x14]; + unsigned int lcd1_configuration; + unsigned int lcd1_status; + unsigned int lcd1_option; + unsigned char res53[0x34]; + unsigned int gps_configuration; + unsigned int gps_status; + unsigned int gps_option; + unsigned char res54[0x14]; + unsigned int gps_alive_configuration; + unsigned int gps_alive_status; + unsigned int gps_alive_option; +}; + +struct exynos5_power { + unsigned int om_stat; + unsigned char res1[0x18]; + unsigned int rtc_clko_sel; + unsigned int gnss_rtc_out_ctrl; + unsigned char res2[0x1dc]; + unsigned int central_seq_configuration; + unsigned int central_seq_status; + unsigned int central_seq_option; + unsigned char res3[0x14]; + unsigned int seq_transition0; + unsigned int seq_transition1; + unsigned int seq_transition2; + unsigned int seq_transition3; + unsigned int seq_transition4; + unsigned int seq_transition5; + unsigned int seq_transition6; + unsigned int seq_transition7; + unsigned int central_seq_dmc_configuration; + unsigned int central_seq_dmc_status; + unsigned int central_seq_dmc_option; + unsigned char res4[0x14]; + unsigned int seq_dmc_transition0; + unsigned int seq_dmc_transition1; + unsigned int seq_dmc_transition2; + unsigned int seq_dmc_transition3; + unsigned int seq_dmc_transition4; + unsigned int seq_dmc_transition5; + unsigned int seq_dmc_transition6; + unsigned int seq_dmc_transition7; + unsigned char res5[0x180]; + unsigned int swreset; + unsigned int rst_stat; + unsigned int automatic_wdt_reset_disable; + unsigned int mask_wdt_reset_request; + unsigned int mask_wreset_request; + unsigned char res6[0xec]; + unsigned int reset_sequencer_configuration; + unsigned int reset_sequencer_status; + unsigned int reset_sequencer_option; + unsigned char res7[0xf4]; + unsigned int wakeup_stat; + unsigned int eint_wakeup_mask; + unsigned int wakeup_mask; + unsigned int wakeup_interrupt; + unsigned char res8[0x10]; + unsigned int wakeup_stat_dmc; + unsigned int eint_wakeup_mask_dmc; + unsigned int wakeup_mask_dmc; + unsigned int wakeup_interrupt_dmc; + unsigned char res9[0xd0]; + unsigned int hdmi_phy_control; + unsigned int usbdrd_phy_control; + unsigned int usbhost_phy_control; + unsigned int efnand_phy_control; + unsigned int mipi_phy0_control; + unsigned int mipi_phy1_control; + unsigned int adc_phy_control; + unsigned int mtcadc_phy_control; + unsigned int dptx_phy_control; + unsigned int sata_phy_control; + unsigned char res10[0xd8]; + unsigned int inform0; + unsigned int inform1; + unsigned int inform2; + unsigned int inform3; + unsigned int sysip_dat0; + unsigned int sysip_dat1; + unsigned int sysip_dat2; + unsigned int sysip_dat3; + unsigned char res11[0xe0]; + unsigned int pmu_spare0; + unsigned int pmu_spare1; + unsigned int pmu_spare2; + unsigned int pmu_spare3; + unsigned char res12[0x70]; + unsigned int irom_data_reg0; + unsigned int irom_data_reg1; + unsigned int irom_data_reg2; + unsigned int irom_data_reg3; + unsigned char res13[0x70]; + unsigned int pmu_debug; + unsigned char res14[0x5fc]; + unsigned int arm_core0_sys_pwr_reg; + unsigned int dis_irq_arm_core0_local_sys_pwr_reg; + unsigned int dis_irq_arm_core0_central_sys_pwr_reg; + unsigned char res15[0x4]; + unsigned int arm_core1_sys_pwr_reg; + unsigned int dis_irq_arm_core1_local_sys_pwr_reg; + unsigned int dis_irq_arm_core1_central_sys_pwr_reg; + unsigned char res16[0x24]; + unsigned int fsys_arm_sys_pwr_reg; + unsigned int dis_irq_fsys_arm_local_sys_pwr_reg; + unsigned int dis_irq_fsys_arm_central_sys_pwr_reg; + unsigned char res17[0x4]; + unsigned int isp_arm_sys_pwr_reg; + unsigned int dis_irq_isp_arm_local_sys_pwr_reg; + unsigned int dis_irq_isp_arm_central_sys_pwr_reg; + unsigned char res18[0x24]; + unsigned int arm_common_sys_pwr_reg; + unsigned char res19[0x3c]; + unsigned int arm_l2_sys_pwr_reg; + unsigned char res20[0x3c]; + unsigned int cmu_aclkstop_sys_pwr_reg; + unsigned int cmu_sclkstop_sys_pwr_reg; + unsigned char res21[0x4]; + unsigned int cmu_reset_sys_pwr_reg; + unsigned char res22[0x10]; + unsigned int cmu_aclkstop_dmc_sys_pwr_reg; + unsigned int cmu_sclkstop_dmc_sys_pwr_reg; + unsigned char res23[0x4]; + unsigned int cmu_reset_dmc_sys_pwr_reg; + unsigned char res24[0x8]; + unsigned int ddrphy_dlllock_sys_pwr_reg; + unsigned char res25[0x4]; + unsigned int apll_sysclk_sys_pwr_reg; + unsigned int mpll_sysclk_sys_pwr_reg; + unsigned int vpll_sysclk_sys_pwr_reg; + unsigned int epll_sysclk_sys_pwr_reg; + unsigned int bpll_sysclk_sys_pwr_reg; + unsigned int cpll_sysclk_sys_pwr_reg; + unsigned int gpll_sysclk_sys_pwr_reg; + unsigned char res26[0x8]; + unsigned int mplluser_sysclk_sys_pwr_reg; + unsigned char res27[0x8]; + unsigned int bplluser_sysclk_sys_pwr_reg; + unsigned char res28[0xc]; + unsigned int top_bus_sys_pwr_reg; + unsigned int top_retention_sys_pwr_reg; + unsigned int top_pwr_sys_pwr_reg; + unsigned char res29[0x4]; + unsigned int top_bus_dmc_sys_pwr_reg; + unsigned int top_retention_dmc_sys_pwr_reg; + unsigned int top_pwr_dmc_sys_pwr_reg; + unsigned char res30[0x4]; + unsigned int logic_reset_sys_pwr_reg; + unsigned int oscclk_gate_sys_pwr_reg; + unsigned char res31[0x8]; + unsigned int logic_reset_dmc_sys_pwr_reg; + unsigned int oscclk_gate_dmc_sys_pwr_reg; + unsigned char res32[0x8]; + unsigned int usbotg_mem_sys_pwr_reg; + unsigned char res33[0x4]; + unsigned int g2d_mem_sys_pwr_reg; + unsigned int usbdrd_mem_sys_pwr_reg; + unsigned int efnand_mem_sys_pwr_reg; + unsigned int cssys_mem_sys_pwr_reg; + unsigned int secss_mem_sys_pwr_reg; + unsigned int rotator_mem_sys_pwr_reg; + unsigned int intram_mem_sys_pwr_reg; + unsigned int introm_mem_sys_pwr_reg; + unsigned int jpeg_mem_sys_pwr_reg; + unsigned int hsi_mem_sys_pwr_reg; + unsigned char res34[0x4]; + unsigned int mcuiop_mem_sys_pwr_reg; + unsigned char res35[0x4]; + unsigned int sata_mem_sys_pwr_reg; + unsigned int pad_retention_dram_sys_pwr_reg; + unsigned int pad_retention_mau_sys_pwr_reg; + unsigned int pad_retention_jtag_sys_pwr_reg; + unsigned char res36[0xc]; + unsigned int pad_retention_mmc2_sys_pwr_reg; + unsigned int pad_retention_mmc3_sys_pwr_reg; + unsigned int pad_retention_gpio_sys_pwr_reg; + unsigned int pad_retention_uart_sys_pwr_reg; + unsigned int pad_retention_mmc0_sys_pwr_reg; + unsigned int pad_retention_mmc1_sys_pwr_reg; + unsigned int pad_retention_ebia_sys_pwr_reg; + unsigned int pad_retention_ebib_sys_pwr_reg; + unsigned int pad_retention_spi_sys_pwr_reg; + unsigned int pad_retention_gpio_dmc_sys_pwr_reg; + unsigned int pad_isolation_sys_pwr_reg; + unsigned char res37[0xc]; + unsigned int pad_isolation_dmc_sys_pwr_reg; + unsigned char res38[0xc]; + unsigned int pad_alv_sel_sys_pwr_reg; + unsigned char res39[0x20]; + unsigned int xxti_sys_pwr_reg; + unsigned char res40[0x38]; + unsigned int ext_regulator_sys_pwr_reg; + unsigned char res41[0x3c]; + unsigned int gpio_mode_sys_pwr_reg; + unsigned char res42[0x1c]; + unsigned int gpio_mode_dmc_sys_pwr_reg; + unsigned char res43[0x1c]; + unsigned int gpio_mode_mau_sys_pwr_reg; + unsigned int top_asb_reset_sys_pwr_reg; + unsigned int top_asb_isolation_sys_pwr_reg; + unsigned char res44[0xb4]; + unsigned int gscl_sys_pwr_reg; + unsigned int isp_sys_pwr_reg; + unsigned int mfc_sys_pwr_reg; + unsigned int g3d_sys_pwr_reg; + unsigned char res45[0x4]; + unsigned int disp1_sys_pwr_reg; + unsigned int mau_sys_pwr_reg; + unsigned char res46[0x64]; + unsigned int cmu_clkstop_gscl_sys_pwr_reg; + unsigned int cmu_clkstop_isp_sys_pwr_reg; + unsigned int cmu_clkstop_mfc_sys_pwr_reg; + unsigned int cmu_clkstop_g3d_sys_pwr_reg; + unsigned char res47[0x4]; + unsigned int cmu_clkstop_disp1_sys_pwr_reg; + unsigned int cmu_clkstop_mau_sys_pwr_reg; + unsigned char res48[0x24]; + unsigned int cmu_sysclk_gscl_sys_pwr_reg; + unsigned int cmu_sysclk_isp_sys_pwr_reg; + unsigned int cmu_sysclk_mfc_sys_pwr_reg; + unsigned int cmu_sysclk_g3d_sys_pwr_reg; + unsigned char res49[0x4]; + unsigned int cmu_sysclk_disp1_sys_pwr_reg; + unsigned int cmu_sysclk_mau_sys_pwr_reg; + unsigned char res50[0xa4]; + unsigned int cmu_reset_gscl_sys_pwr_reg; + unsigned int cmu_reset_isp_sys_pwr_reg; + unsigned int cmu_reset_mfc_sys_pwr_reg; + unsigned int cmu_reset_g3d_sys_pwr_reg; + unsigned char res51[0x4]; + unsigned int cmu_reset_disp1_sys_pwr_reg; + unsigned int cmu_reset_mau_sys_pwr_reg; + unsigned char res52[0xa64]; + unsigned int arm_core0_configuration; + unsigned int arm_core0_status; + unsigned int arm_core0_option; + unsigned char res53[0x14]; + unsigned int dis_irq_arm_core0_local_configuration; + unsigned int dis_irq_arm_core0_local_status; + unsigned int dis_irq_arm_core0_local_option; + unsigned char res54[0x14]; + unsigned int dis_irq_arm_core0_central_configuration; + unsigned int dis_irq_arm_core0_central_status; + unsigned int dis_irq_arm_core0_central_option; + unsigned char res55[0x34]; + unsigned int arm_core1_configuration; + unsigned int arm_core1_status; + unsigned int arm_core1_option; + unsigned char res56[0x14]; + unsigned int dis_irq_arm_core1_local_configuration; + unsigned int dis_irq_arm_core1_local_status; + unsigned int dis_irq_arm_core1_local_option; + unsigned char res57[0x14]; + unsigned int dis_irq_arm_core1_central_configuration; + unsigned int dis_irq_arm_core1_central_status; + unsigned int dis_irq_arm_core1_central_option; + unsigned char res58[0x134]; + unsigned int fsys_arm_configuration; + unsigned int fsys_arm_status; + unsigned int fsys_arm_option; + unsigned char res59[0x14]; + unsigned int dis_irq_fsys_arm_local_configuration; + unsigned int dis_irq_fsys_arm_local_status; + unsigned int dis_irq_fsys_arm_local_option; + unsigned char res60[0x14]; + unsigned int dis_irq_fsys_arm_central_configuration; + unsigned int dis_irq_fsys_arm_central_status; + unsigned int dis_irq_fsys_arm_central_option; + unsigned char res61[0x34]; + unsigned int isp_arm_configuration; + unsigned int isp_arm_status; + unsigned int isp_arm_option; + unsigned char res62[0x14]; + unsigned int dis_irq_isp_arm_local_configuration; + unsigned int dis_irq_isp_arm_local_status; + unsigned int dis_irq_isp_arm_local_option; + unsigned char res63[0x14]; + unsigned int dis_irq_isp_arm_central_configuration; + unsigned int dis_irq_isp_arm_central_status; + unsigned int dis_irq_isp_arm_central_option; + unsigned char res64[0x134]; + unsigned int arm_common_configuration; + unsigned int arm_common_status; + unsigned int arm_common_option; + unsigned char res65[0x1f4]; + unsigned int arm_l2_configuration; + unsigned int arm_l2_status; + unsigned int arm_l2_option; + unsigned char res66[0x1f4]; + unsigned int cmu_aclkstop_configuration; + unsigned int cmu_aclkstop_status; + unsigned int cmu_aclkstop_option; + unsigned char res67[0x14]; + unsigned int cmu_sclkstop_configuration; + unsigned int cmu_sclkstop_status; + unsigned int cmu_sclkstop_option; + unsigned char res68[0x34]; + unsigned int cmu_reset_configuration; + unsigned int cmu_reset_status; + unsigned int cmu_reset_option; + unsigned char res69[0x94]; + unsigned int cmu_aclkstop_dmc_configuration; + unsigned int cmu_aclkstop_dmc_status; + unsigned int cmu_aclkstop_dmc_option; + unsigned char res70[0x14]; + unsigned int cmu_sclkstop_dmc_configuration; + unsigned int cmu_sclkstop_dmc_status; + unsigned int cmu_sclkstop_dmc_option; + unsigned char res71[0x34]; + unsigned int cmu_reset_dmc_configuration; + unsigned int cmu_reset_dmc_status; + unsigned int cmu_reset_dmc_option; + unsigned char res72[0x54]; + unsigned int ddrphy_dlllock_configuration; + unsigned int ddrphy_dlllock_status; + unsigned int ddrphy_dlllock_option; + unsigned char res73[0x34]; + unsigned int apll_sysclk_configuration; + unsigned int apll_sysclk_status; + unsigned int apll_sysclk_option; + unsigned char res74[0x18]; + unsigned int mpll_sysclk_status; + unsigned int mpll_sysclk_option; + unsigned char res75[0x14]; + unsigned int vpll_sysclk_configuration; + unsigned int vpll_sysclk_status; + unsigned int vpll_sysclk_option; + unsigned char res76[0x14]; + unsigned int epll_sysclk_configuration; + unsigned int epll_sysclk_status; + unsigned int epll_sysclk_option; + unsigned char res77[0x14]; + unsigned int bpll_sysclk_configuration; + unsigned int bpll_sysclk_status; + unsigned int bpll_sysclk_option; + unsigned char res78[0x14]; + unsigned int cpll_sysclk_configuration; + unsigned int cpll_sysclk_status; + unsigned int cpll_sysclk_option; + unsigned char res79[0x14]; + unsigned int gpll_sysclk_configuration; + unsigned int gpll_sysclk_status; + unsigned int gpll_sysclk_option; + unsigned char res80[0x54]; + unsigned int mplluser_sysclk_configuration; + unsigned int mplluser_sysclk_status; + unsigned int mplluser_sysclk_option; + unsigned char res81[0x54]; + unsigned int bplluser_sysclk_configuration; + unsigned int bplluser_sysclk_status; + unsigned int bplluser_sysclk_option; + unsigned char res82[0x74]; + unsigned int top_bus_configuration; + unsigned int top_bus_status; + unsigned int top_bus_option; + unsigned char res83[0x14]; + unsigned int top_retention_configuration; + unsigned int top_retention_status; + unsigned int top_retention_option; + unsigned char res84[0x14]; + unsigned int top_pwr_configuration; + unsigned int top_pwr_status; + unsigned int top_pwr_option; + unsigned char res85[0x34]; + unsigned int top_bus_dmc_configuration; + unsigned int top_bus_dmc_status; + unsigned int top_bus_dmc_option; + unsigned char res86[0x14]; + unsigned int top_retention_dmc_configuration; + unsigned int top_retention_dmc_status; + unsigned int top_retention_dmc_option; + unsigned char res87[0x14]; + unsigned int top_pwr_dmc_configuration; + unsigned int top_pwr_dmc_status; + unsigned int top_pwr_dmc_option; + unsigned char res88[0x34]; + unsigned int logic_reset_configuration; + unsigned int logic_reset_status; + unsigned int logic_reset_option; + unsigned char res89[0x14]; + unsigned int oscclk_gate_configuration; + unsigned int oscclk_gate_status; + unsigned int oscclk_gate_option; + unsigned char res90[0x54]; + unsigned int logic_reset_dmc_configuration; + unsigned int logic_reset_dmc_status; + unsigned int logic_reset_dmc_option; + unsigned char res91[0x14]; + unsigned int oscclk_gate_dmc_configuration; + unsigned int oscclk_gate_dmc_status; + unsigned int oscclk_gate_dmc_option; + unsigned char res92[0x54]; + unsigned int usbotg_mem_configuration; + unsigned int usbotg_mem_status; + unsigned int usbotg_mem_option; + unsigned char res93[0x34]; + unsigned int g2d_mem_configuration; + unsigned int g2d_mem_status; + unsigned int g2d_mem_option; + unsigned char res94[0x14]; + unsigned int usbdrd_mem_configuration; + unsigned int usbdrd_mem_status; + unsigned int usbdrd_mem_option; + unsigned char res95[0x14]; + unsigned int efnand_mem_configuration; + unsigned int efnand_mem_status; + unsigned int efnand_mem_option; + unsigned char res96[0x14]; + unsigned int cssys_mem_configuration; + unsigned int cssys_mem_status; + unsigned int cssys_mem_option; + unsigned char res97[0x14]; + unsigned int secss_mem_configuration; + unsigned int secss_mem_status; + unsigned int secss_mem_option; + unsigned char res98[0x14]; + unsigned int rotator_mem_configuration; + unsigned int rotator_mem_status; + unsigned int rotator_mem_option; + unsigned char res99[0x14]; + unsigned int intram_mem_configuration; + unsigned int intram_mem_status; + unsigned int intram_mem_option; + unsigned char res100[0x14]; + unsigned int introm_mem_configuration; + unsigned int introm_mem_status; + unsigned int introm_mem_option; + unsigned char res101[0x14]; + unsigned int jpeg_mem_configuration; + unsigned int jpeg_mem_status; + unsigned int jpeg_mem_option; + unsigned char res102[0x14]; + unsigned int hsi_mem_configuration; + unsigned int hsi_mem_status; + unsigned int hsi_mem_option; + unsigned char res103[0x34]; + unsigned int mcuiop_mem_configuration; + unsigned int mcuiop_mem_status; + unsigned int mcuiop_mem_option; + unsigned char res104[0x14]; + unsigned int sata_mem_configuration; + unsigned int sata_mem_status; + unsigned int sata_mem_option; + unsigned char res105[0x34]; + unsigned int pad_retention_dram_configuration; + unsigned int pad_retention_dram_status; + unsigned int pad_retention_dram_option; + unsigned char res106[0x14]; + unsigned int pad_retention_mau_configuration; + unsigned int pad_retention_mau_status; + unsigned int pad_retention_mau_option; + unsigned char res107[0x14]; + unsigned int pad_retention_jtag_configuration; + unsigned int pad_retention_jtag_status; + unsigned int pad_retention_jtag_option; + unsigned char res108[0x74]; + unsigned int pad_retention_mmc2_configuration; + unsigned int pad_retention_mmc2_status; + unsigned int pad_retention_mmc2_option; + unsigned char res109[0x14]; + unsigned int pad_retention_mmc3_configuration; + unsigned int pad_retention_mmc3_status; + unsigned int pad_retention_mmc3_option; + unsigned char res110[0x14]; + unsigned int pad_retention_gpio_configuration; + unsigned int pad_retention_gpio_status; + unsigned int pad_retention_gpio_option; + unsigned char res111[0x14]; + unsigned int pad_retention_uart_configuration; + unsigned int pad_retention_uart_status; + unsigned int pad_retention_uart_option; + unsigned char res112[0x14]; + unsigned int pad_retention_mmc0_configuration; + unsigned int pad_retention_mmc0_status; + unsigned int pad_retention_mmc0_option; + unsigned char res113[0x14]; + unsigned int pad_retention_mmc1_configuration; + unsigned int pad_retention_mmc1_status; + unsigned int pad_retention_mmc1_option; + unsigned char res114[0x14]; + unsigned int pad_retention_ebia_configuration; + unsigned int pad_retention_ebia_status; + unsigned int pad_retention_ebia_option; + unsigned char res115[0x14]; + unsigned int pad_retention_ebib_configuration; + unsigned int pad_retention_ebib_status; + unsigned int pad_retention_ebib_option; + unsigned char res116[0x14]; + unsigned int pad_retention_spi_configuration; + unsigned int pad_retention_spi_status; + unsigned int pad_retention_spi_option; + unsigned char res117[0x14]; + unsigned int pad_retention_gpio_dmc_configuration; + unsigned int pad_retention_gpio_dmc_status; + unsigned int pad_retention_gpio_dmc_option; + unsigned char res118[0x14]; + unsigned int pad_isolation_configuration; + unsigned int pad_isolation_status; + unsigned int pad_isolation_option; + unsigned char res119[0x74]; + unsigned int pad_isolation_dmc_configuration; + unsigned int pad_isolation_dmc_status; + unsigned int pad_isolation_dmc_option; + unsigned char res120[0x74]; + unsigned int pad_alv_sel_configuration; + unsigned int pad_alv_sel_status; + unsigned int pad_alv_sel_option0; + unsigned int ps_hold_control; + unsigned char res130[0x110]; + unsigned int xxti_configuration; + unsigned int xxti_status; + unsigned int xxti_option; + unsigned char res131[0x10]; + unsigned int xxti_duration3; + unsigned char res132[0x1c0]; + unsigned int ext_regulator_configuration; + unsigned int ext_regulator_status; + unsigned int ext_regulator_option; + unsigned char res133[0x10]; + unsigned int ext_regulator_duration3; + unsigned char res134[0x1e0]; + unsigned int gpio_mode_configuration; + unsigned int gpio_mode_status; + unsigned int gpio_mode_option; + unsigned char res135[0xf4]; + unsigned int gpio_mode_dmc_configuration; + unsigned int gpio_mode_dmc_status; + unsigned int gpio_mode_dmc_option; + unsigned char res136[0xd4]; + unsigned int gpio_mode_mau_configuration; + unsigned int gpio_mode_mau_status; + unsigned int gpio_mode_mau_option; + unsigned char res137[0x14]; + unsigned int top_asb_reset_configuration; + unsigned int top_asb_reset_status; + unsigned int top_asb_reset_option; + unsigned char res138[0x14]; + unsigned int top_asb_isolation_configuration; + unsigned int top_asb_isolation_status; + unsigned int top_asb_isolation_option; + unsigned char res139[0x5d4]; + unsigned int gscl_configuration; + unsigned int gscl_status; + unsigned int gscl_option; + unsigned char res140[0x14]; + unsigned int isp_configuration; + unsigned int isp_status; + unsigned int isp_option; + unsigned char res141[0x14]; + unsigned int mfc_configuration; + unsigned int mfc_status; + unsigned int mfc_option; + unsigned char res142[0x14]; + unsigned int g3d_configuration; + unsigned int g3d_status; + unsigned int g3d_option; + unsigned char res143[0x34]; + unsigned int disp1_configuration; + unsigned int disp1_status; + unsigned int disp1_option; + unsigned char res144[0x14]; + unsigned int mau_configuration; + unsigned int mau_status; + unsigned int mau_option; + unsigned char res145[0x334]; + unsigned int cmu_clkstop_gscl_configuration; + unsigned int cmu_clkstop_gscl_status; + unsigned int cmu_clkstop_gscl_option; + unsigned char res146[0x14]; + unsigned int cmu_clkstop_isp_configuration; + unsigned int cmu_clkstop_isp_status; + unsigned int cmu_clkstop_isp_option; + unsigned char res147[0x14]; + unsigned int cmu_clkstop_mfc_configuration; + unsigned int cmu_clkstop_mfc_status; + unsigned int cmu_clkstop_mfc_option; + unsigned char res148[0x14]; + unsigned int cmu_clkstop_g3d_configuration; + unsigned int cmu_clkstop_g3d_status; + unsigned int cmu_clkstop_g3d_option; + unsigned char res149[0x34]; + unsigned int cmu_clkstop_disp1_configuration; + unsigned int cmu_clkstop_disp1_status; + unsigned int cmu_clkstop_disp1_option; + unsigned char res150[0x14]; + unsigned int cmu_clkstop_mau_configuration; + unsigned int cmu_clkstop_mau_status; + unsigned int cmu_clkstop_mau_option; + unsigned char res151[0x134]; + unsigned int cmu_sysclk_gscl_configuration; + unsigned int cmu_sysclk_gscl_status; + unsigned int cmu_sysclk_gscl_option; + unsigned char res152[0x18]; + unsigned int cmu_sysclk_isp_status; + unsigned int cmu_sysclk_isp_option; + unsigned char res153[0x18]; + unsigned int cmu_sysclk_mfc_status; + unsigned int cmu_sysclk_mfc_option; + unsigned char res154[0x18]; + unsigned int cmu_sysclk_g3d_status; + unsigned int cmu_sysclk_g3d_option; + unsigned char res155[0x38]; + unsigned int cmu_sysclk_disp1_status; + unsigned int cmu_sysclk_disp1_option; + unsigned char res156[0x18]; + unsigned int cmu_sysclk_mau_status; + unsigned int cmu_sysclk_mau_option; + unsigned char res157[0x534]; + unsigned int cmu_reset_gscl_configuration; + unsigned int cmu_reset_gscl_status; + unsigned int cmu_reset_gscl_option; + unsigned char res158[0x14]; + unsigned int cmu_reset_isp_configuration; + unsigned int cmu_reset_isp_status; + unsigned int cmu_reset_isp_option; + unsigned char res159[0x14]; + unsigned int cmu_reset_mfc_configuration; + unsigned int cmu_reset_mfc_status; + unsigned int cmu_reset_mfc_option; + unsigned char res160[0x14]; + unsigned int cmu_reset_g3d_configuration; + unsigned int cmu_reset_g3d_status; + unsigned int cmu_reset_g3d_option; + unsigned char res161[0x34]; + unsigned int cmu_reset_disp1_configuration; + unsigned int cmu_reset_disp1_status; + unsigned int cmu_reset_disp1_option; + unsigned char res162[0x14]; + unsigned int cmu_reset_mau_configuration; + unsigned int cmu_reset_mau_status; + unsigned int cmu_reset_mau_option; + unsigned char res163[0x24]; +}; +#endif /* __ASSEMBLY__ */ + +void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); + +#define EXYNOS_MIPI_PHY_ENABLE (1 << 0) +#define EXYNOS_MIPI_PHY_SRESETN (1 << 1) +#define EXYNOS_MIPI_PHY_MRESETN (1 << 2) + +void set_usbhost_phy_ctrl(unsigned int enable); + +/* Enables hardware tripping to power off the system when TMU fails */ +void set_hw_thermal_trip(void); + +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) + +void set_dp_phy_ctrl(unsigned int enable); + +#define EXYNOS_DP_PHY_ENABLE (1 << 0) + +#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) +#define POWER_ENABLE_HW_TRIP (1UL << 31) + +/* + * Set ps_hold data driving value high + * This enables the machine to stay powered on + * after the initial power-on condition goes away + * (e.g. power button). + */ +void set_ps_hold_ctrl(void); + +/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ +#define PMU_DEBUG_XXTI 0x1000 +/* Mask bit[12:8] for xxti clock selection */ +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 + +/* + * Pmu debug is used for xclkout, enable xclkout with + * source as XXTI + */ +void set_xclkout(void); + +/* + * Read inform1 to get the reset status. + * @return: the value can be either S5P_CHECK_SLEEP or + * S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1 + * if none of these then its normal booting. + */ +uint32_t get_reset_status(void); + + +/* Read the resume function and call it */ +void power_exit_wakeup(void); +#endif diff --git a/arch/arm/include/asm/arch-exynos/pwm.h b/arch/arm/include/asm/arch-exynos/pwm.h new file mode 100644 index 0000000..3e95160 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pwm.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) (x * 4) + +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) +#define TCON4_AUTO_RELOAD (1 << 22) + +#ifndef __ASSEMBLY__ +struct s5p_timer { + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int tcmpb2; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int tcmpb3; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tintcstat; +}; +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-exynos/pwm_backlight.h b/arch/arm/include/asm/arch-exynos/pwm_backlight.h new file mode 100644 index 0000000..368ffc5 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pwm_backlight.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PWM_BACKLIGHT_H_ +#define _PWM_BACKLIGHT_H_ + +struct pwm_backlight_data { + int pwm_id; + int period; + int max_brightness; + int brightness; +}; + +extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); + +#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/arch/arm/include/asm/arch-exynos/sound.h b/arch/arm/include/asm/arch-exynos/sound.h new file mode 100644 index 0000000..d1bd2f6 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/sound.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde <rajeshwari.s@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __SOUND_ARCH_H__ +#define __SOUND_ARCH_H__ + +/* I2S values */ +#define I2S_PLL_CLK 192000000 +#define I2S_SAMPLING_RATE 48000 +#define I2S_BITS_PER_SAMPLE 16 +#define I2S_CHANNELS 2 +#define I2S_RFS 256 +#define I2S_BFS 32 + +/* I2C values */ +#define AUDIO_I2C_BUS 1 +#define AUDIO_I2C_REG 0x1a + +/* Audio Codec */ +#define AUDIO_CODEC "wm8994" + +#define AUDIO_COMPAT 1 +#endif diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h new file mode 100644 index 0000000..7cab1e9 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Padmavathi Venna <padma.v@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ +#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ + +#ifndef __ASSEMBLY__ + +/* SPI peripheral register map; padded to 64KB */ +struct exynos_spi { + unsigned int ch_cfg; /* 0x00 */ + unsigned char reserved0[4]; + unsigned int mode_cfg; /* 0x08 */ + unsigned int cs_reg; /* 0x0c */ + unsigned char reserved1[4]; + unsigned int spi_sts; /* 0x14 */ + unsigned int tx_data; /* 0x18 */ + unsigned int rx_data; /* 0x1c */ + unsigned int pkt_cnt; /* 0x20 */ + unsigned char reserved2[4]; + unsigned char reserved3[4]; + unsigned int fb_clk; /* 0x2c */ + unsigned char padding[0xffd0]; +}; + +#define EXYNOS_SPI_MAX_FREQ 50000000 + +#define SPI_TIMEOUT_MS 10 + +/* SPI_CHCFG */ +#define SPI_CH_HS_EN (1 << 6) +#define SPI_CH_RST (1 << 5) +#define SPI_SLAVE_MODE (1 << 4) +#define SPI_CH_CPOL_L (1 << 3) +#define SPI_CH_CPHA_B (1 << 2) +#define SPI_RX_CH_ON (1 << 1) +#define SPI_TX_CH_ON (1 << 0) + +/* SPI_MODECFG */ +#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) +#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) + +/* SPI_CSREG */ +#define SPI_SLAVE_SIG_INACT (1 << 0) + +/* SPI_STS */ +#define SPI_ST_TX_DONE (1 << 25) +#define SPI_FIFO_LVL_MASK 0x1ff +#define SPI_TX_LVL_OFFSET 6 +#define SPI_RX_LVL_OFFSET 15 + +/* Feedback Delay */ +#define SPI_CLK_BYPASS (0 << 0) +#define SPI_FB_DELAY_90 (1 << 0) +#define SPI_FB_DELAY_180 (2 << 0) +#define SPI_FB_DELAY_270 (3 << 0) + +/* Packet Count */ +#define SPI_PACKET_CNT_EN (1 << 16) + +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h new file mode 100644 index 0000000..59bb7e0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/spl.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_EXYNOS_SPL_H__ +#define __ASM_ARCH_EXYNOS_SPL_H__ + +#include <asm/arch-exynos/dmc.h> + +enum boot_mode { + /* + * Assign the OM pin values for respective boot modes. + * Exynos4 does not support spi boot and the mmc boot OM + * pin values are the same across Exynos4 and Exynos5. + */ + BOOT_MODE_MMC = 4, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ + BOOT_MODE_SERIAL = 20, + /* Boot based on Operating Mode pin settings */ + BOOT_MODE_OM = 32, + BOOT_MODE_USB, /* Boot using USB download */ +}; + +#ifndef __ASSEMBLY__ +/* Parameters of early board initialization in SPL */ +struct spl_machine_param { + /* Add fields as and when required */ + u32 signature; + u32 version; /* Version number */ + u32 size; /* Size of block */ + /** + * Parameters we expect, in order, terminated with \0. Each parameter + * is a single character representing one 32-bit word in this + * structure. + * + * Valid characters in this string are: + * + * Code Name + * v mem_iv_size + * m mem_type + * u uboot_size + * b boot_source + * f frequency_mhz (memory frequency in MHz) + * a ARM clock frequency in MHz + * s serial base address + * i i2c base address for early access (meant for PMIC) + * r board rev GPIO numbers used to read board revision + * (lower halfword=bit 0, upper=bit 1) + * M Memory Manufacturer name + * \0 termination + */ + char params[12]; /* Length must be word-aligned */ + u32 mem_iv_size; /* Memory channel interleaving size */ + enum ddr_mode mem_type; /* Type of on-board memory */ + /* + * U-boot size - The iROM mmc copy function used by the SPL takes a + * block count paramter to describe the u-boot size unlike the spi + * boot copy function which just uses the u-boot size directly. Align + * the u-boot size to block size (512 bytes) when populating the SPL + * table only for mmc boot. + */ + u32 uboot_size; + enum boot_mode boot_source; /* Boot device */ + unsigned frequency_mhz; /* Frequency of memory in MHz */ + unsigned arm_freq_mhz; /* ARM Frequency in MHz */ + u32 serial_base; /* Serial base address */ + u32 i2c_base; /* i2c base address */ + u32 board_rev_gpios; /* Board revision GPIOs */ + enum mem_manuf mem_manuf; /* Memory Manufacturer */ +} __attribute__((__packed__)); +#endif + +/** + * Validate signature and return a pointer to the parameter table. If the + * signature is invalid, call panic() and never return. + * + * @return pointer to the parameter table if signature matched or never return. + */ +struct spl_machine_param *spl_get_machine_params(void); + +#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/sromc.h b/arch/arm/include/asm/arch-exynos/sromc.h new file mode 100644 index 0000000..dc6aae2 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/sromc.h @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for SROMC + * + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[4]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +enum { + FDT_SROM_PMC, + FDT_SROM_TACP, + FDT_SROM_TAH, + FDT_SROM_TCOH, + FDT_SROM_TACC, + FDT_SROM_TCOS, + FDT_SROM_TACS, + + FDT_SROM_TIMING_COUNT, +}; + +struct fdt_sromc { + u8 bank; /* srom bank number */ + u8 width; /* bus width in bytes */ + unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ +}; + +#endif /* __ASM_ARCH_SROMC_H_ */ diff --git a/arch/arm/include/asm/arch-exynos/sys_proto.h b/arch/arm/include/asm/arch-exynos/sys_proto.h new file mode 100644 index 0000000..11f1636 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/sys_proto.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2010 Samsung Electrnoics + * Minkyu Kang <mk7.kang@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_device_type(void); +void invalidate_dcache(u32); +void l2_cache_disable(void); +void l2_cache_enable(void); + +#endif diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h new file mode 100644 index 0000000..42e1d21 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_SYSTEM_H_ +#define __ASM_ARM_ARCH_SYSTEM_H_ + +#ifndef __ASSEMBLY__ +struct exynos4_sysreg { + unsigned char res1[0x210]; + unsigned int display_ctrl; + unsigned int display_ctrl2; + unsigned int camera_control; + unsigned int audio_endian; + unsigned int jtag_con; +}; + +struct exynos5_sysreg { + unsigned char res1[0x214]; + unsigned int disp1blk_cfg; + unsigned int disp2blk_cfg; + unsigned int hdcp_e_fuse; + unsigned int gsclblk_cfg0; + unsigned int gsclblk_cfg1; + unsigned int reserved; + unsigned int ispblk_cfg; + unsigned int usb20phy_cfg; + unsigned char res2[0x29c]; + unsigned int mipi_dphy; + unsigned int dptx_dphy; + unsigned int phyclk_sel; +}; +#endif + +#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) + +void set_usbhost_mode(unsigned int mode); +void set_system_display_ctrl(void); + +#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h new file mode 100644 index 0000000..cad3569 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/tmu.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Akshay Saraswat <akshay.s@samsung.com> + * + * EXYNOS - Thermal Management Unit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TMU_H +#define __ASM_ARCH_TMU_H + +struct exynos5_tmu_reg { + u32 triminfo; + u32 rsvd1[4]; + u32 triminfo_control; + u32 rsvd5[2]; + u32 tmu_control; + u32 rsvd7; + u32 tmu_status; + u32 sampling_internal; + u32 counter_value0; + u32 counter_value1; + u32 rsvd8[2]; + u32 current_temp; + u32 rsvd10[3]; + u32 threshold_temp_rise; + u32 threshold_temp_fall; + u32 rsvd13[2]; + u32 past_temp3_0; + u32 past_temp7_4; + u32 past_temp11_8; + u32 past_temp15_12; + u32 inten; + u32 intstat; + u32 intclear; + u32 rsvd15; + u32 emul_con; +}; +#endif /* __ASM_ARCH_TMU_H */ diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h new file mode 100644 index 0000000..4d9c3a3 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/tzpc.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __TZPC_H_ +#define __TZPC_H_ + +#ifndef __ASSEMBLY__ +struct exynos_tzpc { + unsigned int r0size; + char res1[0x7FC]; + unsigned int decprot0stat; + unsigned int decprot0set; + unsigned int decprot0clr; + unsigned int decprot1stat; + unsigned int decprot1set; + unsigned int decprot1clr; + unsigned int decprot2stat; + unsigned int decprot2set; + unsigned int decprot2clr; + unsigned int decprot3stat; + unsigned int decprot3set; + unsigned int decprot3clr; + char res2[0x7B0]; + unsigned int periphid0; + unsigned int periphid1; + unsigned int periphid2; + unsigned int periphid3; + unsigned int pcellid0; + unsigned int pcellid1; + unsigned int pcellid2; + unsigned int pcellid3; +}; + +#define EXYNOS4_NR_TZPC_BANKS 6 +#define EXYNOS5_NR_TZPC_BANKS 10 + +/* TZPC : Register Offsets */ +#define TZPC_BASE_OFFSET 0x10000 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF +void tzpc_init(void); + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-exynos/uart.h b/arch/arm/include/asm/arch-exynos/uart.h new file mode 100644 index 0000000..6cc68df --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/uart.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * Heungjun Kim <riverful.kim@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned char utxh; + unsigned char res1[3]; + unsigned char urxh; + unsigned char res2[3]; + unsigned int ubrdiv; + union br_rest rest; + unsigned char res3[0xffd0]; +}; + +static inline int s5p_uart_divslot(void) +{ + return 0; +} + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-exynos/watchdog.h b/arch/arm/include/asm/arch-exynos/watchdog.h new file mode 100644 index 0000000..ee0c9c9 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/watchdog.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Heungjun Kim <riverful.kim@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_WATCHDOG_H_ +#define __ASM_ARM_ARCH_WATCHDOG_H_ + +#define WTCON_RESET_OFFSET 0 +#define WTCON_INTEN_OFFSET 2 +#define WTCON_CLKSEL_OFFSET 3 +#define WTCON_EN_OFFSET 5 +#define WTCON_PRE_OFFSET 8 + +#define WTCON_CLK_16 0x0 +#define WTCON_CLK_32 0x1 +#define WTCON_CLK_64 0x2 +#define WTCON_CLK_128 0x3 + +#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) +#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) +#define WTCON_EN (0x1 << WTCON_EN_OFFSET) +#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) +#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) + +#ifndef __ASSEMBLY__ +struct s5p_watchdog { + unsigned int wtcon; + unsigned int wtdat; + unsigned int wtcnt; + unsigned int wtclrint; +}; + +/* functions */ +void wdt_stop(void); +void wdt_start(unsigned int timeout); +#endif /* __ASSEMBLY__ */ + +#endif |
