diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs/aspeed')
29 files changed, 9652 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H new file mode 100644 index 0000000..44b7540 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/COMMINF.H @@ -0,0 +1,641 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef COMMINF_H +#define COMMINF_H + +#include "SWFUNC.H" + +#if defined(LinuxAP) +#endif +#ifdef SLT_UBOOT +#endif +#ifdef SLT_DOS + #include <stdio.h> + #include <time.h> + #include <dos.h> // For delay() +#endif + +#include "TYPEDEF.H" +#include "LIB.H" + +//--------------------------------------------------------- +// Print Message +//--------------------------------------------------------- +// for function +#define FP_LOG 0 +#define FP_IO 1 +#define STD_OUT 2 + +#ifdef SLT_UBOOT + #define PRINT printf + #define OUT_OBJ + #define FILE_VAR + + #define GET_OBJ( i ) \ + do { \ + if ( i != STD_OUT ) \ + return; \ + } while ( 0 ); + +#else + #define PRINT fprintf + #define OUT_OBJ fp, + #define FILE_VAR FILE *fp; + + #define GET_OBJ( i ) \ + switch( i ) { \ + case FP_LOG: \ + fp = fp_log; \ + break; \ + case FP_IO: \ + fp = fp_io; \ + break; \ + case STD_OUT: \ + fp = stdout; \ + break; \ + default : break; \ + } +#endif + +//--------------------------------------------------------- +// Function +//--------------------------------------------------------- +#ifdef SLT_UBOOT + #define DELAY( x ) udelay( x * 1000 ) // For Uboot, the unit of udelay() is us. + #define GET_CAHR getc +#endif +#ifdef SLT_DOS + #define DELAY( x ) delay( x ) // For DOS, the unit of delay() is ms. + #define GET_CAHR getchar +#endif + +//--------------------------------------------------------- +// Default argument +//--------------------------------------------------------- +#define DEF_USER_DEF_PACKET_VAL 0x66666666 //0xff00ff00, 0xf0f0f0f0, 0xcccccccc, 0x55aa55aa, 0x5a5a5a5a, 0x66666666 +#define DEF_IOTIMINGBUND 5 //0/1/3/5/7 +#define DEF_PHY_ADR 0 +#define DEF_TESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: 0x55, 3: random, 4: ARP, 5: ARP, 6: IO timing, 7: IO timing+IO Strength +#define DEF_LOOP_MAX 1 +#define DEF_MAC_LOOP_BACK 0 //GCtrl bit6 +#define DEF_SKIP_CHECK_PHY 0 //GCtrl bit4 +#define DEF_INIT_PHY 1 //GCtrl bit3 + +#define SET_1GBPS 0 // 1G bps +#define SET_100MBPS 1 // 100M bps +#define SET_10MBPS 2 // 10M bps +#define SET_1G_100M_10MBPS 3 // 1G and 100M and 10M bps +#define DEF_SPEED SET_1G_100M_10MBPS +#define DEF_ARPNUMCNT 0 + +//--------------------------------------------------------- +// MAC information +//--------------------------------------------------------- +#if ( AST1010_IOMAP == 1 ) + // AST1010 only has a MAC + #define MAC_BASE1 AST_MAC1_BASE + #define MAC_BASE2 AST_MAC1_BASE + #define MAC_BASE3 AST_MAC1_BASE + #define MAC_BASE4 AST_MAC1_BASE +#endif + +#if ( AST1010_IOMAP == 2 ) + // AST1010 only has a MAC + #define MAC_BASE1 0x0830000 + #define MAC_BASE2 0x0830000 + #define MAC_BASE3 0x0830000 + #define MAC_BASE4 0x0830000 +#endif + +#ifndef AST1010_IOMAP + #define MAC_BASE1 0x1e660000 + #define MAC_BASE2 0x1e680000 + #define MAC_BASE3 0x1e670000 + #define MAC_BASE4 0x1e690000 +#endif + +#define MDC_Thres 0x3f +#define MAC_PHYWr 0x08000000 +#define MAC_PHYRd 0x04000000 + +#define MAC_PHYWr_New 0x00009400 +#define MAC_PHYRd_New 0x00009800 +#define MAC_PHYBusy_New 0x00008000 + +//#define MAC_30h 0x00001010 +//#define MAC_34h 0x00000000 +//#define MAC_38h 0x00d22f00 //default 0x22f00 +//#define MAC_38h 0x00022f00 //default 0x22f00 + +#define MAC_40h 0x40000000 + +#ifdef Enable_BufMerge + #define MAC_48h 0x007702F1 //default 0xf1 +#else + #ifdef AST1010_IOMAP + #define MAC_48h 0x000002F1 //default 0xf1 + #else + #define MAC_48h 0x000001F1 //default 0xf1 + #endif +#endif + +//--------------------------------------------------------- +// Data information +//--------------------------------------------------------- +#ifdef SelectSimpleBoundary + #define ZeroCopy_OFFSET 0 +#else + #define ZeroCopy_OFFSET ( (BurstEnable) ? 0 : 2 ) +#endif + +// --------------------------------- DRAM_MapAdr = TDES_BASE1 +// | TX descriptor ring #1 | +// ------------------------- DRAM_MapAdr + 0x040000 = RDES_BASE1 +// | RX descriptor ring #1 | +// ------------------------- DRAM_MapAdr + 0x080000 = TDES_BASE2 +// | TX descriptor ring #2 | +// ------------------------- DRAM_MapAdr + 0x0C0000 = RDES_BASE2 +// | RX descriptor ring #2 | +// --------------------------------- DRAM_MapAdr + 0x100000 = DMA_BASE ------------------------- +// | #1 | \ | #1 Tx | +// DMA buffer | | DMA_BufSize | LOOP = 0 | +// ( Tx/Rx ) ------------------------- / -------------------------------------------------- +// | #2 | | #2 Rx | #2 Tx | +// | | | LOOP = 0 | LOOP = 1 | +// ------------------------- -------------------------------------------------- +// | #3 | | #3 Rx | +// | | | LOOP = 1 | +// ------------------------- ------------------------- +// | #4 | .......... +// | | +// ------------------------- +// | #5 | +// | | +// ------------------------- +// | #6 | +// | | +// ------------------------- +// . +// . +// ------------------------- +// | #n, n = DMA_BufNum | +// | | +// --------------------------------- + +#if ( AST1010_IOMAP == 1 ) + #define DRAM_MapAdr ( CONFIG_DRAM_SWAP_BASE + 0x00200000 ) // We use 0xA00000 to 0xEFFFFF + #define CPU_BUS_ADDR_SDRAM_OFFSET 0x01000000 // In ReMapping function, MAC engine need Bus address + // But Coldfire need CPU address, so need to do offset +#endif + +#if ( AST1010_IOMAP == 2 ) + #define DRAM_MapAdr 0x0A00000 // We use 0xA00000 to 0xEFFFFF + #define CPU_BUS_ADDR_SDRAM_OFFSET 0 +#endif + +#ifndef AST1010_IOMAP + #ifdef AST3200_IOMAP + #define DRAM_MapAdr 0x80000000 + #else + #define DRAM_MapAdr 0x44000000 + #endif + + #define CPU_BUS_ADDR_SDRAM_OFFSET 0 +#endif + + #define TDES_BASE1 ( 0x00000000 + DRAM_MapAdr ) + #define RDES_BASE1 ( 0x00040000 + DRAM_MapAdr ) + #define TDES_BASE2 ( 0x00080000 + DRAM_MapAdr ) + #define RDES_BASE2 ( 0x000C0000 + DRAM_MapAdr ) + + #define TDES_IniVal ( 0xb0000000 + FRAME_LEN_Cur ) + #define RDES_IniVal ( 0x00000fff ) + #define EOR_IniVal ( 0x40008000 ) + #define HWOwnTx(dat) ( (dat) & 0x80000000 ) + #define HWOwnRx(dat) ( !((dat) & 0x80000000) ) + #define HWEOR(dat) ( dat & 0x40000000 ) + +//--------------------------------------------------------- +// Error Flag Bits +//--------------------------------------------------------- +#define Err_MACMode ( 1 << 0 ) // MAC interface mode mismatch +#define Err_PHY_Type ( 1 << 1 ) // Unidentifiable PHY +#define Err_MALLOC_FrmSize ( 1 << 2 ) // Malloc fail at frame size buffer +#define Err_MALLOC_LastWP ( 1 << 3 ) // Malloc fail at last WP buffer +#define Err_Check_Buf_Data ( 1 << 4 ) // Received data mismatch +#define Err_Check_Des ( 1 << 5 ) // Descriptor error +#define Err_NCSI_LinkFail ( 1 << 6 ) // NCSI packet retry number over flows +#define Err_NCSI_Check_TxOwnTimeOut ( 1 << 7 ) // Time out of checking Tx owner bit in NCSI packet +#define Err_NCSI_Check_RxOwnTimeOut ( 1 << 8 ) // Time out of checking Rx owner bit in NCSI packet +#define Err_NCSI_Check_ARPOwnTimeOut ( 1 << 9 ) // Time out of checking ARP owner bit in NCSI packet +#define Err_NCSI_No_PHY ( 1 << 10 ) // Can not find NCSI PHY +#define Err_NCSI_Channel_Num ( 1 << 11 ) // NCSI Channel Number Mismatch +#define Err_NCSI_Package_Num ( 1 << 12 ) // NCSI Package Number Mismatch +#define Err_PHY_TimeOut ( 1 << 13 ) // Time out of read/write/reset PHY register +#define Err_RXBUF_UNAVA ( 1 << 14 ) // MAC00h[2]:Receiving buffer unavailable +#define Err_RPKT_LOST ( 1 << 15 ) // MAC00h[3]:Received packet lost due to RX FIFO full +#define Err_NPTXBUF_UNAVA ( 1 << 16 ) // MAC00h[6]:Normal priority transmit buffer unavailable +#define Err_TPKT_LOST ( 1 << 17 ) // MAC00h[7]:Packets transmitted to Ethernet lost +#define Err_DMABufNum ( 1 << 18 ) // DMA Buffer is not enough +#define Err_IOMargin ( 1 << 19 ) // IO timing margin is not enough +#define Err_IOMarginOUF ( 1 << 20 ) // IO timing testing out of boundary +#define Err_MHCLK_Ratio ( 1 << 21 ) // Error setting of MAC AHB bus clock (SCU08[18:16]) + +#define Check_Des_TxOwnTimeOut ( 1 << 0 ) // Time out of checking Tx owner bit +#define Check_Des_RxOwnTimeOut ( 1 << 1 ) // Time out of checking Rx owner bit +#define Check_Des_RxErr ( 1 << 2 ) // Input signal RxErr +#define Check_Des_OddNibble ( 1 << 3 ) // Nibble bit happen +#define Check_Des_CRC ( 1 << 4 ) // CRC error of frame +#define Check_Des_RxFIFOFull ( 1 << 5 ) // Rx FIFO full +#define Check_Des_FrameLen ( 1 << 6 ) // Frame length mismatch + +#define NCSI_LinkFail_Get_Version_ID ( 1 << 0 ) // Time out when Get Version ID +#define NCSI_LinkFail_Get_Capabilities ( 1 << 1 ) // Time out when Get Capabilities +#define NCSI_LinkFail_Select_Active_Package ( 1 << 2 ) // Time out when Select Active Package +#define NCSI_LinkFail_Enable_Set_MAC_Address ( 1 << 3 ) // Time out when Enable Set MAC Address +#define NCSI_LinkFail_Enable_Broadcast_Filter ( 1 << 4 ) // Time out when Enable Broadcast Filter +#define NCSI_LinkFail_Enable_Network_TX ( 1 << 5 ) // Time out when Enable Network TX +#define NCSI_LinkFail_Enable_Channel ( 1 << 6 ) // Time out when Enable Channel +#define NCSI_LinkFail_Disable_Network_TX ( 1 << 7 ) // Time out when Disable Network TX +#define NCSI_LinkFail_Disable_Channel ( 1 << 8 ) // Time out when Disable Channel + +//--------------------------------------------------------- +// SCU information +//--------------------------------------------------------- +#if ( AST1010_IOMAP == 1 ) + #define SCU_BASE AST_SCU_BASE +#endif +#if ( AST1010_IOMAP == 2 ) + #define SCU_BASE 0x0841000 +#endif + +#ifndef AST1010_IOMAP + #define SCU_BASE 0x1e6e2000 +#endif + +#define SCU_48h_AST1010 0x00000200 +#define SCU_48h_AST2300 0x00222255 + +//#ifdef SLT_DOS +// #define SCU_80h 0x00000000 +// #define SCU_88h 0x00000000 +// #define SCU_90h 0x00000000 +// #define SCU_74h 0x00000000 +//#else +// #define SCU_80h 0x0000000f //AST2300[3:0]MAC1~4 PHYLINK +// #define SCU_88h 0xc0000000 //AST2300[31]MAC1 MDIO, [30]MAC1 MDC +// #define SCU_90h 0x00000004 //AST2300[2 ]MAC2 MDC/MDIO +// #define SCU_74h 0x06300000 //AST3000[20]MAC2 MDC/MDIO, [21]MAC2 MII, [25]MAC1 PHYLINK, [26]MAC2 PHYLINK +//#endif + +//--------------------------------------------------------- +// DMA Buffer information +//--------------------------------------------------------- +#ifdef FPGA + #define DRAM_KByteSize ( 56 * 1024 ) +#else + #ifdef AST1010_IOMAP + #define DRAM_KByteSize ( 3 * 1024 ) // DATA buffer only use 0xB00000 to 0xE00000 + #else + #define DRAM_KByteSize ( 18 * 1024 ) + #endif +#endif + +#define DMA_BASE ( 0x00100000 + DRAM_MapAdr ) + +#ifdef Enable_Jumbo + #define DMA_PakSize ( 10 * 1024 ) +#else + #define DMA_PakSize ( 2 * 1024 ) // The size of one LAN packet +#endif + +#ifdef SelectSimpleBoundary + #define DMA_BufSize ( ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER +#else + #define DMA_BufSize (4 + ( ( ( ( DES_NUMBER + 15 ) * DMA_PakSize ) >> 2 ) << 2 ) ) //vary by DES_NUMBER +#endif + +#define DMA_BufNum ( ( DRAM_KByteSize * 1024 ) / ( DMA_BufSize ) ) //vary by DES_NUMBER +#define GET_DMA_BASE_SETUP ( DMA_BASE ) +#define GET_DMA_BASE(x) ( DMA_BASE + ( ( ( ( x ) % DMA_BufNum ) + 1 ) * DMA_BufSize ) )//vary by DES_NUMBER + +#define SEED_START 8 +#define DATA_SEED(seed) ( ( seed ) | (( seed + 1 ) << 16 ) ) +#define DATA_IncVal 0x00020001 +//#define DATA_IncVal 0x01000001 //fail +//#define DATA_IncVal 0x10000001 //fail +//#define DATA_IncVal 0x10000000 //fail +//#define DATA_IncVal 0x80000000 //fail +//#define DATA_IncVal 0x00000001 //ok +//#define DATA_IncVal 0x01000100 //ok +//#define DATA_IncVal 0x01010000 //ok +//#define DATA_IncVal 0x01010101 //ok +//#define DATA_IncVal 0x00000101 //ok +//#define DATA_IncVal 0x00001111 //fail +//#define DATA_IncVal 0x00000011 //fail +//#define DATA_IncVal 0x10100101 //fail +//#define DATA_IncVal 0xfeff0201 +//#define DATA_IncVal 0x00010001 +#define PktByteSize ( ( ( ( ZeroCopy_OFFSET + FRAME_LEN_Cur - 1 ) >> 2 ) + 1) << 2 ) + +//--------------------------------------------------------- +// Delay (ms) +//--------------------------------------------------------- +//#define Delay_DesGap 1000 //off +//#define Delay_DesGap 700 //off + +//#define Delay_ChkRxOwn 10 +//#define Delay_ChkTxOwn 10 +#define Delay_CntMax 100000000 +//#define Delay_CntMax 1000 +//#define Delay_CntMax 8465 +//#define Delay_CntMaxIncVal 50000 +#define Delay_CntMaxIncVal 47500 + +#define Delay_PHYRst 100 +#define Delay_PHYRd 5 + +#define Delay_SCU 11 +#define Delay_MACRst 1 +#define Delay_MACDump 100 + +//#define Delay_DES 1 + +//--------------------------------------------------------- +// Time Out +//--------------------------------------------------------- +#define TIME_OUT_Des 10000 +#define TIME_OUT_PHY_RW 10000 +#define TIME_OUT_PHY_Rst 10000 + +//#define TIME_OUT_NCSI 300000 +#define TIME_OUT_NCSI 30000 + + + +//--------------------------------------------------------- +// Chip memory MAP +//--------------------------------------------------------- +#define LITTLE_ENDIAN_ADDRESS 0 +#define BIG_ENDIAN_ADDRESS 1 + +typedef struct { + ULONG StartAddr; + ULONG EndAddr; +} LittleEndian_Area; + +#if ( AST1010_IOMAP == 1 ) + static const LittleEndian_Area LittleEndianArea[] = { + { AST_IO_BASE, (AST_IO_BASE + 0x000FFFFF) }, + { 0xFFFFFFFF, 0xFFFFFFFF } // End + }; +#else + static const LittleEndian_Area LittleEndianArea[] = { + { 0xFFFFFFFF, 0xFFFFFFFF } // End + }; +#endif + +// ======================================================== +// For ncsi.c + +#define DEF_PACKAGE2NUM 1 // Default value +#define DEF_CHANNEL2NUM 2 // Default value + +typedef struct { + unsigned char Package_ID; + unsigned char Channel_ID; + unsigned long Capabilities_Flags; + unsigned long Broadcast_Packet_Filter_Capabilities; + unsigned long Multicast_Packet_Filter_Capabilities; + unsigned long Buffering_Capabilities; + unsigned long AEN_Control_Support; + unsigned long PCI_DID_VID; + unsigned long ManufacturerID; +} NCSI_Capability; + +#undef GLOBAL +#ifdef NCSI_C +#define GLOBAL +#else +#define GLOBAL extern +#endif + +GLOBAL NCSI_Capability NCSI_Cap_SLT; +GLOBAL BYTE number_chl; + +GLOBAL char phy_ncsi (void); + +// ======================================================== +// For mactest + +#undef GLOBAL +#ifdef MACTEST_C +#define GLOBAL +#else +#define GLOBAL extern +#endif + +GLOBAL ULONG NCSI_DiSChannel; + +// +#ifdef SLT_UBOOT +#else +// SLT_DOS +GLOBAL FILE *fp_log; +GLOBAL FILE *fp_io; +#endif + +GLOBAL CHAR dlymap[16][16]; +GLOBAL CHAR PrintNCSIEn; +GLOBAL ULONG ARPNumCnt; +GLOBAL CHAR FileNameMain[256]; +GLOBAL CHAR FileName[256]; +GLOBAL CHAR ASTChipName[256]; +GLOBAL CHAR LOOP_Str[256]; +GLOBAL BYTE IOTimingBund; +GLOBAL BYTE ChannelTolNum; +GLOBAL BYTE PackageTolNum; +GLOBAL ULONG IOdly_out_reg; +GLOBAL BYTE IOdly_out_reg_idx; +GLOBAL ULONG Dat_ULONG; +GLOBAL ULONG IOdly_incval; +GLOBAL ULONG IOdly_in_reg; +GLOBAL BYTE IOdly_in_reg_idx; +GLOBAL ULONG *wp_lst; +GLOBAL ULONG *FRAME_LEN; +GLOBAL ULONG DES_NUMBER; +GLOBAL ULONG DES_NUMBER_Org; +GLOBAL int LOOP_MAX; +GLOBAL ULONG LOOP_CheckNum; +GLOBAL int Loop; +GLOBAL ULONG CheckBuf_MBSize; +GLOBAL ULONG Err_Flag; +GLOBAL ULONG SCU_f0h_old; +#ifdef AST1010_IOMAP + GLOBAL ULONG SCU_11Ch_old; +#endif +GLOBAL ULONG SCU_04h; +GLOBAL ULONG SCU_90h_old; +GLOBAL ULONG SCU_7ch_old; +GLOBAL ULONG MAC_50h; +GLOBAL ULONG SCU_ach_old; +GLOBAL ULONG SCU_70h_old; +GLOBAL ULONG MAC_50h_Speed; +GLOBAL ULONG SCU_48h_old; +GLOBAL ULONG SCU_48h_mix; +GLOBAL ULONG MAC_08h_old; +GLOBAL ULONG MAC_0ch_old; +GLOBAL ULONG MAC_40h_old; +GLOBAL ULONG SCU_08h_old; +GLOBAL ULONG MAC_PHYBASE; +GLOBAL ULONG LOOP_MAX_arg; +GLOBAL BYTE GRun_Mode; +GLOBAL ULONG GSpeed_idx; +GLOBAL CHAR GSpeed_sel[3]; +GLOBAL CHAR PHY_ADR; +GLOBAL CHAR PHY_ADR_arg; +GLOBAL CHAR PHYName[256]; +GLOBAL ULONG PHY_ID3; +GLOBAL ULONG PHY_ID2; +GLOBAL BYTE number_pak; +GLOBAL BYTE TestMode; +GLOBAL ULONG IOStr_i; +GLOBAL BYTE IOTimingBund_arg; +GLOBAL BYTE GSpeed; +GLOBAL BYTE GCtrl; +GLOBAL ULONG UserDVal; +GLOBAL ULONG H_MAC_BASE; +GLOBAL ULONG H_TDES_BASE; +GLOBAL ULONG H_RDES_BASE; +GLOBAL CHAR Loop_rl[3]; +GLOBAL CHAR IOTiming; +GLOBAL CHAR LOOP_INFINI; +GLOBAL CHAR SelectMAC; +GLOBAL CHAR Enable_SkipChkPHY; +GLOBAL CHAR Enable_MAC34; +GLOBAL CHAR IOStrength; +GLOBAL CHAR DataDelay; +GLOBAL CHAR SA[6]; +GLOBAL CHAR RxDataEnable; +GLOBAL CHAR IEEETesting; +GLOBAL CHAR BurstEnable; +GLOBAL CHAR MAC_Mode; +GLOBAL CHAR Enable_MACLoopback; +GLOBAL CHAR Enable_InitPHY; +GLOBAL CHAR MAC1_1GEn; +GLOBAL CHAR MAC2_RMII; +GLOBAL CHAR Enable_RMII; +GLOBAL CHAR MAC2_1GEn; +GLOBAL CHAR TxDataEnable; +GLOBAL CHAR AST2300_NewMDIO; +GLOBAL CHAR ASTChipType; +GLOBAL CHAR Err_Flag_PrintEn; +GLOBAL CHAR AST2400; +GLOBAL CHAR AST2300; +GLOBAL CHAR AST1100;//Different in phy & dram initiation & dram size & RMII +GLOBAL CHAR AST3200; +GLOBAL CHAR AST1010; +GLOBAL SCHAR IOdly_i_min; +GLOBAL SCHAR IOdly_j_min; +GLOBAL SCHAR IOdly_i_max; +GLOBAL SCHAR IOdly_j_max; +GLOBAL BYTE IOdly_i; +GLOBAL BYTE IOdly_j; +GLOBAL BYTE IOdly_in; +GLOBAL BYTE IOdly_out; +GLOBAL SCHAR IOdly_in_str; +GLOBAL BYTE IOdly_in_end; +GLOBAL BYTE IOdly_out_end; +GLOBAL BYTE IOdly_out_shf; +GLOBAL BYTE IOdly_in_shf; +GLOBAL SCHAR IOdly_out_str; +GLOBAL BYTE valary[16]; + +#define MODE_DEDICATED 0x01 +#define MODE_NSCI 0x02 +GLOBAL CHAR ModeSwitch; + +#ifdef SLT_UBOOT +#else + GLOBAL time_t timestart; +#endif + +#ifdef SPI_BUS + GLOBAL ULONG mmiobase; +#else + // ( USE_P2A | USE_LPC ) + GLOBAL UCHAR *mmiobase; + GLOBAL ULONG ulPCIBaseAddress; + GLOBAL ULONG ulMMIOBaseAddress; +#endif + + +// ======================================================== +// For mac.c +#undef GLOBAL +#ifdef MAC_C +#define GLOBAL +#else +#define GLOBAL extern +#endif + +GLOBAL ULONG ARP_data[16]; +GLOBAL ULONG NCSI_LinkFail_Val; +static const char version_name[] = VER_NAME; + +GLOBAL void Debug_delay (void); +GLOBAL void read_scu (void); +GLOBAL void Setting_scu (void); +GLOBAL void PrintMode (void); +GLOBAL void PrintPakNUm (void); +GLOBAL void PrintChlNUm (void); +GLOBAL void PrintTest (void); +GLOBAL void PrintIOTimingBund (void); +GLOBAL void PrintSpeed (void); +GLOBAL void PrintCtrl (void); +GLOBAL void PrintLoop (void); +GLOBAL void PrintPHYAdr (void); +GLOBAL void Finish_Close (void); +GLOBAL void Calculate_LOOP_CheckNum (void); +GLOBAL char Finish_Check (int value); +GLOBAL void init_scu1 (void); +GLOBAL void init_scu_macrst (void); +GLOBAL void setup_arp (void); +GLOBAL void TestingSetup (void); +GLOBAL void init_scu2 (void); +GLOBAL void init_scu3 (void); +GLOBAL void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase); +GLOBAL char TestingLoop (ULONG loop_checknum); +GLOBAL void PrintIO_Line_LOG (void); +GLOBAL void init_phy (int loop_phy); +GLOBAL void recov_phy (int loop_phy); +GLOBAL int FindErr (int value); +GLOBAL int FindErr_Des (int value); +GLOBAL void PrintIO_Header (BYTE option); +GLOBAL void Print_Header (BYTE option); +GLOBAL void PrintIO_LineS (BYTE option); +GLOBAL void PrintIO_Line (BYTE option); +GLOBAL void FPri_ErrFlag (BYTE option); + +#ifdef SUPPORT_PHY_LAN9303 +// ======================================================== +// For LAN9303.c +#undef GLOBAL +#ifdef LAN9303_C +#define GLOBAL +#else +#define GLOBAL extern +#endif + +GLOBAL void LAN9303(int num, int phy_adr, int speed, int int_loopback); +#endif // SUPPORT_PHY_LAN9303 +#endif // End COMMINF_H + diff --git a/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H new file mode 100644 index 0000000..02353e7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/DEF_SPI.H @@ -0,0 +1,35 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef DEF_SPI_H
+#define DEF_SPI_H
+
+#include "TYPEDEF.H"
+#include "SWFUNC.H"
+
+typedef struct _DEVICE_PCI_INFO
+{
+ USHORT usVendorID;
+ USHORT usDeviceID;
+ ULONG ulPCIConfigurationBaseAddress;
+ ULONG ulPhysicalBaseAddress;
+ ULONG ulMMIOBaseAddress;
+ USHORT usRelocateIO;
+} DEVICE_PCI_INFO;
+
+//VIDEO Engine Info
+typedef struct _VIDEO_ENGINE_INFO {
+ USHORT iEngVersion;
+ DEVICE_PCI_INFO VGAPCIInfo;
+} VIDEO_ENGINE_INFO;
+
+BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo);
+
+#endif // DEF_SPI_H
diff --git a/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c new file mode 100644 index 0000000..fe2b5cf --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/DRAM_SPI.c @@ -0,0 +1,78 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define DRAM_SPI_C
+static const char ThisFile[] = "DRAM_SPI.c";
+
+#include "SWFUNC.H"
+
+#ifdef SPI_BUS
+#include <stdio.h>
+#include "DEF_SPI.H"
+#include "LIB_SPI.H"
+
+VOID Set_MMIO_Base(ULONG PCI_BASE, ULONG addr)
+{
+ static ULONG MMIO_BASE = -1;
+
+ if(MMIO_BASE != (addr & 0xffff0000)){
+ if(MMIO_BASE == -1){
+ *(ULONG *)(PCI_BASE + 0xF000) = 1;
+ }
+ *(ULONG *)(PCI_BASE + 0xF004) = addr;
+ MMIO_BASE = addr & 0xffff0000;
+ }
+}
+
+VOID MOutbm(ULONG PCI_BASE, ULONG Offset, BYTE Data)
+{
+ Set_MMIO_Base(PCI_BASE, Offset);
+ *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
+}
+
+VOID MOutwm(ULONG PCI_BASE, ULONG Offset, USHORT Data)
+{
+ Set_MMIO_Base(PCI_BASE, Offset);
+ *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
+}
+
+VOID MOutdwm(ULONG PCI_BASE, ULONG Offset, ULONG Data)
+{
+ Set_MMIO_Base(PCI_BASE, Offset);
+ *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff)) = Data;
+}
+
+BYTE MInbm(ULONG PCI_BASE, ULONG Offset)
+{
+ BYTE jData;
+
+ Set_MMIO_Base(PCI_BASE, Offset);
+ jData = *(BYTE *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
+ return(jData);
+}
+
+USHORT MInwm(ULONG PCI_BASE, ULONG Offset)
+{
+ USHORT usData;
+
+ Set_MMIO_Base(PCI_BASE, Offset);
+ usData = *(USHORT *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
+ return(usData);
+}
+
+ULONG MIndwm(ULONG PCI_BASE, ULONG Offset)
+{
+ ULONG ulData;
+
+ Set_MMIO_Base(PCI_BASE, Offset);
+ ulData = *(ULONG *)(PCI_BASE + 0x10000 + (Offset & 0xffff));
+ return(ulData);
+}
+#endif // End SPI_BUS
diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.H b/arch/arm/cpu/arm926ejs/aspeed/IO.H new file mode 100644 index 0000000..5fe03f0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/IO.H @@ -0,0 +1,36 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef IO_H
+#define IO_H
+
+#include "SWFUNC.H"
+
+//
+// Macro
+//
+#if defined(LinuxAP)
+ #define delay(val) usleep(val*1000)
+ #define ob(p,d) outb(d,p)
+ #define ib(p) inb(p)
+#else
+ #define ob(p,d) outp(p,d)
+ #define ib(p) inp(p)
+#endif
+
+#ifdef USE_LPC
+void open_aspeed_sio_password(void);
+void enable_aspeed_LDU(BYTE jldu_number);
+int findlpcport(BYTE jldu_number);
+#endif
+
+void WriteSOC_DD(ULONG addr, ULONG data);
+ULONG ReadSOC_DD(ULONG addr);
+#endif
diff --git a/arch/arm/cpu/arm926ejs/aspeed/IO.c b/arch/arm/cpu/arm926ejs/aspeed/IO.c new file mode 100644 index 0000000..b06fdba --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/IO.c @@ -0,0 +1,355 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define IO_C
+static const char ThisFile[] = "IO.c";
+
+#include "SWFUNC.H"
+
+#if defined(LinuxAP)
+ #include <stdio.h>
+ #include <string.h>
+ #include <stdlib.h>
+ #include <stdarg.h>
+ #include <unistd.h>
+ #include <string.h>
+ #include <fcntl.h>
+ #include <pthread.h>
+ #include <sys/mman.h>
+ #include <sys/io.h>
+#endif
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+ #include <post.h>
+ #include <malloc.h>
+ #include <net.h>
+ #include "COMMINF.H"
+#endif
+#ifdef SLT_DOS
+ #include <stdlib.h>
+ #include <stdio.h>
+ #include <time.h>
+ #include <conio.h>
+ #include <dos.h>
+ #include <mem.h>
+ #include "TYPEDEF.H"
+ #include "LIB.H"
+ #include "COMMINF.H"
+#endif
+
+#include "TYPEDEF.H"
+#include "IO.H"
+#include "LIB_SPI.H"
+
+#ifdef SPI_BUS
+#endif
+#ifdef USE_LPC
+ USHORT usLPCPort;
+#endif
+#ifdef USE_P2A
+#endif
+
+#ifdef USE_LPC
+//------------------------------------------------------------
+// LPC access
+//------------------------------------------------------------
+void open_aspeed_sio_password(void)
+{
+ ob (usLPCPort, 0xaa);
+
+ ob (usLPCPort, 0xa5);
+ ob (usLPCPort, 0xa5);
+}
+
+//------------------------------------------------------------
+void close_aspeed_sio_password(void)
+{
+ ob (usLPCPort, 0xaa);
+}
+
+//------------------------------------------------------------
+void enable_aspeed_LDU(BYTE jldu_number)
+{
+ ob (usLPCPort, 0x07);
+ ob ((usLPCPort + 1), jldu_number);
+ ob (usLPCPort, 0x30);
+ ob ((usLPCPort + 1), 0x01);
+}
+
+//------------------------------------------------------------
+void disable_aspeed_LDU(BYTE jldu_number)
+{
+ ob (usLPCPort, 0x07);
+ ob ((usLPCPort + 1), jldu_number);
+ ob (usLPCPort, 0x30);
+ ob ((usLPCPort + 1), 0x00);
+}
+
+//------------------------------------------------------------
+/*
+ulAddress = AHB address
+jmode = 0: byte mode
+ 1: word mode
+ 2: dword mode
+*/
+static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
+{
+ ULONG uldata = 0;
+ ULONG ultemp = 0;
+ BYTE jtemp;
+
+ //Write Address
+ ob ( usLPCPort, 0xf0);
+ ob ( (usLPCPort + 1 ), ((ulAddress & 0xff000000) >> 24));
+ ob ( usLPCPort, 0xf1);
+ ob ( (usLPCPort + 1) , ((ulAddress & 0x00ff0000) >> 16));
+ ob ( usLPCPort, 0xf2);
+ ob ( (usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
+ ob ( usLPCPort, 0xf3);
+ ob ( (usLPCPort + 1), ulAddress & 0xff);
+
+ //Write Mode
+ ob (usLPCPort, 0xf8);
+ jtemp = ib ((usLPCPort + 1));
+ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
+
+ //Fire
+ ob (usLPCPort, 0xfe);
+ jtemp = ib ((usLPCPort + 1));
+
+ //Get Data
+ switch ( jmode )
+ {
+ case 0:
+ ob (usLPCPort, 0xf7);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp);
+ break;
+
+ case 1:
+ ob (usLPCPort, 0xf6);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp << 8);
+ ob (usLPCPort, 0xf7);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp << 0);
+ break;
+
+ case 2:
+ ob (usLPCPort, 0xf4);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp << 24);
+ ob (usLPCPort, 0xf5);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp << 16);
+ ob (usLPCPort, 0xf6);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= (ultemp << 8);
+ ob (usLPCPort, 0xf7);
+ ultemp = ib ((usLPCPort + 1));
+ uldata |= ultemp;
+ break;
+ } // End switch ( jmode )
+
+ return uldata;
+} // End static ULONG lpc_read (ULONG ulAddress, BYTE jmode)
+
+//------------------------------------------------------------
+static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
+{
+ BYTE jtemp;
+
+ //Write Address
+ ob ( usLPCPort, 0xf0);
+ ob ((usLPCPort + 1), ((ulAddress & 0xff000000) >> 24));
+ ob ( usLPCPort, 0xf1);
+ ob ((usLPCPort + 1), ((ulAddress & 0x00ff0000) >> 16));
+ ob ( usLPCPort, 0xf2);
+ ob ((usLPCPort + 1), ((ulAddress & 0x0000ff00) >> 8));
+ ob ( usLPCPort, 0xf3);
+ ob ((usLPCPort + 1), ulAddress & 0xff);
+
+ //Write Data
+ switch ( jmode )
+ {
+ case 0:
+ ob ( usLPCPort, 0xf7);
+ ob ((usLPCPort + 1), (uldata & 0xff));
+ break;
+ case 1:
+ ob ( usLPCPort, 0xf6);
+ ob ((usLPCPort + 1), ((uldata & 0xff00) >> 8));
+ ob ( usLPCPort, 0xf7);
+ ob ((usLPCPort + 1), (uldata & 0x00ff));
+ break;
+ case 2:
+ ob ( usLPCPort, 0xf4);
+ ob ((usLPCPort + 1), ((uldata & 0xff000000) >> 24));
+ ob ( usLPCPort, 0xf5);
+ ob ((usLPCPort + 1), ((uldata & 0x00ff0000) >> 16));
+ ob ( usLPCPort, 0xf6);
+ ob ((usLPCPort + 1), ((uldata & 0x0000ff00) >> 8));
+ ob ( usLPCPort, 0xf7);
+ ob ((usLPCPort + 1), uldata & 0xff);
+ break;
+ } // End switch ( jmode )
+
+ //Write Mode
+ ob (usLPCPort, 0xf8);
+ jtemp = ib ((usLPCPort + 1));
+ ob ((usLPCPort + 1), ((jtemp & 0xfc) | jmode));
+
+ //Fire
+ ob (usLPCPort, 0xfe);
+ ob ((usLPCPort + 1), 0xcf);
+
+} // End static void lpc_write (ULONG ulAddress, ULONG uldata, BYTE jmode)
+
+//------------------------------------------------------------
+static USHORT usLPCPortList[] = {0x2e, 0x4e, 0xff};
+int findlpcport(BYTE jldu_number)
+{
+ USHORT *jLPCPortPtr;
+ ULONG ulData;
+
+ jLPCPortPtr = usLPCPortList;
+ while (*(USHORT *)(jLPCPortPtr) != 0xff )
+ {
+ usLPCPort = *(USHORT *)(jLPCPortPtr++);
+
+ open_aspeed_sio_password();
+ enable_aspeed_LDU(0x0d);
+
+ ulData = lpc_read(0x1e6e207c, 2);
+
+ if ( (ulData != 0x00000000) &&
+ (ulData != 0xFFFFFFFF) )
+ {
+ printf("Find LPC IO port at 0x%2x \n", usLPCPort);
+ return 1;
+ }
+
+ disable_aspeed_LDU(0x0d);
+ close_aspeed_sio_password();
+ }
+
+ //printf("[Error] Fail to find proper LPC IO Port \n");
+ return 0;
+}
+#endif // End ifdef USE_LPC
+
+#ifdef USE_P2A
+//------------------------------------------------------------
+// A2P Access
+//------------------------------------------------------------
+void mm_write (ULONG addr, ULONG data, BYTE jmode)
+{
+ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
+ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
+
+ switch ( jmode )
+ {
+ case 0:
+ *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (BYTE) data;
+ break;
+ case 1:
+ *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = (USHORT) data;
+ break;
+ case 2:
+ default:
+ *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) = data;
+ break;
+ } //switch
+}
+
+//------------------------------------------------------------
+ULONG mm_read (ULONG addr, BYTE jmode)
+{
+ *(ULONG *) (mmiobase + 0xF004) = (ULONG) ((addr) & 0xFFFF0000);
+ *(ULONG *) (mmiobase + 0xF000) = (ULONG) 0x00000001;
+ switch (jmode)
+ {
+ case 0:
+ return ( *(BYTE *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
+ break;
+ case 1:
+ return ( *(USHORT *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
+ break;
+ default:
+ case 2:
+ return ( *(ULONG *) (mmiobase + 0x10000 + ((addr) & 0x0000FFFF)) );
+ break;
+ } //switch
+
+ return 0;
+}
+#endif // End ifdef USE_P2A
+
+//------------------------------------------------------------
+// General Access API
+//------------------------------------------------------------
+#ifdef SLT_UBOOT
+BYTE Check_BEorLN ( ULONG chkaddr )
+{
+ BYTE ret = BIG_ENDIAN_ADDRESS;
+ BYTE i = 0;
+
+ do {
+ if ( LittleEndianArea[i].StartAddr == LittleEndianArea[i].EndAddr )
+ break;
+
+ if ( ( LittleEndianArea[i].StartAddr <= chkaddr ) &&
+ ( LittleEndianArea[i].EndAddr >= chkaddr ) ) {
+ ret = LITTLE_ENDIAN_ADDRESS;
+ break;
+ }
+ i++;
+ } while ( 1 );
+
+ return ret;
+}
+#endif
+
+void WriteSOC_DD(ULONG addr, ULONG data)
+{
+#ifdef SLT_UBOOT
+ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
+ *(volatile unsigned long *)(addr) = cpu_to_le32(data);
+ else
+ *(volatile unsigned long *)(addr) = data;
+#else
+ #ifdef USE_LPC
+ lpc_write(addr, data, 2);
+ #endif
+ #ifdef USE_P2A
+ mm_write(addr, data, 2);
+ #endif
+#endif
+}
+
+//------------------------------------------------------------
+ULONG ReadSOC_DD(ULONG addr)
+{
+#ifdef SLT_UBOOT
+ if ( Check_BEorLN( addr ) == BIG_ENDIAN_ADDRESS )
+ return le32_to_cpu(*(volatile unsigned long *) (addr));
+ else
+ return (*(volatile unsigned long *) (addr));
+#else
+ #ifdef USE_LPC
+ return (lpc_read(addr, 2));
+ #endif
+ #ifdef USE_P2A
+ return (mm_read(addr, 2));
+ #endif
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c new file mode 100644 index 0000000..fdabd45 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/LAN9303.c @@ -0,0 +1,525 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define LAN9303_C
+static const char ThisFile[] = "LAN9303.c";
+
+#include "SWFUNC.H" +#ifdef SLT_UBOOT
+ #include "COMMINF.H" + #include "MAC.H" + #include "IO.H"
+#endif
+
+#ifdef SLT_DOS
+ #include "COMMINF.H"
+ #include <stdlib.h> + #include "IO.H" +#endif
+
+#ifdef SUPPORT_PHY_LAN9303 +//#define LAN9303M
+#define I2C_Debug 0
+#define Print_DWRW 0
+#define Print_PHYRW 0
+#define I2C_TIMEOUT 10000000
+
+ULONG devbase;
+ULONG busnum;
+ULONG byte;
+ULONG data_rd;
+
+//------------------------------------------------------------
+// Basic
+//------------------------------------------------------------
+void actime(ULONG ac1, ULONG ac2, ULONG *fact, ULONG *ckh, ULONG *ckl)
+{
+ static int divcnt;
+
+ ac1 = ac1 * 50 + 1;
+ ac2 = ac2 * 50 + 1;
+
+ divcnt = 0;
+ while (ac1 > 8 || ac2 > 8) {
+ divcnt++;
+ ac1 >>= 1;
+ ac2 >>= 1;
+ }
+
+ if (ac1 < 2 ) ac1 = 2;
+ if (ac2 < 2 ) ac2 = 2;
+ if (ac1 > ac2) ac2 = 1;
+ else ac1 += 1;
+
+#ifdef PRINT_MSG
+ printf("Divcnt = %d, ckdiv = %d, ckh = %d, ckl = %d\n",(1<<divcnt)*(ac1+ac2),divcnt,ac1-1,ac2-1);
+ printf("CKH = %d us, CKL = %d us\n",(1<<divcnt)*ac1/50,(1<<divcnt)*ac2/50);
+#endif
+
+ *fact = divcnt;
+ *ckh = ac1 - 1;
+ *ckl = ac2 - 1;
+}
+
+//------------------------------------------------------------
+ULONG PollStatus()
+{
+ static ULONG status;
+ static ULONG cnt = 0;
+
+ do {
+ status = ReadSOC_DD( devbase + 0x14 ) & 0xff;
+
+ if ( ++cnt > I2C_TIMEOUT ) {
+ printf("\nWait1 Timeout at bus %d!\n", busnum);
+ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
+ exit(0);
+ }
+ } while (status != 0);
+
+ cnt = 0;
+ do {
+ status = ReadSOC_DD( devbase + 0x10 );
+ if ( ++cnt > I2C_TIMEOUT ) {
+ printf("\nWait2 Timeout at bus %d!\n", busnum);
+ printf("Status 14 = %08x\n", ReadSOC_DD(devbase + 0x14));
+ exit(0);
+ }
+ } while (status == 0);
+
+ WriteSOC_DD( devbase + 0x10, status );
+
+ return(status);
+}
+
+
+//------------------------------------------------------------
+ULONG writeb(ULONG start, ULONG data, ULONG stop)
+{
+ WriteSOC_DD( devbase + 0x20, data);
+ WriteSOC_DD( devbase + 0x14, 0x02 | start | (stop << 5) );
+ return(PollStatus());
+}
+
+//------------------------------------------------------------
+ULONG readb(ULONG last, ULONG stop)
+{
+ static ULONG data;
+
+ WriteSOC_DD( devbase + 0x14, 0x08 | (last << 4) | (stop << 5) );
+ data = PollStatus();
+
+ if (data & 0x4) {
+ data = ReadSOC_DD( devbase + 0x20 );
+ return(data >> 8);
+ }
+ else {
+ return(-1);
+ }
+}
+
+//------------------------------------------------------------
+void Initial(ULONG base, ULONG ckh, ULONG ckl)
+{
+ static ULONG ackh;
+ static ULONG ackl;
+ static ULONG divx;
+
+ actime(ckh, ckl, &divx, &ackh, &ackl);
+ WriteSOC_DD(base + 0x00, 0x1);
+ if (ReadSOC_DD(base + 0x00) != 0x1) {
+ printf("Controller initial fail : %x\n",base);
+ exit(0);
+ }
+ WriteSOC_DD(base + 0x04, 0x77700360 | (ackh << 16) | (ackl << 12) | divx);
+ WriteSOC_DD(base + 0x08, 0x0);
+ WriteSOC_DD(base + 0x0c, 0x0);
+ WriteSOC_DD(base + 0x10, 0xffffffff);
+ WriteSOC_DD(base + 0x14, 0x00);
+ WriteSOC_DD(base + 0x1C, 0xff0000);
+ WriteSOC_DD(base + 0x20, 0x00);
+}
+
+//------------------------------------------------------------
+void print_status(ULONG status)
+{
+ if ( status & 0x02 ) printf( "Device NAK\n" );
+ if ( status & 0x08 ) printf( "Arbitration Loss\n" );
+ if ( status & 0x10 ) printf( "STOP\n" );
+ if ( status & 0x20 ) printf( "Abnormal STOP\n" );
+ if ( status & 0x40 ) printf( "SCL Low timeout\n" );
+}
+
+//------------------------------------------------------------
+void readme()
+{
+ printf("\nVersion:%s\n", version_name);
+#ifdef LAN9303M
+ printf("LAN9303M [bus] [vir_PHY_adr] [speed] [func]\n");
+#else
+ printf("LAN9303 [bus] [vir_PHY_adr] [speed] [func]\n" );
+#endif
+ printf("[bus] | 1~14: I2C bus number\n" );
+ printf("[vir_PHY_adr] | 0~1: virtual PHY address\n" );
+ printf("[speed] | 1: 100M\n" );
+ printf(" | 2: 10 M\n" );
+ printf("[func] | 0: external loopback\n" );
+ printf(" | 1: internal loopback\n" );
+}
+
+//------------------------------------------------------------
+void quit()
+{
+ WriteSOC_DD( devbase + 0x14, 0x20 );
+ PollStatus();
+ readme();
+}
+
+//------------------------------------------------------------
+// Double-Word Read/Write
+//------------------------------------------------------------
+ULONG I2C_DWRead(ULONG adr)
+{
+ static ULONG status;
+ int i;
+
+ Initial(devbase, 10, 10);
+
+ if ( Print_DWRW )
+ printf("RAdr %02x: ", adr);
+
+ status = writeb( 1, LAN9303_I2C_ADR, 0 ); + if ( I2C_Debug )
+ printf("R1W[%02x]%02x ", status, LAN9303_I2C_ADR); +
+ if ( status != 0x1 ) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+
+ status = writeb(0, adr, 0);
+ if ( I2C_Debug )
+ printf("R2W[%02x]%02x ", status, adr);
+ if ( !(status & 0x1) ) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+
+ status = writeb(1, LAN9303_I2C_ADR | 0x1, 0); + if ( I2C_Debug )
+ printf("R3W[%02x]%02x ", status, LAN9303_I2C_ADR | 0x1); + if ( status != 0x1 ) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+
+ if ( I2C_Debug )
+ printf("R4");
+
+ data_rd = 0;
+ for (i = 24; i >= 0; i-=8) {
+ if (i == 0) byte = readb(1, 1);
+ else byte = readb(0, 0);
+
+ if ( I2C_Debug )
+ printf("%02x ", byte);
+ data_rd = data_rd | (byte << i);
+ }
+
+ if ( Print_DWRW )
+ printf("%08x\n", data_rd);
+
+ return (data_rd);
+} // End ULONG I2C_DWRead(ULONG adr)
+
+//------------------------------------------------------------
+void I2C_DWWrite(ULONG adr, ULONG dwdata)
+{
+ static ULONG status;
+ int i;
+ ULONG endx;
+
+ Initial(devbase, 10, 10);
+ if (Print_DWRW)
+ printf("WAdr %02x: ", adr);
+
+ status = writeb(1, LAN9303_I2C_ADR, 0); + if ( I2C_Debug )
+ printf("W1[%02x]%02x ", status, LAN9303_I2C_ADR); + if ( status != 0x1 ) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+ status = writeb(0, adr, 0);
+ if ( I2C_Debug )
+ printf("W2[%02x]%02x ", status, adr);
+ if ( !(status & 0x1) ) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+
+ if (I2C_Debug)
+ printf("W3");
+ endx = 0;
+ for (i = 24; i >= 0; i-=8) {
+ if (i == 0)
+ endx = 1;
+ byte = (dwdata >> i) & 0xff;
+ status = writeb(0, byte, endx);
+
+ if (I2C_Debug)
+ printf("[%02x]%02x ", status, byte);
+ if (!(status & 0x1)) {
+ print_status(status);
+ quit();
+ exit(0);
+ }
+ }
+
+ if (Print_DWRW) printf("%08x\n", dwdata);
+} // End void I2C_DWWrite(ULONG adr, ULONG dwdata)
+
+//------------------------------------------------------------
+// PHY Read/Write
+//------------------------------------------------------------
+ULONG LAN9303_PHY_Read(ULONG phy_adr, ULONG reg_adr)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6));//[0A8h]PMI_ACCESS
+ do {
+ data_rd = I2C_DWRead (0x2a);
+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
+
+ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
+ if (Print_PHYRW)
+ printf("PHY:%2d, Reg:%2d, Data:%08x\n", phy_adr, reg_adr, data_rd);
+
+ return(data_rd);
+}
+
+//------------------------------------------------------------
+void LAN9303_PHY_Write(ULONG phy_adr, ULONG reg_adr, ULONG data_wr)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite(0x29, data_wr);//[0A4h]PMI_DATA
+
+ I2C_DWWrite(0x2a, ((phy_adr & 0x1f) << 11) | ((reg_adr & 0x1f) << 6) | 0x2);//[0A8h]PMI_ACCESS
+ do {
+ data_rd = I2C_DWRead (0x2a);
+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
+}
+
+//------------------------------------------------------------
+ULONG LAN9303_PHY_Read_WD(ULONG data_ctl)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite(0x2a, data_ctl);//[0A8h]PMI_ACCESS
+ do {
+ data_rd = I2C_DWRead (0x2a);
+ } while(data_rd & 0x00000001);//[0A8h]PMI_ACCESS
+
+ data_rd = I2C_DWRead (0x29);//[0A4h]PMI_DATA
+ if (Print_PHYRW)
+ printf("WD Data:%08x\n", data_ctl);
+
+ return(data_rd);
+}
+
+//------------------------------------------------------------
+void LAN9303_PHY_Write_WD(ULONG data_ctl, ULONG data_wr)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite( 0x29, data_wr ); //[0A4h]PMI_DATA
+ I2C_DWWrite( 0x2a, data_ctl ); //[0A8h]PMI_ACCESS
+ do {
+ data_rd = I2C_DWRead (0x2a);
+ } while(data_rd & 0x00000001); //[0A8h]PMI_ACCESS
+}
+
+//------------------------------------------------------------
+// Virtual PHY Read/Write
+//------------------------------------------------------------
+ULONG LAN9303_VirPHY_Read(ULONG reg_adr)
+{
+ static ULONG data_rd;
+
+ data_rd = I2C_DWRead (0x70+reg_adr);//[1C0h]
+ if ( Print_PHYRW )
+ printf("VirPHY Reg:%2d, Data:%08x\n", reg_adr, data_rd);
+
+ return(data_rd);
+}
+
+//------------------------------------------------------------
+void LAN9303_VirPHY_Write(ULONG reg_adr, ULONG data_wr)
+{
+ I2C_DWWrite(0x70+reg_adr, data_wr);//[1C0h]
+}
+
+//------------------------------------------------------------
+void LAN9303_VirPHY_RW(ULONG reg_adr, ULONG data_clr, ULONG data_set)
+{
+ I2C_DWWrite(0x70+reg_adr, (LAN9303_VirPHY_Read(reg_adr) & (~data_clr)) | data_set);//[1C0h]
+}
+
+//------------------------------------------------------------
+// PHY Read/Write
+//------------------------------------------------------------
+ULONG LAN9303_Read(ULONG adr)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite(0x6c, 0xc00f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
+ do {
+ data_rd = I2C_DWRead (0x6c);
+ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
+
+ return(I2C_DWRead (0x6b));//[1ACh]SWITCH_CSR_DATA
+}
+
+//------------------------------------------------------------
+void LAN9303_Write(ULONG adr, ULONG data)
+{
+ static ULONG data_rd;
+
+ I2C_DWWrite(0x6b, data);//[1ACh]SWITCH_CSR_DATA
+ I2C_DWWrite(0x6c, 0x800f0000 | adr & 0xffff);//[1B0h]SWITCH_CSR_CMD
+
+ do {
+ data_rd = I2C_DWRead (0x6c);
+ } while(data_rd & 0x80000000);//[1B0h]SWITCH_CSR_CMD
+}
+
+//------------------------------------------------------------
+void LAN9303(int num, int phy_adr, int speed, int int_loopback)
+{
+ static ULONG data_rd;
+
+ //------------------------------------------------------------
+ // I2C Initial
+ //------------------------------------------------------------
+ busnum = num;
+ if (busnum <= 7) devbase = 0x1E78A000 + ( busnum * 0x40);
+ else devbase = 0x1E78A300 + ((busnum-8) * 0x40);
+ Initial(devbase, 10, 10);
+
+ //------------------------------------------------------------
+ // LAN9303 Register Setting
+ //------------------------------------------------------------
+ printf("----> Start\n");
+ if (int_loopback == 0) {
+ //Force Speed & external loopback
+ if (speed == 1) { //100M
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); //adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); //adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
+ }
+ else {
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); //adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); //adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100);
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100);
+ }
+
+ LAN9303_Write( 0x180c, 0x00000001 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000010 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x00000002 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000011 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x00000003 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000012 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+#ifdef LAN9303M
+ LAN9303_Write( 0x180c, 0x00022001 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x00024002 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x0002a003 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+#else
+ LAN9303_Write( 0x180c, 0x0002a001 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000000 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x0000a002 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000001 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+
+ LAN9303_Write( 0x180c, 0x00022003 ); // SWE_VLAN_WR_DATA
+ LAN9303_Write( 0x180b, 0x00000002 ); // SWE_VLAN_CMD
+ do {data_rd = LAN9303_Read (0x1810);} while(data_rd & 0x1);
+#endif
+ LAN9303_Write( 0x1840, 0x00000007);
+ }
+ else if ( int_loopback == 1 ) {
+ //Force Speed & internal loopback
+ if ( speed == 1 ) {
+ //100M
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x6300 ); // adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x6300 ); // adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x6300 );
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x6300 );
+ }
+ else {
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x4100 ); // adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x4100 ); // adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x4100 );
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x4100 );
+ }
+ }
+ else {
+ //Force Speed
+ if (speed == 1) {
+ //100M
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x2300 ); // adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x2300 ); // adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x2300 );
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x2300 );
+ }
+ else {
+ LAN9303_VirPHY_RW( 0, 0xffff, 0x0100 ); // adr clr set //VPHY_BASIC_CTRL
+ LAN9303_VirPHY_RW( 11, 0xffff, 0x0100 ); // adr clr set //P1_MII_BASIC_CONTROL
+ LAN9303_PHY_Write( phy_adr + 1, 0, 0x0100 );
+ LAN9303_PHY_Write( phy_adr + 2, 0, 0x0100 );
+ }
+#ifdef LAN9303M
+#else
+ if (int_loopback == 3) {
+ //[LAN9303]IEEE measurement
+ data_rd = LAN9303_PHY_Read(phy_adr+1, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
+ LAN9303_PHY_Write(phy_adr+1, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
+
+ data_rd = LAN9303_PHY_Read(phy_adr+2, 27);//PHY_SPECIAL_CONTROL_STAT_IND_x
+ LAN9303_PHY_Write(phy_adr+2, 27, (data_rd & 0x9fff) | 0x8000);//PHY_SPECIAL_CONTROL_STAT_IND_x
+ }
+#endif
+ } // End if (int_loopback == 0)
+} // End void LAN9303(int num, int phy_adr, int speed, int int_loopback)
+#endif // SUPPORT_PHY_LAN9303 +
diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.H b/arch/arm/cpu/arm926ejs/aspeed/LIB.H new file mode 100644 index 0000000..a7c61dd --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.H @@ -0,0 +1,37 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef LIB_H
+#define LIB_H
+
+#include "TYPEDEF.H"
+
+//
+// Macro
+//
+#define INTFUNC int386
+
+#define OUTDWPORT outpd
+#define INDWPORT inpd
+#define OUTPUT outp
+#define INPUT inp
+
+//
+// PCI
+//
+ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask);
+ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType);
+VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData);
+
+//
+// Map Resource
+//
+ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize);
+#endif
diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB.c b/arch/arm/cpu/arm926ejs/aspeed/LIB.c new file mode 100644 index 0000000..f2a0c54 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/LIB.c @@ -0,0 +1,184 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define LIB_C
+static const char ThisFile[] = "LIB.c";
+
+#include "SWFUNC.H"
+
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+#endif
+#ifdef SLT_DOS
+#include <stdlib.h>
+#include <stdio.h>
+#include <time.h>
+#include <conio.h>
+#include <dos.h>
+#include <mem.h>
+#endif
+
+#include "LIB.H"
+#include "TYPEDEF.H"
+
+#ifdef USE_P2A
+//------------------------------------------------------------
+// PCI
+//------------------------------------------------------------
+ULONG ReadPCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask)
+{
+#ifndef Windows
+ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
+
+ return (((ULONG)INDWPORT(0xcfc)) & ulMask);
+#else
+ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
+
+ return (READ_PORT_ULONG((PULONG)0xcfc) & ulMask);
+#endif
+}
+
+//------------------------------------------------------------
+VOID WritePCIReg (ULONG ulPCIConfigAddress, BYTE jOffest, ULONG ulMask, ULONG ulData)
+{
+#ifndef Windows
+ OUTDWPORT(0xcf8, ulPCIConfigAddress + jOffest);
+ OUTDWPORT(0xcfc, (INDWPORT(0xcfc) & ulMask | ulData));
+#else
+ WRITE_PORT_ULONG((PULONG)0xcf8, ulPCIConfigAddress + jOffest);
+ WRITE_PORT_ULONG((PULONG)0xcfc, (READ_PORT_ULONG((PULONG)0xcfc) & ulMask | ulData));
+#endif
+}
+
+//------------------------------------------------------------
+ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
+{
+//Return: ulPCIConfigAddress
+//usBusType: ACTIVE/PCI/AGP/PCI-E
+
+ ULONG Base[256];
+ ULONG ebx;
+ USHORT i;
+ USHORT j;
+
+ for (i = 0; i < 256; i++) {
+ Base[i] = 0x80000000 + 0x10000 * i;
+ }
+
+ if (usBusType == PCI)
+ {
+ ebx = 0x80000000;
+ }
+ else if (usBusType == PCIE)
+ {
+ ebx = 0x80020000;
+ }
+ else // AGP and ACTIVE
+ {
+ ebx = 0x80010000;
+ }
+
+ if ( usBusType != ACTIVE ) //AGP, PCI, PCIE
+ {
+ for (i = 0; i < 32; i++)
+ {
+ ebx = ebx + (0x800);
+ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
+ {
+ return ebx;
+ }
+ }
+ return 0;
+ }
+ else //ACTIVE
+ {
+ for (j = 0; j < 256; j++)
+ {
+ ebx = Base[j];
+ for (i = 0; i < 32; i++)
+ {
+ ebx = ebx + (0x800);
+ if (((USHORT)ReadPCIReg(ebx, 0, 0xffff) == usVendorID) && ((USHORT)(ReadPCIReg(ebx, 0, 0xffff0000) >> 16) == usDeviceID))
+ {
+ return ebx;
+ }
+ }
+ }
+ return 0;
+ }
+} // End ULONG FindPCIDevice (USHORT usVendorID, USHORT usDeviceID, USHORT usBusType)
+#endif
+//------------------------------------------------------------
+// Allocate Resource
+//------------------------------------------------------------
+#ifdef SLT_DOS
+ULONG InitDOS32()
+{
+ union REGS regs ;
+
+ regs.w.ax = 0xee00;
+ INTFUNC(0x31, ®s, ®s) ;
+
+ if(regs.w.ax >= 0x301) // DOS32 version >= 3.01 ?
+ return 1;
+ else
+ return 0;
+}
+
+//------------------------------------------------------------
+USHORT CheckDOS()
+{
+ union REGS regs;
+
+ regs.w.ax = 0xeeff;
+ int386(0x31, ®s, ®s);
+ if (regs.x.eax == 0x504d4457)
+ {
+ return 0;
+ } else {
+ printf("PMODEW Init. fail\n");
+ return 1;
+ }
+}
+
+//------------------------------------------------------------
+ULONG MapPhysicalToLinear (ULONG ulBaseAddress, ULONG ulSize)
+{
+ union REGS regs;
+
+ regs.w.ax = 0x0800; // map physcial memory
+ regs.w.bx = ulBaseAddress >> 16; // bx:cx = physical address
+ regs.w.cx = ulBaseAddress;
+ regs.w.si = ulSize >> 16; // si:di = mapped memory block size
+ regs.w.di = ulSize;
+ INTFUNC(0x31, ®s, ®s); // int386(0x31, ®s, ®s);
+ if (regs.w.cflag == 0)
+ return (ULONG) (regs.w.bx << 16 + regs.w.cx); // Linear Addr = bx:cx
+ else
+ return 0;
+}
+
+//------------------------------------------------------------
+USHORT FreePhysicalMapping(ULONG udwLinAddress)
+{
+ union REGS regs;
+
+ regs.w.ax = 0x0801;
+ regs.w.bx = udwLinAddress >> 16;
+ regs.w.cx = udwLinAddress & 0xFFFF;
+ int386(0x31, ®s, ®s);
+
+ if (regs.x.cflag)
+ return ((USHORT) 0);
+ else return ((USHORT) 1);
+}
+#endif
+
diff --git a/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H new file mode 100644 index 0000000..78c8f1e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/LIB_SPI.H @@ -0,0 +1,23 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef LIB_SPI_H
+#define LIB_SPI_H
+
+#ifdef SPI_BUS
+ // MMIO Functions
+ VOID MOutwm (ULONG, ULONG, USHORT);
+ VOID MOutdwm (ULONG, ULONG, ULONG);
+ ULONG MIndwm (ULONG, ULONG);
+
+ void spim_init(int cs);
+#endif
+
+#endif // LIB_SPI_H
diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.H b/arch/arm/cpu/arm926ejs/aspeed/MAC.H new file mode 100644 index 0000000..6732117 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.H @@ -0,0 +1,157 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef MAC_H
+#define MAC_H
+
+#ifdef SPI_BUS
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <time.h>
+ #define SPI_CS 1
+#endif
+// ( USE_P2A | USE_LPC )
+
+#if defined(LinuxAP)
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <stdarg.h>
+ #include <unistd.h>
+ #include <string.h>
+ #include <fcntl.h>
+ #include <pthread.h>
+ #include <sys/mman.h>
+ #include <sys/io.h>
+#endif
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+#endif
+#ifdef SLT_DOS
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <time.h>
+ #include <conio.h>
+ #include <dos.h>
+ #include <mem.h>
+#endif
+
+#include "NCSI.H"
+#include "IO.H"
+
+// --------------------------------------------------------------
+// Define
+// --------------------------------------------------------------
+
+//#define Force_Enable_MAC34 //[ON][SLT:off] (Force enable mac34)
+//#define Force_Enable_NewMDIO //[off][SLT:off] (Force enable new MDC/MDIO)
+//#define Enable_Fast_SCU //[off]
+//#define Enable_Old_Style //[off]
+#define ENABLE_DASA //[ON]
+//#define Enable_AST2300_Int125MHz //[off]
+//#define ENABLE_ARP_2_WOL //[off]
+//#define Enable_MAC_SWRst //[off]
+
+#define Enable_Runt
+//#define Enable_Jumbo
+//#define Enable_BufMerge
+//#define Disable_VGA
+
+//#define SelectSimpleBoundary //[off] Using in debug
+//#define SelectSimpleData //[off] Using in debug
+//#define SelectSimpleLength 1512 //[off] 60(0x3c) ~ 1514(0x5ea); 1512(0x5e8)
+//#define SelectDesNumber 8 //[off] 1 ~
+//#define SelectSimpleDA //[off] Using in debug
+//#define SelectSimpleDes //[off]
+//#define SelectLengthInc //[off] Using in debug
+
+#define SimpleData_Fix //[ON] Using in debug
+#define SimpleData_FixNum 12
+#define SimpleData_FixVal00 0x00000000 //[0]no SelectSimpleDA: (60: 0412 8908)(1512: e20d e9da)
+#define SimpleData_FixVal01 0xffffffff //[0]no SelectSimpleDA: (60: f48c f14d)(1512: af05 260c)
+#define SimpleData_FixVal02 0x55555555 //[0]no SelectSimpleDA: (60: 5467 5ecb)(1512: d90a 5368)
+#define SimpleData_FixVal03 0xaaaaaaaa //[0]no SelectSimpleDA: (60: a4f9 268e)(1512: 9402 9cbe)
+#define SimpleData_FixVal04 0x5a5a5a5a //[1]no SelectSimpleDA: (60: 7f01 e22d)(1512: 4fd3 8012)
+#define SimpleData_FixVal05 0xc3c3c3c3 //[1]no SelectSimpleDA: (60: 5916 02d5)(1512: 99f1 6127)
+#define SimpleData_FixVal06 0x96969696 //[1]no SelectSimpleDA: (60: 0963 d516)(1512: a2f6 db95)
+#define SimpleData_FixVal07 0xf0f0f0f0 //[1]no SelectSimpleDA: (60: dfea 4dab)(1512: 39dc f576)
+#define SimpleData_FixVal08 0x5555aaaa //[2]no SelectSimpleDA: (60: b61b 5777)(1512: 4652 ddb0)
+#define SimpleData_FixVal09 0xffff0000 //[2]no SelectSimpleDA: (60: 16f0 f8f1)(1512: 305d a8d4)
+#define SimpleData_FixVal10 0x5a5aa5a5 //[2]no SelectSimpleDA: (60: 9d7d eb91)(1512: d08b 0eca)
+#define SimpleData_FixVal11 0xc3c33c3c //[2]no SelectSimpleDA: (60: bb6a 0b69)(1512: 06a9 efff)
+
+#define SelectSimpleDA_Dat0 0x67052301
+#define SelectSimpleDA_Dat1 0xe0cda089
+#define SelectSimpleDA_Dat2 0x98badcfe
+
+#define SelectWOLDA_DatH 0x206a
+#define SelectWOLDA_DatL 0x8a374d9b
+
+#define MOVE_DATA_MB_SEC 800 // MByte per second to move data
+
+//---------------------------------------------------------
+// Frame size
+//---------------------------------------------------------
+#define ENABLE_RAND_SIZE 0
+#define Rand_Sed 0xffccd
+#define FRAME_Rand_Simple 0
+#define MIN_FRAME_RAND_SIZE 60
+#define MAX_FRAME_RAND_SIZE 1514
+
+#define FRAME_SELH_PERD 7
+#ifdef Enable_Jumbo
+// #define FRAME_LENH 9212 //max:9212
+// #define FRAME_LENL 9211 //max:9212
+ #define FRAME_LENH 9212 //max:9212
+ #define FRAME_LENL 9212 //max:9212
+// #define FRAME_LENH 8120
+// #define FRAME_LENL 8119
+// #define FRAME_LENH 7000
+// #define FRAME_LENL 6999
+// #define FRAME_LENH 4095
+// #define FRAME_LENL 4094
+// #define FRAME_LENH 2040
+// #define FRAME_LENL 2039
+#else
+ #ifdef SelectSimpleLength
+// #define FRAME_LENH ( SelectSimpleLength + 1 )
+// #define FRAME_LENL ( SelectSimpleLength )
+ #define FRAME_LENH SelectSimpleLength
+ #define FRAME_LENL SelectSimpleLength
+ #else
+// #define FRAME_LENH 1514 //max:1514
+// #define FRAME_LENL 1513 //max:1514
+ #define FRAME_LENH 1514 //max:1514
+ #define FRAME_LENL 1514 //max:1514
+ #endif
+#endif
+
+const ULONG ARP_org_data[16] = {
+ 0xffffffff,
+ 0x0000ffff, // SA:00 00
+ 0x12345678, // SA:12 34 56 78
+ 0x01000608, // ARP(0x0806)
+ 0x04060008,
+ 0x00000100, // sender MAC Address: 00 00
+ 0x12345678, // sender MAC Address: 12 34 56 78
+ 0xeb00a8c0, // sender IP Address: 192.168.0.235
+ 0x00000000, // target MAC Address: 00 00 00 00
+ 0xa8c00000, // target MAC Address: 00 00, sender IP Address:192.168
+ 0x00000100, // sender IP Address: 0.1
+// 0x0000de00, // sender IP Address: 0.222
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xc68e2bd5
+};
+
+#endif // MAC_H
diff --git a/arch/arm/cpu/arm926ejs/aspeed/MAC.c b/arch/arm/cpu/arm926ejs/aspeed/MAC.c new file mode 100644 index 0000000..b4182f5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/MAC.c @@ -0,0 +1,2083 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define MAC_C
+static const char ThisFile[] = "MAC.c";
+
+#include "SWFUNC.H"
+
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+ #include "COMMINF.H"
+ #include "STDUBOOT.H"
+#endif
+#ifdef SLT_DOS
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <conio.h>
+ #include <string.h>
+ #include "COMMINF.H"
+#endif
+
+#include "MAC.H"
+
+double Avg_frame_len;
+ULONG Check_Des_Val;
+ULONG wp_fir;
+ULONG wp;
+ULONG FRAME_LEN_Cur;
+ULONG gdata;
+ULONG CheckDesFail_DesNum;
+ULONG VGAMode;
+ULONG SCU_1ch_old;
+ULONG SCU_0ch_old;
+ULONG SCU_48h_default;
+ULONG SCU_2ch_old;
+ULONG SCU_80h_old;
+ULONG SCU_74h_old;
+ULONG SCU_a4h_old;
+ULONG SCU_88h_old;
+ULONG WDT_0ch_old;
+ULONG SCU_04h_mix;
+ULONG SCU_04h_old;
+ULONG WDT_2ch_old;
+char SCU_oldvld = 0;
+
+#ifdef SLT_UBOOT
+#else
+ static double timeused;
+#endif
+// -------------------------------------------------------------
+
+void Debug_delay (void) {
+ #ifdef DbgPrn_Enable_Debug_delay
+ GET_CAHR();
+ #endif
+}
+
+
+
+
+void dump_mac_ROreg (void) {
+ DELAY(Delay_MACDump);
+ printf("\n");
+ printf("[MAC-H] ROReg A0h~ACh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xA0), ReadSOC_DD(H_MAC_BASE+0xA4), ReadSOC_DD(H_MAC_BASE+0xA8), ReadSOC_DD(H_MAC_BASE+0xAC));
+ printf("[MAC-H] ROReg B0h~BCh: %08lx %08lx %08lx %08lx\n", ReadSOC_DD(H_MAC_BASE+0xB0), ReadSOC_DD(H_MAC_BASE+0xB4), ReadSOC_DD(H_MAC_BASE+0xB8), ReadSOC_DD(H_MAC_BASE+0xBC));
+ printf("[MAC-H] ROReg C0h~C8h: %08lx %08lx %08lx \n", ReadSOC_DD(H_MAC_BASE+0xC0), ReadSOC_DD(H_MAC_BASE+0xC4), ReadSOC_DD(H_MAC_BASE+0xC8));
+}
+
+//------------------------------------------------------------
+// SCU
+//------------------------------------------------------------
+void recov_scu (void) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("recov_scu\n");
+ Debug_delay();
+ #endif
+
+ //MAC
+ WriteSOC_DD( H_MAC_BASE + 0x08, MAC_08h_old );
+ WriteSOC_DD( H_MAC_BASE + 0x0c, MAC_0ch_old );
+ WriteSOC_DD( H_MAC_BASE + 0x40, MAC_40h_old );
+
+ //SCU
+ WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old );
+ WriteSOC_DD( SCU_BASE + 0x08, SCU_08h_old );
+ WriteSOC_DD( SCU_BASE + 0x0c, SCU_0ch_old );
+ WriteSOC_DD( SCU_BASE + 0x1c, SCU_1ch_old );
+ WriteSOC_DD( SCU_BASE + 0x2c, SCU_2ch_old );
+ WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_old );
+// WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old );
+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old );
+ WriteSOC_DD( SCU_BASE + 0x7c, SCU_7ch_old );
+ WriteSOC_DD( SCU_BASE + 0x80, SCU_80h_old );
+ WriteSOC_DD( SCU_BASE + 0x88, SCU_88h_old );
+ WriteSOC_DD( SCU_BASE + 0x90, SCU_90h_old );
+ WriteSOC_DD( SCU_BASE + 0xa4, SCU_a4h_old );
+ WriteSOC_DD( SCU_BASE + 0xac, SCU_ach_old );
+ #ifdef AST1010_IOMAP
+ WriteSOC_DD( SCU_BASE + 0x11C, SCU_11Ch_old );
+ #endif
+
+ //WDT
+ #ifdef AST1010_IOMAP
+ #else
+ // WriteSOC_DD(0x1e78500c, WDT_0ch_old);
+ // WriteSOC_DD(0x1e78502c, WDT_2ch_old);
+ #endif
+
+ if ( ASTChipType == 3 ) {
+ if ( SCU_f0h_old & 0x01 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //Enable MAC34
+ if ( SCU_f0h_old & 0x02 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x2000DEEA ); //Enable Decode
+ if ( SCU_f0h_old & 0x04 ) WriteSOC_DD( SCU_BASE + 0xf0, 0xA0E0E0D3 ); //Enable I2S
+ if ( SCU_f0h_old & 0x08 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x4D0E0E0A ); //Enable PCI Host
+ if ( SCU_f0h_old & 0x10 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x10ADDEED ); //Enable IR
+ if ( SCU_f0h_old & 0x20 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 ); //Enabel Buffer Merge
+ if ( SCU_f0h_old & 0x40 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68961A33 ); //Enable PS2 IO
+ if ( SCU_f0h_old & 0x80 ) WriteSOC_DD( SCU_BASE + 0xf0, 0x68971A33 ); //Enable PS2 IO
+ }
+} // End void recov_scu (void)
+
+void read_scu (void) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("read_scu\n");
+ Debug_delay();
+ #endif
+
+ if (!SCU_oldvld) {
+ //SCU
+ SCU_04h_old = ReadSOC_DD( SCU_BASE + 0x04 );
+ SCU_08h_old = ReadSOC_DD( SCU_BASE + 0x08 );
+ SCU_0ch_old = ReadSOC_DD( SCU_BASE + 0x0c );
+ SCU_1ch_old = ReadSOC_DD( SCU_BASE + 0x1c );
+ SCU_2ch_old = ReadSOC_DD( SCU_BASE + 0x2c );
+ SCU_48h_old = ReadSOC_DD( SCU_BASE + 0x48 );
+ SCU_70h_old = ReadSOC_DD( SCU_BASE + 0x70 );
+ SCU_74h_old = ReadSOC_DD( SCU_BASE + 0x74 );
+ SCU_7ch_old = ReadSOC_DD( SCU_BASE + 0x7c );
+ SCU_80h_old = ReadSOC_DD( SCU_BASE + 0x80 );
+ SCU_88h_old = ReadSOC_DD( SCU_BASE + 0x88 );
+ SCU_90h_old = ReadSOC_DD( SCU_BASE + 0x90 );
+ SCU_a4h_old = ReadSOC_DD( SCU_BASE + 0xa4 );
+ SCU_ach_old = ReadSOC_DD( SCU_BASE + 0xac );
+ SCU_f0h_old = ReadSOC_DD( SCU_BASE + 0xf0 );
+ #ifdef AST1010_IOMAP
+ SCU_11Ch_old = ReadSOC_DD( SCU_BASE + 0x11C );
+ #endif
+
+ //WDT
+ #ifdef AST1010_IOMAP
+ #else
+ WDT_0ch_old = ReadSOC_DD( 0x1e78500c );
+ WDT_2ch_old = ReadSOC_DD( 0x1e78502c );
+ #endif
+
+ SCU_oldvld = 1;
+ } // End if (!SCU_oldvld)
+} // End read_scu()
+
+void Setting_scu (void)
+{
+ //SCU
+ if (AST1010) {
+ do {
+ WriteSOC_DD( SCU_BASE + 0x00 , 0x1688a8a8);
+ #ifndef SLT_UBOOT
+ WriteSOC_DD( SCU_BASE + 0x70 , SCU_70h_old & 0xfffffffe); // Disable CPU
+ #endif
+ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
+
+ #if( AST1010_IOMAP == 1)
+ WriteSOC_DD( SCU_BASE + 0x11C, 0x00000000); // Disable Cache functionn
+ #endif
+ }
+ else {
+ do {
+ WriteSOC_DD( SCU_BASE + 0x00, 0x1688a8a8);
+ #ifndef SLT_UBOOT
+ WriteSOC_DD( SCU_BASE + 0x70, SCU_70h_old | 0x3 ); // Disable CPU
+ #endif
+ } while ( ReadSOC_DD( SCU_BASE + 0x00 ) != 0x1 );
+ } // End if (AST1010)
+
+ //WDT
+ #ifdef AST1010_IOMAP
+ #else
+ WriteSOC_DD( 0x1e78500c, WDT_0ch_old & 0xfffffffc );
+ WriteSOC_DD( 0x1e78502c, WDT_2ch_old & 0xfffffffc );
+ #endif
+}
+
+//------------------------------------------------------------
+void init_scu1 (void) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("init_scu1\n");
+ Debug_delay();
+ #endif
+
+ if (AST3200) {
+ WriteSOC_DD( SCU_BASE + 0x0c, (SCU_0ch_old & 0xffefffff) );//Clock Stop Control
+ }
+ else if (AST1010) {
+ WriteSOC_DD( SCU_BASE + 0x0c, ( SCU_0ch_old & 0xffffffbf ) );//Clock Stop Control
+ WriteSOC_DD( SCU_BASE + 0x88, ((SCU_88h_old & 0x003fffff ) | 0xffc00000) );//Multi-function Pin Control
+ }
+ else if (AST2300) {
+#ifdef Enable_BufMerge
+ WriteSOC_DD( SCU_BASE + 0xf0, 0x66559959 );//MAC buffer merge
+#endif
+
+#ifdef Enable_AST2300_Int125MHz
+ SCU_48h_mix = (SCU_48h_old & 0xf0000000) | 0x80000000;
+// WriteSOC_DD( SCU_BASE + 0xf0, 0xa0e0e0d3 );//Enable I2S
+// WriteSOC_DD( SCU_BASE + 0x04, SCU_04h_old & 0xfffdffff );//Rst(Enable I2S)
+//
+//// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00010000 );//P_I2SPLLAdjEnable
+// WriteSOC_DD( 0x1e6e5020, ReadSOC_DD(0x1e6e5020) | 0x00000000 );//P_I2SPLLAdjEnable
+// WriteSOC_DD( 0x1e6e5024, 0x00000175 );//P_I2SPLLAdjCnt
+
+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a51a );//124800000(24MHz)
+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000a92f );//125333333(24MHz)
+// WriteSOC_DD( SCU_BASE + 0x1c, 0x0000587d );//125000000(24MHz)
+ WriteSOC_DD( SCU_BASE + 0x1c, 0x00006c7d );//125000000(24MHz)
+ WriteSOC_DD( SCU_BASE + 0x2c, 0x00300000 | (SCU_2ch_old & 0xffcfffef) );//D-PLL assigned to VGA, D2-PLL assigned to I2S.
+ WriteSOC_DD( SCU_BASE + 0x48, 0x80000000 | SCU_48h_old );//125MHz come from I2SPLL
+#else
+ SCU_48h_mix = (SCU_48h_old & 0xf0000000);
+#endif
+ switch (SelectMAC) {
+ case 0 :
+ WriteSOC_DD( SCU_BASE + 0x88, (SCU_88h_old & 0x3fffffff) | 0xc0000000 );//[31]MAC1 MDIO, [30]MAC1 MDC
+ break;
+ case 1 :
+ WriteSOC_DD( SCU_BASE + 0x90, (SCU_90h_old & 0xfffffffb) | 0x00000004 );//[2 ]MAC2 MDC/MDIO
+ break;
+ case 2 :
+ case 3 :
+ default : break;
+ }
+
+ WriteSOC_DD(SCU_BASE+0x0c, (SCU_0ch_old & 0xff0fffff) );//Clock Stop Control
+// WriteSOC_DD(SCU_BASE+0x80, (SCU_80h_old & 0xfffffff0) | 0x0000000f);//MAC1LINK/MAC2LINK
+ }
+ else {
+ switch (SelectMAC) {
+ case 0 :
+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfdffffff) | 0x02000000);//[25]MAC1 PHYLINK
+ break;
+ case 1 :
+ if (MAC2_RMII) {
+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbefffff) | 0x04100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
+ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffefffff) | 0x00100000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
+ } else {
+// WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xfbcfffff) | 0x04300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
+ WriteSOC_DD(SCU_BASE+0x74, (SCU_74h_old & 0xffcfffff) | 0x00300000);//[26]MAC2 PHYLINK, [21]MAC2 MII, [20]MAC2 MDC/MDIO
+ }
+ break;
+ default : break;
+ } // End switch (SelectMAC)
+ } // End if (AST3200)
+} // End void init_scu1 (void)
+
+//------------------------------------------------------------
+void init_scu_macrst (void) {
+
+#ifdef Enable_AST2300_Int125MHz
+ if (ASTChipType == 3) {
+ SCU_04h_mix = SCU_04h_old & 0xfffdffff;
+ } else {
+ SCU_04h_mix = SCU_04h_old;
+ }
+#else
+ SCU_04h_mix = SCU_04h_old;
+#endif
+
+ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) | SCU_04h);//Rst
+ DELAY(Delay_SCU);
+ WriteSOC_DD ( SCU_BASE + 0x04, (SCU_04h_mix & ~SCU_04h) );//Enable Engine
+// DELAY(Delay_SCU);
+} // End void init_scu_macrst (void)
+
+//------------------------------------------------------------
+void init_scu2 (void) {
+
+#ifdef SCU_74h
+ #ifdef DbgPrn_FuncHeader
+ printf ("init_scu2\n");
+ Debug_delay();
+ #endif
+
+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | SCU_74h );//PinMux
+ delay(Delay_SCU);
+#endif
+
+} // End void init_scu2 (void)
+
+//------------------------------------------------------------
+void init_scu3 (void) {
+
+#ifdef SCU_74h
+ #ifdef DbgPrn_FuncHeader
+ printf ("init_scu3\n");
+ Debug_delay();
+ #endif
+
+ WriteSOC_DD( SCU_BASE + 0x74, SCU_74h_old | (SCU_74h & 0xffefffff) );//PinMux
+ delay(Delay_SCU);
+#endif
+
+} // End void init_scu3 (void)
+
+//------------------------------------------------------------
+// MAC
+//------------------------------------------------------------
+void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("init_mac\n");
+ Debug_delay();
+ #endif
+
+#ifdef Enable_MAC_SWRst
+ WriteSOC_DD( base + 0x50, 0x80000000 | MAC_50h | MAC_50h_Speed);
+// WriteSOC_DD( base + 0x50, 0x80000000);
+
+ while (0x80000000 & ReadSOC_DD(base+0x50)) {
+//printf(".");
+ DELAY(Delay_MACRst);
+ }
+ DELAY(Delay_MACRst);
+#endif
+
+ WriteSOC_DD( base + 0x20, (tdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+ WriteSOC_DD( base + 0x24, (rdexbase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+
+#ifdef MAC_30h
+ WriteSOC_DD( base + 0x30, MAC_30h);//Int Thr/Cnt
+#endif
+
+#ifdef MAC_34h
+ WriteSOC_DD( base + 0x34, MAC_34h);//Poll Cnt
+#endif
+
+#ifdef MAC_38h
+ WriteSOC_DD( base + 0x38, MAC_38h);
+#endif
+
+#ifdef MAC_40h
+ if (Enable_MACLoopback) {
+ if (AST2300_NewMDIO) WriteSOC_DD( base + 0x40, MAC_40h | 0x80000000);
+ else WriteSOC_DD( base + 0x40, MAC_40h);
+ }
+#endif
+
+#ifdef MAC_48h
+ WriteSOC_DD( base + 0x48, MAC_48h);
+#endif
+
+ if ( ModeSwitch == MODE_NSCI )
+ WriteSOC_DD( base + 0x4c, NCSI_RxDMA_PakSize);
+ else
+ WriteSOC_DD( base + 0x4c, DMA_PakSize);
+
+ WriteSOC_DD( base + 0x50, MAC_50h | MAC_50h_Speed | 0xf);
+ DELAY(Delay_MACRst);
+} // End void init_mac (ULONG base, ULONG tdexbase, ULONG rdexbase)
+
+//------------------------------------------------------------
+// Basic
+//------------------------------------------------------------
+void FPri_RegValue (BYTE option) {
+
+#ifdef SLT_UBOOT
+#else
+ time_t timecur;
+#endif
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ PRINT(OUT_OBJ "[SCU] 04:%08lx 08:%08lx 0c:%08lx 48:%08lx\n", SCU_04h_old, SCU_08h_old, SCU_0ch_old, SCU_48h_old);
+ PRINT(OUT_OBJ "[SCU] 70:%08lx 74:%08lx 7c:%08lx\n", SCU_70h_old, SCU_74h_old, SCU_7ch_old);
+ PRINT(OUT_OBJ "[SCU] 80:%08lx 88:%08lx 90:%08lx f0:%08lx\n", SCU_80h_old, SCU_88h_old, SCU_90h_old, SCU_f0h_old);
+ PRINT(OUT_OBJ "[SCU] a4:%08lx ac:%08lx\n", SCU_a4h_old, SCU_ach_old);
+ PRINT(OUT_OBJ "[WDT] 0c:%08lx 2c:%08lx\n", WDT_0ch_old, WDT_2ch_old);
+ PRINT(OUT_OBJ "[MAC] 08:%08lx 0c:%08lx\n", MAC_08h_old, MAC_0ch_old);
+ PRINT(OUT_OBJ "[MAC] A0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xa0), ReadSOC_DD( MAC_PHYBASE + 0xa4 ), ReadSOC_DD( MAC_PHYBASE + 0xa8 ), ReadSOC_DD(MAC_PHYBASE + 0xac ) );
+ PRINT(OUT_OBJ "[MAC] B0|%08lx %08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xb0), ReadSOC_DD( MAC_PHYBASE + 0xb4 ), ReadSOC_DD( MAC_PHYBASE + 0xb8 ), ReadSOC_DD(MAC_PHYBASE + 0xbc ) );
+ PRINT(OUT_OBJ "[MAC] C0|%08lx %08lx %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0xc0), ReadSOC_DD( MAC_PHYBASE + 0xc4 ), ReadSOC_DD( MAC_PHYBASE + 0xc8 ));
+
+#ifdef SLT_UBOOT
+#else
+ fprintf(fp, "Time: %s", ctime(×tart));
+ time(&timecur);
+ fprintf(fp, "----> %s", ctime(&timecur));
+#endif
+} // End void FPri_RegValue (BYTE *fp)
+
+//------------------------------------------------------------
+void FPri_End (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ if ( !RxDataEnable ) {
+ }
+ else if ( Err_Flag ) {
+ PRINT(OUT_OBJ " \n----> fail !!!\n");
+ } else {
+ PRINT(OUT_OBJ " \n----> All Pass !!!\n");
+ }
+
+ if ( ModeSwitch == MODE_DEDICATED ) {
+ if (PHY_ADR_arg != PHY_ADR)
+ PRINT(OUT_OBJ "\n[Warning] PHY Address change from %d to %d !!!\n", PHY_ADR_arg, PHY_ADR);
+ }
+
+ if ( AST1010 ) {
+ Dat_ULONG = (SCU_ach_old >> 12) & 0xf;
+ if (Dat_ULONG) {
+ PRINT(OUT_OBJ "\n[Warning] SCUAC[15:12] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
+ }
+
+ SCU_48h_default = SCU_48h_AST1010 & 0x01000f00;
+ if ((SCU_48h_old != SCU_48h_default)) {
+ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
+ }
+ }
+ else if ( AST2300 ) {
+ if ( AST2400 ) {
+ Dat_ULONG = (SCU_90h_old >> 8) & 0xf;
+ if (Dat_ULONG) {
+ PRINT(OUT_OBJ "\n[Warning] SCU90[11: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
+ }
+ }
+ else {
+ Dat_ULONG = (SCU_90h_old >> 8) & 0xff;
+ if (Dat_ULONG) {
+ PRINT(OUT_OBJ "\n[Warning] SCU90[15: 8] == 0x%02lx is not the suggestion value 0.\n", Dat_ULONG);
+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
+ }
+ }
+
+ if (Enable_MAC34) SCU_48h_default = SCU_48h_AST2300;
+ else SCU_48h_default = SCU_48h_AST2300 & 0x0300ffff;
+
+ if ((SCU_48h_old != SCU_48h_default)) {
+ PRINT(OUT_OBJ "\n[Warning] SCU48 == 0x%08lx is not the suggestion value 0x%08lx.\n", SCU_48h_old, SCU_48h_default);
+ PRINT(OUT_OBJ " This change at this platform must been proven again by the ASPEED.\n");
+ }
+ } // End if ( AST1010 )
+
+ if ( ModeSwitch == MODE_NSCI ) {
+ PRINT(OUT_OBJ "\n[Arg] %d %d %d %d %d %ld (%s)\n", GRun_Mode, PackageTolNum, ChannelTolNum, TestMode, IOTimingBund, (ARPNumCnt| (ULONG)PrintNCSIEn), ASTChipName);
+
+ switch (NCSI_Cap_SLT.PCI_DID_VID) {
+ case PCI_DID_VID_Intel_82574L : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82574L \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82575_10d6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82575_10a7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82575_10a9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82575 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_10c9 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_10e6 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_10e7 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_10e8 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_1518 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_1526 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_150a : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82576_150d : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82576 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82599_10fb : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_82599_1557 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel 82599 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_I350_1521 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_I350_1523 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I350 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_I210 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel I210 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Intel_X540 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel X540 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Broadcom_BCM5718 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5718 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Broadcom_BCM5720 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5720 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Broadcom_BCM5725 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom BCM5725 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+// case PCI_DID_VID_Broadcom_BCM57810 : PRINT( OUT_OBJ "[NC]%08x %08x: Broadcom BCM57810 \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case PCI_DID_VID_Mellanox_ConnectX_3 : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox ConnectX-3\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ default :
+ switch (NCSI_Cap_SLT.ManufacturerID) {
+ case ManufacturerID_Intel : PRINT( OUT_OBJ "[NC]%08lx %08lx: Intel \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case ManufacturerID_Broadcom : PRINT( OUT_OBJ "[NC]%08lx %08lx: Broadcom\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ case ManufacturerID_Mellanox : PRINT( OUT_OBJ "[NC]%08lx %08lx: Mellanox\n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID ); break;
+ default : PRINT(OUT_OBJ "[NC]%08lx %08lx \n", NCSI_Cap_SLT.ManufacturerID, NCSI_Cap_SLT.PCI_DID_VID); break;
+ } // End switch (NCSI_Cap_SLT.ManufacturerID)
+ } // End switch (NCSI_Cap_SLT.PCI_DID_VID)
+ }
+ else {
+ if (LOOP_INFINI) PRINT(OUT_OBJ "\n[Arg] %d %d %d # %d %d %d %lx (%s)[%d %d %d]\n" , GRun_Mode, GSpeed, GCtrl, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
+ else PRINT(OUT_OBJ "\n[Arg] %d %d %d %ld %d %d %d %lx (%s)[%d %d %d]\n", GRun_Mode, GSpeed, GCtrl, LOOP_MAX_arg, TestMode, PHY_ADR_arg, IOTimingBund, UserDVal, ASTChipName, Loop_rl[0], Loop_rl[1], Loop_rl[2]);
+
+ PRINT(OUT_OBJ "[PHY] Adr:%d ID2:%04lx ID3:%04lx (%s)\n", PHY_ADR, PHY_ID2, PHY_ID3, PHYName);
+ } // End if ( ModeSwitch == MODE_NSCI )
+
+#ifdef SUPPORT_PHY_LAN9303
+ PRINT(OUT_OBJ "[Ver II] %s (for LAN9303 with I2C%d)\n", version_name, LAN9303_I2C_BUSNUM);
+#else
+ PRINT(OUT_OBJ "[Ver II] %s\n", version_name);
+#endif
+} // End void FPri_End (BYTE option)
+
+//------------------------------------------------------------
+void FPri_ErrFlag (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ if (Err_Flag && Err_Flag_PrintEn) {
+ PRINT(OUT_OBJ "\n\n");
+//fprintf(fp, "Err_Flag: %x\n\n", Err_Flag);
+
+ if ( Err_Flag & Err_PHY_Type ) PRINT( OUT_OBJ "[Err] Unidentifiable PHY \n" );
+ if ( Err_Flag & Err_MALLOC_FrmSize ) PRINT( OUT_OBJ "[Err] Malloc fail at frame size buffer \n" );
+ if ( Err_Flag & Err_MALLOC_LastWP ) PRINT( OUT_OBJ "[Err] Malloc fail at last WP buffer \n" );
+ if ( Err_Flag & Err_Check_Buf_Data ) PRINT( OUT_OBJ "[Err] Received data mismatch \n" );
+ if ( Err_Flag & Err_NCSI_Check_TxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Tx owner bit in NCSI packet \n" );
+ if ( Err_Flag & Err_NCSI_Check_RxOwnTimeOut ) PRINT( OUT_OBJ "[Err] Time out of checking Rx owner bit in NCSI packet \n" );
+ if ( Err_Flag & Err_NCSI_Check_ARPOwnTimeOut) PRINT( OUT_OBJ "[Err] Time out of checking ARP owner bit in NCSI packet \n" );
+ if ( Err_Flag & Err_NCSI_No_PHY ) PRINT( OUT_OBJ "[Err] Can not find NCSI PHY \n" );
+ if ( Err_Flag & Err_NCSI_Channel_Num ) PRINT( OUT_OBJ "[Err] NCSI Channel Number Mismatch \n" );
+ if ( Err_Flag & Err_NCSI_Package_Num ) PRINT( OUT_OBJ "[Err] NCSI Package Number Mismatch \n" );
+ if ( Err_Flag & Err_PHY_TimeOut ) PRINT( OUT_OBJ "[Err] Time out of read/write/reset PHY register \n" );
+ if ( Err_Flag & Err_RXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[2]:Receiving buffer unavailable \n" );
+ if ( Err_Flag & Err_RPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[3]:Received packet lost due to RX FIFO full \n" );
+ if ( Err_Flag & Err_NPTXBUF_UNAVA ) PRINT( OUT_OBJ "[Err] MAC00h[6]:Normal priority transmit buffer unavailable \n" );
+ if ( Err_Flag & Err_TPKT_LOST ) PRINT( OUT_OBJ "[Err] MAC00h[7]:Packets transmitted to Ethernet lost \n" );
+ if ( Err_Flag & Err_DMABufNum ) PRINT( OUT_OBJ "[Err] DMA Buffer is not enough \n" );
+ if ( Err_Flag & Err_IOMargin ) PRINT( OUT_OBJ "[Err] IO timing margin is not enough \n" );
+
+ if ( Err_Flag & Err_MHCLK_Ratio ) {
+ if ( AST1010 ) {
+ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[13:12]) \n");
+ Dat_ULONG = (SCU_08h_old >> 12) & 0x3;
+ PRINT(OUT_OBJ " SCU08[13:12] == 0x%01lx is not the suggestion value 0.\n", Dat_ULONG);
+ }
+ else {
+ PRINT(OUT_OBJ "[Err] Error setting of MAC AHB bus clock (SCU08[18:16]) \n");
+ Dat_ULONG = (SCU_08h_old >> 16) & 0x7;
+
+ if (MAC1_1GEn | MAC2_1GEn) {
+ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 2.\n", Dat_ULONG);
+ }
+ else {
+ PRINT(OUT_OBJ " SCU08[18:16] == 0x%01lx is not the suggestion value 4.\n", Dat_ULONG);
+ }
+ } // end if ( AST1010 )
+ } // End if ( Err_Flag & Err_MHCLK_Ratio )
+
+ if (Err_Flag & Err_IOMarginOUF ) {
+ PRINT(OUT_OBJ "[Err] IO timing testing range out of boundary\n");
+ if (Enable_RMII) {
+#ifdef Enable_Old_Style
+ PRINT(OUT_OBJ " (%d,%d): 1x%d [%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOdly_out_reg_idx, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
+#else
+ PRINT(OUT_OBJ " (%d,%d): %dx1 [%d:%d]x[%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx);
+#endif
+ } else {
+#ifdef Enable_Old_Style
+ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_out_reg_idx, IOdly_in_reg_idx, IOTimingBund, IOTimingBund, IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1), IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1));
+#else
+ PRINT(OUT_OBJ " (%d,%d): %dx%d [%d:%d]x[%d:%d]\n", IOdly_in_reg_idx, IOdly_out_reg_idx, IOTimingBund, IOTimingBund, IOdly_in_reg_idx - (IOTimingBund>>1), IOdly_in_reg_idx + (IOTimingBund>>1), IOdly_out_reg_idx - (IOTimingBund>>1), IOdly_out_reg_idx + (IOTimingBund>>1));
+#endif
+ }
+ } // End if (Err_Flag & Err_IOMarginOUF )
+
+ if (Err_Flag & Err_Check_Des ) {
+ PRINT(OUT_OBJ "[Err] Descriptor error\n");
+ if ( Check_Des_Val & Check_Des_TxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Tx owner bit\n" );
+ if ( Check_Des_Val & Check_Des_RxOwnTimeOut ) PRINT( OUT_OBJ "[Des] Time out of checking Rx owner bit\n" );
+ if ( Check_Des_Val & Check_Des_RxErr ) PRINT( OUT_OBJ "[Des] Input signal RxErr \n" );
+ if ( Check_Des_Val & Check_Des_OddNibble ) PRINT( OUT_OBJ "[Des] Nibble bit happen \n" );
+ if ( Check_Des_Val & Check_Des_CRC ) PRINT( OUT_OBJ "[Des] CRC error of frame \n" );
+ if ( Check_Des_Val & Check_Des_RxFIFOFull ) PRINT( OUT_OBJ "[Des] Rx FIFO full \n" );
+ if ( Check_Des_Val & Check_Des_FrameLen ) PRINT( OUT_OBJ "[Des] Frame length mismatch \n" );
+ } // End if (Err_Flag & Err_Check_Des )
+
+ if (Err_Flag & Err_MACMode ) {
+ PRINT(OUT_OBJ "[Err] MAC interface mode mismatch\n");
+ if ( AST1010 ) {
+ }
+ else if (AST2300) {
+ switch (MAC_Mode) {
+ case 0 : PRINT( OUT_OBJ " SCU70h[7:6] == 0: [MAC#1] RMII [MAC#2] RMII \n" ); break;
+ case 1 : PRINT( OUT_OBJ " SCU70h[7:6] == 1: [MAC#1] RGMII [MAC#2] RMII \n" ); break;
+ case 2 : PRINT( OUT_OBJ " SCU70h[7:6] == 2: [MAC#1] RMII [MAC#2] RGMII\n" ); break;
+ case 3 : PRINT( OUT_OBJ " SCU70h[7:6] == 3: [MAC#1] RGMII [MAC#2] RGMII\n" ); break;
+ }
+ }
+ else {
+ switch (MAC_Mode) {
+ case 0 : PRINT( OUT_OBJ " SCU70h[8:6] == 000: [MAC#1] GMII \n" ); break;
+ case 1 : PRINT( OUT_OBJ " SCU70h[8:6] == 001: [MAC#1] MII [MAC#2] MII \n" ); break;
+ case 2 : PRINT( OUT_OBJ " SCU70h[8:6] == 010: [MAC#1] RMII [MAC#2] MII \n" ); break;
+ case 3 : PRINT( OUT_OBJ " SCU70h[8:6] == 011: [MAC#1] MII \n" ); break;
+ case 4 : PRINT( OUT_OBJ " SCU70h[8:6] == 100: [MAC#1] RMII \n" ); break;
+ case 5 : PRINT( OUT_OBJ " SCU70h[8:6] == 101: Reserved \n" ); break;
+ case 6 : PRINT( OUT_OBJ " SCU70h[8:6] == 110: [MAC#1] RMII [MAC#2] RMII\n" ); break;
+ case 7 : PRINT( OUT_OBJ " SCU70h[8:6] == 111: Disable MAC \n" ); break;
+ }
+ } // End if ( AST1010 )
+ } // End if (Err_Flag & Err_MACMode )
+
+ if ( ModeSwitch == MODE_NSCI ) {
+ if (Err_Flag & Err_NCSI_LinkFail ) {
+ PRINT(OUT_OBJ "[Err] NCSI packet retry number over flows when find channel\n");
+
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Version_ID ) PRINT(OUT_OBJ "[NCSI] Time out when Get Version ID \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Get_Capabilities ) PRINT(OUT_OBJ "[NCSI] Time out when Get Capabilities \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Select_Active_Package ) PRINT(OUT_OBJ "[NCSI] Time out when Select Active Package \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Set_MAC_Address ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Set MAC Address \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Broadcast_Filter) PRINT(OUT_OBJ "[NCSI] Time out when Enable Broadcast Filter\n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Network TX \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Enable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Enable Channel \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Network_TX ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Network TX \n");
+ if (NCSI_LinkFail_Val & NCSI_LinkFail_Disable_Channel ) PRINT(OUT_OBJ "[NCSI] Time out when Disable Channel \n");
+ }
+
+ if (Err_Flag & Err_NCSI_Channel_Num ) PRINT(OUT_OBJ "[NCSI] Channel number expected: %d, real: %d\n", ChannelTolNum, number_chl);
+ if (Err_Flag & Err_NCSI_Package_Num ) PRINT(OUT_OBJ "[NCSI] Peckage number expected: %d, real: %d\n", PackageTolNum, number_pak);
+ } // End if ( ModeSwitch == MODE_NSCI )
+ } // End if (Err_Flag && Err_Flag_PrintEn)
+} // End void FPri_ErrFlag (BYTE option)
+
+//------------------------------------------------------------
+void Finish_Close (void) {
+
+ if (SCU_oldvld)
+ recov_scu();
+
+#ifdef SLT_DOS
+ if (fp_io && IOTiming)
+ fclose(fp_io);
+
+ if (fp_log)
+ fclose(fp_log);
+#endif
+} // End void Finish_Close (void)
+
+//------------------------------------------------------------
+char Finish_Check (int value) {
+ ULONG temp;
+ CHAR i = 0;
+
+#ifdef Disable_VGA
+ if (VGAModeVld) {
+ outp(0x3d4, 0x17);
+ outp(0x3d5, VGAMode);
+ }
+#endif
+ #ifdef DbgPrn_FuncHeader
+ printf ("Finish_Check\n");
+ Debug_delay();
+ #endif
+
+ if ( FRAME_LEN )
+ free(FRAME_LEN);
+
+ if ( wp_lst )
+ free(wp_lst );
+
+ Err_Flag = Err_Flag | value;
+
+ if ( DbgPrn_ErrFlg )
+ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
+
+ if ( !BurstEnable )
+ FPri_ErrFlag( FP_LOG );
+
+ if ( IOTiming )
+ FPri_ErrFlag( FP_IO );
+
+ FPri_ErrFlag( STD_OUT );
+
+ if ( !BurstEnable )
+ FPri_End( FP_LOG );
+
+ if ( IOTiming )
+ FPri_End( FP_IO );
+
+ FPri_End( STD_OUT );
+
+
+ if ( !BurstEnable ) FPri_RegValue( FP_LOG );
+ if ( IOTiming ) FPri_RegValue( FP_IO );
+
+ Finish_Close();
+
+ // 20140325
+ temp = ReadSOC_DD( 0x1e6e2040 );
+ if ( ModeSwitch == MODE_NSCI )
+ {
+ if ( SelectMAC == 0 )
+ i = 17;
+ else
+ i = 16;
+ }
+ else
+ {
+ if ( SelectMAC == 0 )
+ i = 19;
+ else
+ i = 18;
+ }
+ WriteSOC_DD( 0x1e6e2040, (temp | (1 << i)) );
+
+
+ if ( Err_Flag )
+ {
+ // Fail
+ return( 1 );
+ }
+ else
+ {
+ // Pass
+ return( 0 );
+ }
+} // End char Finish_Check (int value)
+
+//------------------------------------------------------------
+int FindErr (int value) {
+ Err_Flag = Err_Flag | value;
+
+ if ( DbgPrn_ErrFlg )
+ printf ("\nErr_Flag: [%08lx]\n", Err_Flag);
+
+ return(1);
+}
+
+//------------------------------------------------------------
+int FindErr_Des (int value) {
+ Check_Des_Val = Check_Des_Val | value;
+ Err_Flag = Err_Flag | Err_Check_Des;
+ if ( DbgPrn_ErrFlg )
+ printf ("\nErr_Flag: [%08lx] Check_Des_Val: [%08lx]\n", Err_Flag, Check_Des_Val);
+
+ return(1);
+}
+
+//------------------------------------------------------------
+// Get and Check status of Interrupt
+//------------------------------------------------------------
+int check_int ( char *type ) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("check_int : %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ Dat_ULONG = ReadSOC_DD( H_MAC_BASE + 0x00 );//Interrupt Status
+#ifdef SLT_DOS
+#ifdef CheckRxbufUNAVA
+ if ( Dat_ULONG & 0x00000004 ) {
+ fprintf(fp_log, "[%sIntStatus] Receiving buffer unavailable : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
+ FindErr( Err_RXBUF_UNAVA );
+ }
+#endif
+
+#ifdef CheckRPktLost
+ if ( Dat_ULONG & 0x00000008 ) {
+ fprintf(fp_log, "[%sIntStatus] Received packet lost due to RX FIFO full : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
+ FindErr( Err_RPKT_LOST );
+ }
+#endif
+
+#ifdef CheckNPTxbufUNAVA
+ if ( Dat_ULONG & 0x00000040 ) {
+ fprintf(fp_log, "[%sIntStatus] Normal priority transmit buffer unavailable: %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
+ FindErr( Err_NPTXBUF_UNAVA );
+ }
+#endif
+
+#ifdef CheckTPktLost
+ if ( Dat_ULONG & 0x00000080 ) {
+ fprintf(fp_log, "[%sIntStatus] Packets transmitted to Ethernet lost : %08lx [loop:%d]\n", type, Dat_ULONG, Loop);
+ FindErr( Err_TPKT_LOST );
+ }
+#endif
+#endif
+ if (Err_Flag)
+ return(1);
+ else
+ return(0);
+} // End int check_int (char *type)
+
+
+//------------------------------------------------------------
+// Buffer
+//------------------------------------------------------------
+void setup_framesize (void) {
+ int i;
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("setup_framesize\n");
+ Debug_delay();
+ #endif
+
+ //------------------------------------------------------------
+ // Fill Frame Size out descriptor area
+ //------------------------------------------------------------
+ #ifdef SLT_UBOOT
+ if (0)
+ #else
+ if ( ENABLE_RAND_SIZE )
+ #endif
+ {
+ for (i = 0; i < DES_NUMBER; i++) {
+ if ( FRAME_Rand_Simple ) {
+ switch(rand() % 5) {
+ case 0 : FRAME_LEN[i] = 0x4e ; break;
+ case 1 : FRAME_LEN[i] = 0x4ba; break;
+ default: FRAME_LEN[i] = 0x5ea; break;
+ }
+ }
+ else {
+ FRAME_LEN_Cur = rand() % (MAX_FRAME_RAND_SIZE + 1);
+
+ if (FRAME_LEN_Cur < MIN_FRAME_RAND_SIZE)
+ FRAME_LEN_Cur = MIN_FRAME_RAND_SIZE;
+
+ FRAME_LEN[i] = FRAME_LEN_Cur;
+ }
+#ifdef SLT_DOS
+ if (DbgPrn_FRAME_LEN)
+ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
+#endif
+ }
+ }
+ else {
+ for (i = 0; i < DES_NUMBER; i++) {
+ #ifdef SelectSimpleLength
+ if (i % FRAME_SELH_PERD)
+ FRAME_LEN[i] = FRAME_LENH;
+ else
+ FRAME_LEN[i] = FRAME_LENL;
+ #else
+ if ( BurstEnable ) {
+ if (IEEETesting) {
+ FRAME_LEN[i] = 1514;
+ }
+ else {
+ #ifdef ENABLE_ARP_2_WOL
+ FRAME_LEN[i] = 164;
+ #else
+ FRAME_LEN[i] = 60;
+ #endif
+ }
+ }
+ else {
+ #ifdef SelectLengthInc
+// FRAME_LEN[i] = (i%1455)+60;
+ FRAME_LEN[i] = 1514-( i % 1455 );
+ #else
+ if (i % FRAME_SELH_PERD)
+ FRAME_LEN[i] = FRAME_LENH;
+ else
+ FRAME_LEN[i] = FRAME_LENL;
+ #endif
+ } // End if (BurstEnable)
+ #endif
+/*
+ switch(i % 20) {
+ case 0 : FRAME_LEN[i] = FRAME_LENH; break;
+ case 1 : FRAME_LEN[i] = FRAME_LENH; break;
+ case 2 : FRAME_LEN[i] = FRAME_LENH; break;
+ default: FRAME_LEN[i] = FRAME_LENL; break;
+ }
+*/
+#ifdef SLT_DOS
+ if (DbgPrn_FRAME_LEN)
+ fprintf(fp_log, "[setup_framesize] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN[i], i, Loop);
+#endif
+ } // End for (i = 0; i < DES_NUMBER; i++)
+ } // End if ( ENABLE_RAND_SIZE )
+
+ // Calculate average of frame size
+ Avg_frame_len = 0;
+
+ for ( i = 0; i < DES_NUMBER; i++ ) {
+ Avg_frame_len += FRAME_LEN[i];
+ }
+
+ Avg_frame_len = Avg_frame_len / (double)DES_NUMBER;
+
+ //------------------------------------------------------------
+ // Write Plane
+ //------------------------------------------------------------
+ switch( ZeroCopy_OFFSET & 0x3 ) {
+ case 0: wp_fir = 0xffffffff; break;
+ case 1: wp_fir = 0xffffff00; break;
+ case 2: wp_fir = 0xffff0000; break;
+ case 3: wp_fir = 0xff000000; break;
+ }
+
+ for ( i = 0; i < DES_NUMBER; i++ ) {
+ switch( ( ZeroCopy_OFFSET + FRAME_LEN[i] - 1 ) & 0x3 ) {
+ case 0: wp_lst[i] = 0x000000ff; break;
+ case 1: wp_lst[i] = 0x0000ffff; break;
+ case 2: wp_lst[i] = 0x00ffffff; break;
+ case 3: wp_lst[i] = 0xffffffff; break;
+ }
+ } // End for ( i = 0; i < DES_NUMBER; i++ )
+} // End void setup_framesize (void)
+
+//------------------------------------------------------------
+void setup_arp (void) {
+ int i;
+ for (i = 0; i < 16; i++ )
+ ARP_data[i] = ARP_org_data[i];
+
+ ARP_data[1] = 0x0000ffff | ( SA[0] << 16 )
+ | ( SA[1] << 24 );
+
+ ARP_data[2] = ( SA[2] )
+ | ( SA[3] << 8 )
+ | ( SA[4] << 16 )
+ | ( SA[5] << 24 );
+
+ ARP_data[5] = 0x00000100 | ( SA[0] << 16 )
+ | ( SA[1] << 24 );
+
+ ARP_data[6] = ( SA[2] )
+ | ( SA[3] << 8 )
+ | ( SA[4] << 16 )
+ | ( SA[5] << 24 );
+} // End void setup_arp (void)
+
+//------------------------------------------------------------
+void setup_buf (void) {
+ int i;
+ int j;
+ ULONG adr;
+ ULONG adr_srt;
+ ULONG adr_end;
+ ULONG len;
+ #ifdef SelectSimpleDA
+ int cnt;
+ ULONG Current_framelen;
+ #endif
+
+ #ifdef ENABLE_ARP_2_WOL
+ int DA[3];
+
+ DA[0] = ( ( SelectWOLDA_DatH >> 8 ) & 0x00ff ) |
+ ( ( SelectWOLDA_DatH << 8 ) & 0xff00 );
+
+ DA[1] = ( ( SelectWOLDA_DatL >> 24 ) & 0x00ff ) |
+ ( ( SelectWOLDA_DatL >> 8 ) & 0xff00 );
+
+ DA[2] = ( ( SelectWOLDA_DatL >> 8 ) & 0x00ff ) |
+ ( ( SelectWOLDA_DatL << 8 ) & 0xff00 );
+ #endif
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("setup_buf : %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ // It need be multiple of 4
+ adr_srt = GET_DMA_BASE_SETUP & 0xfffffffc;
+
+ for (j = 0; j < DES_NUMBER; j++) {
+ if ( DbgPrn_BufAdr )
+ printf("[loop:%4d][des:%4d][setup_buf ] %08lx\n", Loop, j, adr_srt);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ #ifdef ENABLE_DASA
+ WriteSOC_DD( adr_srt , 0xffffffff );
+ WriteSOC_DD( adr_srt + 4, ARP_data[1] );
+ WriteSOC_DD( adr_srt + 8, ARP_data[2] );
+
+ for (adr = (adr_srt + 12); adr < (adr_srt + DMA_PakSize); adr += 4 )
+ #else
+ for (adr = adr_srt; adr < (adr_srt + DMA_PakSize); adr += 4 )
+ #endif
+ {
+ switch( TestMode ) {
+ case 1: gdata = 0xffffffff; break;
+ case 2: gdata = 0x55555555; break;
+ case 3: gdata = rand() | (rand() << 16); break;
+ case 5: gdata = UserDVal; break;
+ }
+ WriteSOC_DD(adr, gdata);
+ } // End for()
+ }
+ else {
+ for (i = 0; i < 16; i++) {
+ WriteSOC_DD( adr_srt + ( i << 2 ), ARP_data[i] );
+ }
+
+ #ifdef ENABLE_ARP_2_WOL
+ for (i = 16; i < 40; i += 3) {
+ WriteSOC_DD( adr_srt + ( i << 2 ), ( DA[1] << 16 ) | DA[0] );
+ WriteSOC_DD( adr_srt + ( i << 2 ) + 4, ( DA[0] << 16 ) | DA[2] );
+ WriteSOC_DD( adr_srt + ( i << 2 ) + 8, ( DA[2] << 16 ) | DA[1] );
+ }
+ #endif
+ } // End if ( IEEETesting )
+ }
+ else {
+ // --------------------------------------------
+ #ifdef SelectSimpleData
+ #ifdef SimpleData_Fix
+ switch( j % SimpleData_FixNum ) {
+ case 0 : gdata = SimpleData_FixVal00; break;
+ case 1 : gdata = SimpleData_FixVal01; break;
+ case 2 : gdata = SimpleData_FixVal02; break;
+ case 3 : gdata = SimpleData_FixVal03; break;
+ case 4 : gdata = SimpleData_FixVal04; break;
+ case 5 : gdata = SimpleData_FixVal05; break;
+ case 6 : gdata = SimpleData_FixVal06; break;
+ case 7 : gdata = SimpleData_FixVal07; break;
+ case 8 : gdata = SimpleData_FixVal08; break;
+ case 9 : gdata = SimpleData_FixVal09; break;
+ case 10 : gdata = SimpleData_FixVal10; break;
+ default : gdata = SimpleData_FixVal11; break;
+ }
+ #else
+ gdata = 0x11111111 * ((j + SEED_START) % 256);
+ #endif
+
+ adr_end = adr_srt + DMA_PakSize;
+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
+ WriteSOC_DD( adr, gdata );
+ }
+ // --------------------------------------------
+ #elif SelectSimpleDA
+
+ gdata = DATA_SEED(j + SEED_START);
+ Current_framelen = FRAME_LEN[j];
+
+ if ( DbgPrn_FRAME_LEN )
+ fprintf(fp_log, "[setup_buf ] Current_framelen:%08lx[Des:%d][loop:%d]\n", Current_framelen, j, Loop);
+
+ cnt = 0;
+ len = ( ( ( Current_framelen - 14 ) & 0xff ) << 8) |
+ ( ( Current_framelen - 14 ) >> 8 );
+
+ adr_end = adr_srt + DMA_PakSize;
+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
+ cnt++;
+ if (cnt == 1 ) WriteSOC_DD( adr, SelectSimpleDA_Dat0 );
+ else if (cnt == 2 ) WriteSOC_DD( adr, SelectSimpleDA_Dat1 );
+ else if (cnt == 3 ) WriteSOC_DD( adr, SelectSimpleDA_Dat2 );
+ else if (cnt == 4 ) WriteSOC_DD( adr, len | (len << 16) );
+ else
+ WriteSOC_DD( adr, gdata );
+
+ gdata += DATA_IncVal;
+ }
+ // --------------------------------------------
+ #else
+
+ gdata = DATA_SEED(j + SEED_START);
+ adr_end = adr_srt + DMA_PakSize;
+ for ( adr = adr_srt; adr < adr_end; adr += 4 ) {
+ WriteSOC_DD( adr, gdata );
+
+ gdata += DATA_IncVal;
+ }
+
+ #endif
+
+ } // End if ( BurstEnable )
+
+ adr_srt += DMA_PakSize;
+ } // End for (j = 0; j < DES_NUMBER; j++)
+} // End void setup_buf (void)
+
+//------------------------------------------------------------
+// Check data of one packet
+//------------------------------------------------------------
+char check_Data (ULONG desadr, LONG number) {
+ int index;
+ int cnt;
+ ULONG rdata;
+ ULONG wp_lst_cur;
+ ULONG adr_las;
+ ULONG adr;
+ ULONG adr_srt;
+ ULONG adr_end;
+ ULONG len;
+ #ifdef SelectSimpleDA
+ ULONG gdata_bak;
+ #endif
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("check_Data : %d\n", Loop);
+ Debug_delay();
+ #endif
+ //printf("[Des:%d][loop:%d]Desadr:%08x\n", number, Loop, desadr);
+
+ wp_lst_cur = wp_lst[number];
+ FRAME_LEN_Cur = FRAME_LEN[number];
+#ifdef SLT_DOS
+ if ( DbgPrn_FRAME_LEN )
+ fprintf(fp_log, "[check_Data ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, number, Loop);
+#endif
+ adr_srt = ReadSOC_DD(desadr) & 0xfffffffc;
+ adr_end = adr_srt + PktByteSize;
+
+ #ifdef SelectSimpleData
+ #ifdef SimpleData_Fix
+ switch( number % SimpleData_FixNum ) {
+ case 0 : gdata = SimpleData_FixVal00; break;
+ case 1 : gdata = SimpleData_FixVal01; break;
+ case 2 : gdata = SimpleData_FixVal02; break;
+ case 3 : gdata = SimpleData_FixVal03; break;
+ case 4 : gdata = SimpleData_FixVal04; break;
+ case 5 : gdata = SimpleData_FixVal05; break;
+ case 6 : gdata = SimpleData_FixVal06; break;
+ case 7 : gdata = SimpleData_FixVal07; break;
+ case 8 : gdata = SimpleData_FixVal08; break;
+ case 9 : gdata = SimpleData_FixVal09; break;
+ case 10 : gdata = SimpleData_FixVal10; break;
+ default : gdata = SimpleData_FixVal11; break;
+ }
+ #else
+ gdata = 0x11111111 * ((number + SEED_START) % 256);
+ #endif
+ #else
+ gdata = DATA_SEED(number + SEED_START);
+ #endif
+
+ wp = wp_fir;
+ adr_las = adr_end - 4;
+
+ cnt = 0;
+ len = (((FRAME_LEN_Cur-14) & 0xff) << 8) | ((FRAME_LEN_Cur-14) >> 8);
+#ifdef SLT_DOS
+ if (DbgPrn_Bufdat)
+ fprintf(fp_log, " Inf:%08lx ~ %08lx(%08lx) %08lx [Des:%d][loop:%d]\n", adr_srt, adr_end, adr_las, gdata, number, Loop);
+#endif
+ for (adr = adr_srt; adr < adr_end; adr+=4) {
+
+ #ifdef SelectSimpleDA
+ cnt++;
+ if ( cnt == 1 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat0; }
+ else if ( cnt == 2 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat1; }
+ else if ( cnt == 3 ) { gdata_bak = gdata; gdata = SelectSimpleDA_Dat2; }
+ else if ( cnt == 4 ) { gdata_bak = gdata; gdata = len | (len << 16); }
+ #endif
+ rdata = ReadSOC_DD(adr);
+ if (adr == adr_las)
+ wp = wp & wp_lst_cur;
+
+ if ( (rdata & wp) != (gdata & wp) ) {
+#ifdef SLT_DOS
+ fprintf(fp_log, "\nError: Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
+#endif
+ for (index = 0; index < 6; index++) {
+ rdata = ReadSOC_DD(adr);
+#ifdef SLT_DOS
+ fprintf(fp_log, "Rep : Adr:%08lx (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, rdata, gdata, wp, number, Loop);
+#endif
+ }
+
+ if ( DbgPrn_DumpMACCnt )
+ dump_mac_ROreg();
+
+ return( FindErr( Err_Check_Buf_Data ) );
+ } // End if ( (rdata & wp) != (gdata & wp) )
+#ifdef SLT_DOS
+ if ( DbgPrn_BufdatDetail )
+ fprintf(fp_log, " Adr:%08lx[%3d] (%08lx) (%08lx:%08lx) [Des:%d][loop:%d]\n", adr, (adr - adr_srt) / 4, rdata, gdata, wp, number, Loop);
+#endif
+ #ifdef SelectSimpleDA
+ if ( cnt <= 4 )
+ gdata = gdata_bak;
+ #endif
+
+ #ifdef SelectSimpleData
+ #else
+ gdata += DATA_IncVal;
+ #endif
+
+ wp = 0xffffffff;
+ }
+ return(0);
+} // End char check_Data (ULONG desadr, LONG number)
+
+//------------------------------------------------------------
+char check_buf (int loopcnt) {
+ int count;
+ ULONG desadr;
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("check_buf : %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ for ( count = DES_NUMBER - 1; count >= 0; count-- ) {
+ desadr = H_RDES_BASE + ( 16 * count ) + 12;
+ //printf("%d:%08x\n", count, desadr);
+ if (check_Data(desadr, count)) {
+ check_int ("");
+
+ return(1);
+ }
+ }
+ if ( check_int ("") )
+ return(1);
+
+ return(0);
+} // End char check_buf (int loopcnt)
+
+//------------------------------------------------------------
+// Descriptor
+//------------------------------------------------------------
+void setup_txdes (ULONG desadr, ULONG bufbase) {
+ ULONG bufadr;
+ ULONG desval;
+ int count;
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("setup_txdes: %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ bufadr = bufbase + ZeroCopy_OFFSET;
+
+ if (TxDataEnable) {
+ for (count = 0; count < DES_NUMBER; count++) {
+ FRAME_LEN_Cur = FRAME_LEN[count];
+ desval = TDES_IniVal;
+ #ifdef SLT_DOS
+ if (DbgPrn_FRAME_LEN)
+ fprintf(fp_log, "[setup_txdes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", FRAME_LEN_Cur, count, Loop);
+ #endif
+ if (DbgPrn_BufAdr)
+ printf("[loop:%4d][des:%4d][setup_txdes] %08lx\n", Loop, count, bufadr);
+
+ WriteSOC_DD( desadr + 0x04, 0 );
+ WriteSOC_DD( desadr + 0x08, 0 );
+ WriteSOC_DD( desadr + 0x0C, (bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+ if ( count == ( DES_NUMBER - 1 ) )
+ WriteSOC_DD( desadr , desval | EOR_IniVal);
+ else
+ WriteSOC_DD( desadr , desval );
+
+ bufadr += DMA_PakSize;
+ desadr += 16;
+ }
+ }
+ else {
+ WriteSOC_DD( desadr , 0);
+ }
+} // End void setup_txdes (ULONG desadr, ULONG bufbase)
+
+//------------------------------------------------------------
+void setup_rxdes (ULONG desadr, ULONG bufbase) {
+ ULONG bufadr;
+ ULONG desval;
+ int count;
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("setup_rxdes: %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ bufadr = bufbase+ZeroCopy_OFFSET;
+ desval = RDES_IniVal;
+
+ if ( RxDataEnable ) {
+ for (count = 0; count < DES_NUMBER; count++) {
+ if (DbgPrn_BufAdr)
+ printf("[loop:%4d][des:%4d][setup_rxdes] %08lx\n", Loop, count, bufadr);
+ WriteSOC_DD( desadr + 0x04, 0 );
+ WriteSOC_DD( desadr + 0x08, 0 );
+ WriteSOC_DD( desadr + 0x0C, ( bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+ if ( count == ( DES_NUMBER - 1 ) )
+ WriteSOC_DD( desadr , desval | EOR_IniVal );
+ else
+ WriteSOC_DD( desadr , desval );
+
+ desadr += 16;
+ bufadr += DMA_PakSize;
+ }
+ }
+ else {
+ WriteSOC_DD( desadr , 0x80000000 );
+ } // End if ( RxDataEnable )
+} // End void setup_rxdes (ULONG desadr, ULONG bufbase)
+
+//------------------------------------------------------------
+// First setting TX and RX information
+//------------------------------------------------------------
+void setup_des (ULONG bufnum) {
+
+ if ( DbgPrn_BufAdr ) {
+ printf ("setup_rxdes: %ld\n", bufnum);
+ Debug_delay();
+ }
+
+ setup_txdes( H_TDES_BASE, GET_DMA_BASE_SETUP );
+ setup_rxdes( H_RDES_BASE, GET_DMA_BASE(0) );
+
+} // End void setup_des (ULONG bufnum)
+
+//------------------------------------------------------------
+// Move buffer point of TX and RX descriptor to next DMA buffer
+//------------------------------------------------------------
+void setup_des_loop (ULONG bufnum) {
+ int count;
+ ULONG H_rx_desadr;
+ ULONG H_tx_desadr;
+ ULONG H_tx_bufadr;
+ ULONG H_rx_bufadr;
+
+ if ( DbgPrn_BufAdr ) {
+ printf ("setup_rxdes_loop: %ld\n", bufnum);
+ Debug_delay();
+ }
+
+ if (RxDataEnable) {
+ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
+ H_rx_desadr = H_RDES_BASE;
+//printf (" =====>setup_rxdes_loop: %ld [%lX]\n", bufnum, H_rx_bufadr);
+ for (count = 0; count < DES_NUMBER; count++) {
+ WriteSOC_DD(H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+
+ if (count == (DES_NUMBER - 1)) {
+ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
+ }
+ else {
+ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
+ }
+ H_rx_bufadr += DMA_PakSize;
+ H_rx_desadr += 16;
+ }
+ }
+
+ if (TxDataEnable) {
+ if (RxDataEnable) {
+ H_tx_bufadr = GET_DMA_BASE( bufnum ) + ZeroCopy_OFFSET;
+ }
+ else {
+ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
+ }
+ H_tx_desadr = H_TDES_BASE;
+//printf (" =====>setup_Txdes_loop: %ld [%lX]\n", bufnum, H_tx_bufadr);
+ for (count = 0; count < DES_NUMBER; count++) {
+ FRAME_LEN_Cur = FRAME_LEN[count];
+ WriteSOC_DD( H_tx_desadr + 0x0C, ( H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+ if (count == (DES_NUMBER - 1)) {
+ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
+ }
+ else {
+ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
+ }
+ H_tx_bufadr += DMA_PakSize;
+ H_tx_desadr += 16;
+ }
+ }
+
+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); // Tx Poll
+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); // Rx Poll
+} // End void setup_des_loop (ULONG bufnum)
+
+//------------------------------------------------------------
+char check_des_header_Tx (char *type, ULONG adr, LONG desnum) {
+ int timeout = 0;
+ ULONG dat;
+
+ dat = ReadSOC_DD(adr);
+
+ while ( HWOwnTx(dat) ) {
+ // we will run again, if transfer has not been completed.
+ if ( RxDataEnable && (++timeout > TIME_OUT_Des) ) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sTxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
+ #endif
+ return(FindErr_Des(Check_Des_TxOwnTimeOut));
+ }
+ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
+ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
+
+ #ifdef Delay_ChkTxOwn
+ delay(Delay_ChkTxOwn);
+ #endif
+ dat = ReadSOC_DD(adr);
+ }
+
+ return(0);
+} // End char check_des_header_Tx (char *type, ULONG adr, LONG desnum)
+
+//------------------------------------------------------------
+char check_des_header_Rx (char *type, ULONG adr, LONG desnum) {
+ #ifdef CheckRxOwn
+ int timeout = 0;
+ ULONG dat;
+
+ dat = ReadSOC_DD(adr);
+
+ while ( HWOwnRx( dat ) ) {
+ // we will run again, if transfer has not been completed.
+ if (TxDataEnable && (++timeout > TIME_OUT_Des)) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDesOwn] Address %08lx = %08lx [Des:%d][loop:%d]\n", type, adr, dat, desnum, Loop);
+ #endif
+ return(FindErr_Des(Check_Des_RxOwnTimeOut));
+ }
+
+ WriteSOC_DD(H_MAC_BASE + 0x18, 0x00000000);//Tx Poll
+ WriteSOC_DD(H_MAC_BASE + 0x1c, 0x00000000);//Rx Poll
+
+ #ifdef Delay_ChkRxOwn
+ delay(Delay_ChkRxOwn);
+ #endif
+ dat = ReadSOC_DD(adr);
+ };
+
+ Dat_ULONG = ReadSOC_DD( adr + 12 );
+
+ #ifdef CheckRxLen
+ #ifdef SLT_DOS
+ if ( DbgPrn_FRAME_LEN )
+ fprintf(fp_log, "[%sRxDes ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]\n", type, (FRAME_LEN_Cur + 4), desnum, Loop);
+ #endif
+
+ if ((dat & 0x3fff) != (FRAME_LEN_Cur + 4)) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDes] Error Frame Length %08lx:%08lx %08lx(%4d/%4d) [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, (dat & 0x3fff), (FRAME_LEN_Cur + 4), desnum, Loop);
+ #endif
+ FindErr_Des(Check_Des_FrameLen);
+ }
+ #endif // End CheckRxLen
+
+ #ifdef CheckRxErr
+ if (dat & 0x00040000) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDes] Error RxErr %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
+ #endif
+ FindErr_Des(Check_Des_RxErr);
+ }
+ #endif // End CheckRxErr
+
+ #ifdef CheckOddNibble
+ if (dat & 0x00400000) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDes] Odd Nibble %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
+ #endif
+ FindErr_Des(Check_Des_OddNibble);
+ }
+ #endif // End CheckOddNibble
+
+ #ifdef CheckCRC
+ if (dat & 0x00080000) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDes] Error CRC %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
+ #endif
+ FindErr_Des(Check_Des_CRC);
+ }
+ #endif // End CheckCRC
+
+ #ifdef CheckRxFIFOFull
+ if (dat & 0x00800000) {
+ #ifdef SLT_DOS
+ fprintf(fp_log, "[%sRxDes] Error Rx FIFO Full %08lx:%08lx %08lx [Des:%d][loop:%d]\n", type, adr, dat, Dat_ULONG, desnum, Loop);
+ #endif
+ FindErr_Des(Check_Des_RxFIFOFull);
+ }
+ #endif // End CheckRxFIFOFull
+
+ // if (check_int ("")) {return(1);}
+ #endif // End CheckRxOwn
+
+ if (Err_Flag)
+ return(1);
+ else
+ return(0);
+} // End char check_des_header_Rx (char *type, ULONG adr, LONG desnum)
+
+//------------------------------------------------------------
+char check_des (ULONG bufnum, int checkpoint) {
+ int desnum;
+ ULONG H_rx_desadr;
+ ULONG H_tx_desadr;
+ ULONG H_tx_bufadr;
+ ULONG H_rx_bufadr;
+
+ #ifdef Delay_DesGap
+ ULONG dly_cnt = 0;
+ ULONG dly_max = Delay_CntMaxIncVal;
+ #endif
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("check_des : %d(%d)\n", Loop, checkpoint);
+ Debug_delay();
+ #endif
+
+ // Fire the engine to send and recvice
+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll
+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 );//Rx Poll
+
+ #ifdef SelectSimpleDes
+ #else
+ if ( IEEETesting == 1 ) {
+ // IEEE test mode, there is the same data in every lan packet
+ H_tx_bufadr = GET_DMA_BASE_SETUP;
+ H_rx_bufadr = GET_DMA_BASE(0);
+ }
+ else {
+ H_rx_bufadr = GET_DMA_BASE( bufnum + 1 ) + ZeroCopy_OFFSET;
+
+ if (RxDataEnable) {
+ H_tx_bufadr = GET_DMA_BASE(bufnum ) + ZeroCopy_OFFSET;
+ }
+ else {
+ H_tx_bufadr = GET_DMA_BASE( 0 ) + ZeroCopy_OFFSET;
+ }
+ }
+ #endif
+
+ H_rx_desadr = H_RDES_BASE;
+ H_tx_desadr = H_TDES_BASE;
+
+ #ifdef Delay_DES
+ delay(Delay_DES);
+ #endif
+
+ for (desnum = 0; desnum < DES_NUMBER; desnum++) {
+ if ( DbgPrn_BufAdr )
+ printf( "[loop:%4d][des:%4d][check_des ] %08lx %08lx [%08lx] [%08lx]\n", Loop, desnum, ( H_tx_desadr ), ( H_rx_desadr ), ReadSOC_DD( H_tx_desadr + 12 ), ReadSOC_DD( H_rx_desadr + 12 ) );
+
+ //[Delay]--------------------
+ #ifdef Delay_DesGap
+ if ( dly_cnt++ > 3 ) {
+ switch ( rand() % 12 ) {
+ case 1 : dly_max = 00000; break;
+ case 3 : dly_max = 20000; break;
+ case 5 : dly_max = 40000; break;
+ case 7 : dly_max = 60000; break;
+ defaule: dly_max = 70000; break;
+ }
+
+ dly_max += ( rand() % 4 ) * 14321;
+
+ while (dly_cnt < dly_max) {
+ dly_cnt++;
+ }
+
+ dly_cnt = 0;
+ }
+ else {
+// timeout = 0;
+// while (timeout < 50000) {timeout++;};
+ }
+ #endif // End Delay_DesGap
+
+ //[Check Owner Bit]--------------------
+ FRAME_LEN_Cur = FRAME_LEN[desnum];
+#ifdef SLT_DOS
+ if ( DbgPrn_FRAME_LEN )
+ fprintf(fp_log, "[check_des ] FRAME_LEN_Cur:%08lx[Des:%d][loop:%d]%d\n", FRAME_LEN_Cur, desnum, Loop, checkpoint);
+#endif
+// if (BurstEnable) {
+// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
+// } else {
+// if (check_des_header_Rx("", H_rx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
+// if (check_des_header_Tx("", H_tx_desadr, desnum)) {CheckDesFail_DesNum = desnum; return(1);}
+// }
+
+ // Check the description of Tx and Rx
+ if ( RxDataEnable && check_des_header_Rx("", H_rx_desadr, desnum) ) {
+ CheckDesFail_DesNum = desnum;
+
+ return(1);
+ }
+ if ( TxDataEnable && check_des_header_Tx("", H_tx_desadr, desnum) ) {
+ CheckDesFail_DesNum = desnum;
+
+ return(1);
+ }
+// else {
+// printf(" %d \r", desnum);
+// }
+
+ #ifdef SelectSimpleDes
+ #else
+ if ( !checkpoint ) {
+ // Setting buffer address to description of Tx and Rx on next stage
+
+// if (!BurstEnable) {
+// WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
+// WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) );
+// }
+//
+// if ( desnum == (DES_NUMBER - 1) ) {
+// WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
+// WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
+// }
+// else {
+// WriteSOC_DD( H_rx_desadr, RDES_IniVal );
+// WriteSOC_DD( H_tx_desadr, TDES_IniVal );
+// }
+// WriteSOC_DD( H_MAC_BASE+0x18, 0x00000000 ); //Tx Poll
+// WriteSOC_DD( H_MAC_BASE+0x1c, 0x00000000 ); //Rx Poll
+
+ if ( RxDataEnable ) {
+ WriteSOC_DD( H_rx_desadr + 0x0C, (H_rx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+
+ if ( desnum == (DES_NUMBER - 1) ) {
+ WriteSOC_DD( H_rx_desadr, RDES_IniVal | EOR_IniVal );
+ } else {
+ WriteSOC_DD( H_rx_desadr, RDES_IniVal );
+ }
+ }
+ if ( TxDataEnable ) {
+ WriteSOC_DD( H_tx_desadr + 0x0C, (H_tx_bufadr + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730
+ if ( desnum == (DES_NUMBER - 1) ) {
+ WriteSOC_DD( H_tx_desadr, TDES_IniVal | EOR_IniVal );
+ }
+ else {
+ WriteSOC_DD( H_tx_desadr, TDES_IniVal );
+ }
+ }
+ WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 ); //Tx Poll
+ WriteSOC_DD( H_MAC_BASE + 0x1c, 0x00000000 ); //Rx Poll
+ }
+ H_rx_bufadr += DMA_PakSize;
+ H_tx_bufadr += DMA_PakSize;
+ #endif // End SelectSimpleDes
+
+ H_rx_desadr += 16;
+ H_tx_desadr += 16;
+ } // End for (desnum = 0; desnum < DES_NUMBER; desnum++)
+
+ return(0);
+} // End char check_des (ULONG bufnum, int checkpoint)
+//#endif
+
+//------------------------------------------------------------
+// Print
+//------------------------------------------------------------
+void PrintMode (void) {
+ if (Enable_MAC34) printf ("run_mode[dec] | 0->MAC1 1->MAC2 2->MAC3 3->MAC4\n");
+ else printf ("run_mode[dec] | 0->MAC1 1->MAC2\n");
+}
+
+//------------------------------------------------------------
+void PrintSpeed (void) {
+ printf ("speed[dec] | 0->1G 1->100M 2->10M 3->all speed (default:%3d)\n", DEF_SPEED);
+}
+
+//------------------------------------------------------------
+void PrintCtrl (void) {
+ printf ("ctrl[dec] | bit0~2: Reserved\n");
+ printf ("(default:%3d) | bit3 : 1->Enable PHY init 0->Disable PHY init\n", GCtrl);
+ printf (" | bit4 : 1->Enable PHY int-loop 0->Disable PHY int-loop\n");
+ printf (" | bit5 : 1->Ignore PHY ID 0->Check PHY ID\n");
+ if (AST2400) {
+ printf (" | bit6 : 1->Enable MAC int-loop 0->Disable MAC int-loop\n");
+ }
+}
+
+//------------------------------------------------------------
+void PrintLoop (void) {
+ printf ("loop_max[dec] | 1G : 20 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 20);
+ printf (" | 100M: 2 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX * 2);
+ printf (" | 10M : 1 will run 1 sec (default:%3d)\n", DEF_LOOP_MAX);
+}
+
+//------------------------------------------------------------
+void PrintTest (void) {
+ if ( ModeSwitch == MODE_NSCI ) {
+ printf ("test_mode[dec] | 0: NCSI configuration with Disable_Channel request\n");
+ printf ("(default:%3d) | 1: NCSI configuration without Disable_Channel request\n", DEF_TESTMODE);
+ }
+ else {
+ printf ("test_mode[dec] | 0: Tx/Rx frame checking\n");
+ printf ("(default:%3d) | 1: Tx output 0xff frame\n", DEF_TESTMODE);
+ printf (" | 2: Tx output 0x55 frame\n");
+ printf (" | 3: Tx output random frame\n");
+ printf (" | 4: Tx output ARP frame\n");
+ printf (" | 5: Tx output user defined value frame (default:0x%8x)\n", DEF_USER_DEF_PACKET_VAL);
+ } // End if ( ModeSwitch == MODE_NSCI )
+
+ if (AST2300) {
+ printf (" | 6: IO timing testing\n");
+ printf (" | 7: IO timing/strength testing\n");
+ }
+}
+
+//------------------------------------------------------------
+void PrintPHYAdr (void) {
+ printf ("phy_adr[dec] | 0~31: PHY Address (default:%d)\n", DEF_PHY_ADR);
+}
+
+//------------------------------------------------------------
+void PrintIOTimingBund (void) {
+ printf ("IO margin[dec] | 0/1/3/5 (default:%d)\n", DEF_IOTIMINGBUND);
+}
+
+//------------------------------------------------------------
+void PrintPakNUm (void) {
+ printf ("package_num[dec] | 1~ 8: Total Number of NCSI Package (default:%d)\n", DEF_PACKAGE2NUM);
+}
+
+//------------------------------------------------------------
+void PrintChlNUm (void) {
+ printf ("channel_num[dec] | 1~32: Total Number of NCSI Channel (default:%d)\n", DEF_CHANNEL2NUM);
+}
+
+//------------------------------------------------------------
+
+void Print_Header (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ if (GSpeed_sel[0]) PRINT(OUT_OBJ " 1G ");
+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ " 100M ");
+ else PRINT(OUT_OBJ " 10M ");
+
+ switch (TestMode) {
+ case 0 : PRINT(OUT_OBJ "Tx/Rx frame checking \n" ); break;
+ case 1 : PRINT(OUT_OBJ "Tx output 0xff frame \n" ); break;
+ case 2 : PRINT(OUT_OBJ "Tx output 0x55 frame \n" ); break;
+ case 3 : PRINT(OUT_OBJ "Tx output random frame \n" ); break;
+ case 4 : PRINT(OUT_OBJ "Tx output ARP frame \n" ); break;
+ case 5 : PRINT(OUT_OBJ "Tx output 0x%08lx frame \n", UserDVal); break;
+ case 6 : PRINT(OUT_OBJ "IO delay testing \n" ); break;
+ case 7 : PRINT(OUT_OBJ "IO delay testing(Strength) \n" ); break;
+ case 8 : PRINT(OUT_OBJ "Tx frame \n" ); break;
+ case 9 : PRINT(OUT_OBJ "Rx frame checking \n" ); break;
+ }
+}
+
+//------------------------------------------------------------
+void PrintIO_Header (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ if ( IOStrength ) {
+ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[Strength %ld][1G ]========================================\n", IOStr_i);
+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[Strength %ld][100M]========================================\n", IOStr_i);
+ else PRINT(OUT_OBJ "[Strength %ld][10M ]========================================\n", IOStr_i);
+ } else {
+ if (GSpeed_sel[0]) PRINT(OUT_OBJ "[1G ]========================================\n");
+ else if (GSpeed_sel[1]) PRINT(OUT_OBJ "[100M]========================================\n");
+ else PRINT(OUT_OBJ "[10M ]========================================\n");
+ }
+
+#ifdef Enable_Old_Style
+ if (Enable_RMII) PRINT(OUT_OBJ "Tx:SCU48[ %2d]= ", IOdly_out_shf);
+ else PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]= ", IOdly_out_shf+3, IOdly_out_shf);
+
+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
+ IOdly_out = valary[IOdly_j];
+ PRINT(OUT_OBJ "%2x", IOdly_out);
+ }
+
+ PRINT(OUT_OBJ "\n ");
+ for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) {
+ if (IOdly_out_reg_idx == IOdly_j) PRINT(OUT_OBJ " |");
+ else PRINT(OUT_OBJ " ");
+ }
+#else
+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]= ", IOdly_in_shf+3, IOdly_in_shf);
+
+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
+ IOdly_in = valary[IOdly_i];
+ PRINT(OUT_OBJ "%2x", IOdly_in);
+ }
+
+ PRINT(OUT_OBJ "\n ");
+ for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) {
+ if (IOdly_in_reg_idx == IOdly_i) PRINT(OUT_OBJ " |");
+ else PRINT(OUT_OBJ " ");
+ }
+#endif
+
+ PRINT(OUT_OBJ "\n");
+} // End void PrintIO_Header (BYTE option)
+
+//------------------------------------------------------------
+void PrintIO_LineS (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+
+#ifdef Enable_Old_Style
+ if (IOdly_in_reg == IOdly_in) {
+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x:-", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
+ }
+ else {
+ PRINT(OUT_OBJ "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
+ }
+#else
+ if (Enable_RMII) {
+ if (IOdly_out_reg == IOdly_out) {
+ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x:-", IOdly_out_shf, IOdly_out);
+ }
+ else {
+ PRINT(OUT_OBJ "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
+ }
+ } else {
+ if (IOdly_out_reg == IOdly_out) {
+ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x:-", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
+ }
+ else {
+ PRINT(OUT_OBJ "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
+ }
+ }
+#endif
+} // void PrintIO_LineS (BYTE option)
+
+//------------------------------------------------------------
+void PrintIO_Line (BYTE option) {
+
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) {
+ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " X");
+ else PRINT(OUT_OBJ " O");
+ }
+ else {
+ if (dlymap[IOdly_i][IOdly_j]) PRINT(OUT_OBJ " x");
+ else PRINT(OUT_OBJ " o");
+ }
+} // End void PrintIO_Line (BYTE option)
+
+//------------------------------------------------------------
+void PrintIO_Line_LOG (void) {
+#ifndef SLT_UBOOT
+#ifdef Enable_Old_Style
+ if (Enable_RMII) fprintf(fp_log, "\nTx:SCU48[ %2d]=%2x, ", IOdly_out_shf, IOdly_out);
+ else fprintf(fp_log, "\nTx:SCU48[%2d:%2d]=%2x, ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
+
+ fprintf(fp_log, "Rx:SCU48[%2d:%2d]=%01x: ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
+
+ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
+ else fprintf(fp_log, " O\n");
+#else
+ fprintf(fp_log, "\nRx:SCU48[%2d:%2d]=%2x, ", IOdly_in_shf+3, IOdly_in_shf, IOdly_in);
+
+ if (Enable_RMII) fprintf(fp_log, "Tx:SCU48[ %2d]=%01x: ", IOdly_out_shf, IOdly_out);
+ else fprintf(fp_log, "Tx:SCU48[%2d:%2d]=%01x: ", IOdly_out_shf+3, IOdly_out_shf, IOdly_out);
+
+ if (dlymap[IOdly_i][IOdly_j]) fprintf(fp_log, " X\n");
+ else fprintf(fp_log, " O\n");
+#endif
+#endif
+}
+
+//------------------------------------------------------------
+// main
+//------------------------------------------------------------
+void Calculate_LOOP_CheckNum (void) {
+
+#define ONE_MBYTE 1048576
+
+ #ifdef CheckDataEveryTime
+ LOOP_CheckNum = 1;
+ #else
+ if (IOTiming || IOTimingBund || (GSpeed == SET_1G_100M_10MBPS)) {
+ LOOP_CheckNum = LOOP_MAX;
+ }
+ else {
+ switch ( GSpeed ) {
+ case SET_1GBPS : CheckBuf_MBSize = MOVE_DATA_MB_SEC ; break; // 1G
+ case SET_100MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 3); break; // 100M ~ 1G / 8
+ case SET_10MBPS : CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 6); break; // 10M ~ 1G / 64
+ }
+ LOOP_CheckNum = ( CheckBuf_MBSize / ( ((DES_NUMBER * DMA_PakSize) / ONE_MBYTE ) + 1) );
+ }
+ #endif
+}
+
+//------------------------------------------------------------
+void TestingSetup (void) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("TestingSetup\n");
+ Debug_delay();
+ #endif
+
+ #ifdef SLT_UBOOT
+ #else
+ #ifdef Rand_Sed
+ srand((unsigned) Rand_Sed);
+ #else
+ srand((unsigned) timestart);
+ #endif
+ #endif
+
+ //[Disable VGA]--------------------
+ #ifdef Disable_VGA
+ if ( LOOP_INFINI & ~(BurstEnable || IOTiming) ) {
+ VGAModeVld = 1;
+ outp(0x3d4, 0x17);
+ VGAMode = inp(0x3d5);
+ outp(0x3d4, 0x17);
+ outp(0x3d5, 0);
+ }
+ #endif
+
+ //[Setup]--------------------
+ setup_framesize();
+ setup_buf();
+}
+
+//------------------------------------------------------------
+// Return 1 ==> fail
+// Return 0 ==> PASS
+//------------------------------------------------------------
+char TestingLoop (ULONG loop_checknum) {
+ char checkprd;
+ char looplast;
+ char checken;
+
+ #ifdef SLT_UBOOT
+ #else
+ clock_t timeold;
+ #endif
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("TestingLoop: %d\n", Loop);
+ Debug_delay();
+ #endif
+
+ if ( DbgPrn_DumpMACCnt )
+ dump_mac_ROreg();
+
+ //[Setup]--------------------
+ Loop = 0;
+ checkprd = 0;
+ checken = 0;
+ looplast = 0;
+
+ setup_des( 0 );
+
+ #ifdef SLT_UBOOT
+ #else
+ timeold = clock();
+ #endif
+
+ while ( (Loop < LOOP_MAX) || LOOP_INFINI ) {
+ looplast = !LOOP_INFINI && (Loop == LOOP_MAX - 1);
+
+ #ifdef CheckRxBuf
+ if (!BurstEnable) {
+ checkprd = ((Loop % loop_checknum) == (loop_checknum - 1));
+ }
+ checken = looplast | checkprd;
+ #endif
+
+ if ( DataDelay & ( Loop == 0 ) ) {
+ printf ("Press any key to start...\n");
+ GET_CAHR();
+ }
+
+#ifdef DbgPrn_FuncHeader
+ if ( DbgPrn_BufAdr ) {
+ printf ("for start ======> %d/%d(%d) looplast:%d checkprd:%d checken:%d\n", Loop, LOOP_MAX, LOOP_INFINI, looplast, checkprd, checken);
+ Debug_delay();
+ }
+#endif
+
+ //[Check DES]--------------------
+ if ( check_des(Loop, checken) ) {
+ //descriptor error
+ #ifdef CheckRxBuf
+ DES_NUMBER = CheckDesFail_DesNum + 1;
+ if ( checkprd ) {
+ check_buf(loop_checknum);
+ }
+ else {
+ check_buf((LOOP_MAX % loop_checknum));
+ }
+ DES_NUMBER = DES_NUMBER_Org;
+ #endif
+
+ if (DbgPrn_DumpMACCnt)
+ dump_mac_ROreg();
+
+ return(1);
+ }
+
+ //[Check Buf]--------------------
+ if ( RxDataEnable && checken ) {
+ #ifdef SLT_UBOOT
+ #else
+ timeused = (clock() - timeold) / (double) CLK_TCK;
+ #endif
+
+ if ( checkprd ) {
+ #ifdef SLT_DOS
+ #else
+ #ifdef SLT_UBOOT
+ #else
+ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
+ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", loop_checknum, ((double)loop_checknum * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
+ #endif
+ #endif
+
+ #ifdef CheckRxBuf
+ if ( check_buf( loop_checknum ) )
+ return(1);
+ #endif
+ }
+ else {
+ #ifdef SLT_DOS
+ #else
+ #ifdef SLT_UBOOT
+ #else
+ printf("[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
+ fprintf(fp_log, "[run loop:%3d] BandWidth: %7.2f Mbps, %6.2f sec\n", (LOOP_MAX % loop_checknum), ((double)(LOOP_MAX % loop_checknum) * (double)DES_NUMBER * Avg_frame_len * 8.0) / ((double)timeused * 1000000.0), timeused);
+ #endif
+ #endif
+
+ #ifdef CheckRxBuf
+ if ( check_buf( ( LOOP_MAX % loop_checknum ) ) )
+ return(1);
+ #endif
+ } // End if ( checkprd )
+
+ #ifdef SelectSimpleDes
+ #else
+ if ( !looplast )
+ setup_des_loop( Loop );
+ #endif
+
+ #ifdef SLT_DOS
+ #else
+ #ifdef SLT_UBOOT
+ #else
+ timeold = clock();
+ #endif
+ #endif
+
+ } // End if ( RxDataEnable && checken )
+
+ #ifdef SelectSimpleDes
+ if ( !looplast )
+ setup_des_loop( Loop );
+ #endif
+
+ if ( LOOP_INFINI ) {
+ printf("===============> Loop: %d \r", Loop);
+ }
+ else if (TestMode == 0) {
+ if (!(DbgPrn_BufAdr || IOTimingBund))
+ printf(" %d \r", Loop);
+// switch (Loop % 4) {
+// case 0x00: printf("| %d \r", Loop); break;
+// case 0x01: printf("/ %d \r", Loop); break;
+// case 0x02: printf("- %d \r", Loop); break;
+// default : printf("\ %d \r", Loop); break;
+// }
+ }
+
+ if ( DbgPrn_BufAdr ) {
+ printf ("for end ======> %d/%d(%d)\n", Loop, LOOP_MAX, LOOP_INFINI);
+ Debug_delay();
+ }
+
+ Loop++;
+ } // End while ((Loop < LOOP_MAX) || LOOP_INFINI)
+
+ Loop_rl[GSpeed_idx] = Loop;
+
+ return(0);
+} // End char TestingLoop (ULONG loop_checknum)
diff --git a/arch/arm/cpu/arm926ejs/aspeed/Makefile b/arch/arm/cpu/arm926ejs/aspeed/Makefile new file mode 100644 index 0000000..4c4e239 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/Makefile @@ -0,0 +1,53 @@ +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = timer.o +COBJS += reset.o +COBJS += mactest.o +COBJS += DRAM_SPI.o +COBJS += IO.o +COBJS += LIB.o +COBJS += MAC.o +COBJS += NCSI.o +COBJS += PCI_SPI.o +COBJS += PHY.o +COBJS += SPIM.o +COBJS += STDUBOOT.o +COBJS += PLLTESTU.o +COBJS += TRAPTEST.o +COBJS += STRESS.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.H b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H new file mode 100644 index 0000000..a0e448b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.H @@ -0,0 +1,189 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef NCSI_H +#define NCSI_H + +#include "TYPEDEF.H" + +//--------------------------------------------------------- +// Define +//--------------------------------------------------------- +#define MAX_PACKAGE_NUM 8 // 1 ~ 8 +#define MAX_CHANNEL_NUM 4 // 1 ~ 32 +//#define Enable_NCSI_LOOP_INFINI //[off] + +//--------------------------------------------------------- +// Function +//--------------------------------------------------------- +#define SENT_RETRY_COUNT 1 +#define NCSI_RxDESNum 50 + +//#define NCSI_Skip_Phase1_DeSelectPackage +//#define NCSI_Skip_DeSelectPackage +//#define NCSI_Skip_DiSChannel +//#define NCSI_EnableDelay_DeSelectPackage +//#define NCSI_EnableDelay_GetLinkStatus +//#define NCSI_EnableDelay_EachPackage +//#define Print_Version_ID +//#define Print_PackageName + +//--------------------------------------------------------- +// PCI DID/VID & Manufacturer ID +//--------------------------------------------------------- +#define ManufacturerID_Intel 0x00000157 //343 +#define ManufacturerID_Broadcom 0x0000113d //4413 +#define ManufacturerID_Mellanox 0x000002c9 //713 + +//PCI VID: [163c]intel +//PCI VID: [8086]Intel Corporation +//PCI VID: [8087]Intel +//PCI VID: [14e4]Broadcom Corporation +//PCI VID: [15b3]Mellanox +#define PCI_DID_VID_Intel_82574L 0x10d38086 // IntelR 82574L Gigabit Ethernet Controller +#define PCI_DID_VID_Intel_82575_10d6 0x10d68086 // 82566 DM-2-gigabyte +#define PCI_DID_VID_Intel_82575_10a7 0x10a78086 // 82575EB Gigabit Network Connection +#define PCI_DID_VID_Intel_82575_10a9 0x10a98086 // 82575EB Gigabit Network Connection +#define PCI_DID_VID_Intel_82576_10c9 0x10c98086 //*82576 Gigabit ET Dual Port Server Adapter +#define PCI_DID_VID_Intel_82576_10e6 0x10e68086 // 82576 Gigabit Network Connection +#define PCI_DID_VID_Intel_82576_10e7 0x10e78086 // 82576 Gigabit Network Connection +#define PCI_DID_VID_Intel_82576_10e8 0x10e88086 // E64750-xxx Intel Gigabit ET Quad Port Server Adapter +#define PCI_DID_VID_Intel_82576_1518 0x15188086 // 82576NS SerDes Gigabit Network Connectio +#define PCI_DID_VID_Intel_82576_1526 0x15268086 // Intel Gigabit ET2 Quad Port Server Adapter +#define PCI_DID_VID_Intel_82576_150a 0x150a8086 // 82576NS Gigabit Ethernet Controller +#define PCI_DID_VID_Intel_82576_150d 0x150d8086 // 82576 Gigabit Backplane Connection +#define PCI_DID_VID_Intel_82599_10fb 0x10fb8086 // 10 Gb Ethernet controller +#define PCI_DID_VID_Intel_82599_1557 0x15578086 // +#define PCI_DID_VID_Intel_I350_1521 0x15218086 // +#define PCI_DID_VID_Intel_I350_1523 0x15238086 // +#define PCI_DID_VID_Intel_I210 0x15338086 // +#define PCI_DID_VID_Intel_X540 0x15288086 // +#define PCI_DID_VID_Broadcom_BCM5718 0x165614e4 // +#define PCI_DID_VID_Broadcom_BCM5720 0x165f14e4 // +#define PCI_DID_VID_Broadcom_BCM5725 0x164314e4 // +#define PCI_DID_VID_Mellanox_ConnectX_3 0x100315b3 //* + +//--------------------------------------------------------- +// Delay (ms) +//--------------------------------------------------------- +#define Delay_EachPackage 1000 +#define Delay_DeSelectPackage 50 +#define Delay_GetLinkStatus 50 + +//--------------------------------------------------------- +// NCSI Parameter +//--------------------------------------------------------- +//Command and Response Type +#define CLEAR_INITIAL_STATE 0x00 //M +#define SELECT_PACKAGE 0x01 //M +#define DESELECT_PACKAGE 0x02 //M +#define ENABLE_CHANNEL 0x03 //M +#define DISABLE_CHANNEL 0x04 //M +#define RESET_CHANNEL 0x05 //M +#define ENABLE_CHANNEL_NETWORK_TX 0x06 //M +#define DISABLE_CHANNEL_NETWORK_TX 0x07 //M +#define AEN_ENABLE 0x08 +#define SET_LINK 0x09 //M +#define GET_LINK_STATUS 0x0A //M +#define SET_VLAN_FILTER 0x0B //M +#define ENABLE_VLAN 0x0C //M +#define DISABLE_VLAN 0x0D //M +#define SET_MAC_ADDRESS 0x0E //M +#define ENABLE_BROADCAST_FILTERING 0x10 //M +#define DISABLE_BROADCAST_FILTERING 0x11 //M +#define ENABLE_GLOBAL_MULTICAST_FILTERING 0x12 +#define DISABLE_GLOBAL_MULTICAST_FILTERING 0x13 +#define SET_NCSI_FLOW_CONTROL 0x14 +#define GET_VERSION_ID 0x15 //M +#define GET_CAPABILITIES 0x16 //M +#define GET_PARAMETERS 0x17 //M +#define GET_CONTROLLER_PACKET_STATISTICS 0x18 +#define GET_NCSI_STATISTICS 0x19 +#define GET_NCSI_PASS_THROUGH_STATISTICS 0x1A + +//Standard Response Code +#define COMMAND_COMPLETED 0x00 +#define COMMAND_FAILED 0x01 +#define COMMAND_UNAVAILABLE 0x02 +#define COMMAND_UNSUPPORTED 0x03 + +//Standard Reason Code +#define NO_ERROR 0x0000 +#define INTERFACE_INITIALIZATION_REQUIRED 0x0001 +#define PARAMETER_IS_INVALID 0x0002 +#define CHANNEL_NOT_READY 0x0003 +#define PACKAGE_NOT_READY 0x0004 +#define INVALID_PAYLOAD_LENGTH 0x0005 +#define UNKNOWN_COMMAND_TYPE 0x7FFF + +//SET_MAC_ADDRESS +#define UNICAST ( 0x00 << 5 ) +#define MULTICAST ( 0x01 << 5 ) +#define DISABLE_MAC_ADDRESS_FILTER 0x00 +#define ENABLE_MAC_ADDRESS_FILTER 0x01 + +//GET_LINK_STATUS +#define LINK_DOWN 0 +#define LINK_UP 1 + +#define NCSI_RxDMA_PakSize 2048 +#define NCSI_RxDMA_BASE (DMA_BASE+0x00100000) + +//--------------------------------------------------------- +// Variable +//--------------------------------------------------------- +//NC-SI Command Packet +typedef struct { +//Ethernet Header + unsigned char DA[6]; // Destination Address + unsigned char SA[6]; // Source Address + unsigned short EtherType; // DMTF NC-SI, it should be 0x88F8 +//NC-SI Control Packet + unsigned char MC_ID; // Management Controller should set this field to 0x00 + unsigned char Header_Revision; // For NC-SI 1.0 spec, this field has to set 0x01 + unsigned char Reserved_1; // Reserved has to set to 0x00 + unsigned char IID; // Instance ID + unsigned char Command; + unsigned char Channel_ID; + unsigned short Payload_Length; // Payload Length = 12 bits, 4 bits are reserved + unsigned long Reserved_2; + unsigned long Reserved_3; + + unsigned short Reserved_4; + unsigned short Reserved_5; + unsigned short Response_Code; + unsigned short Reason_Code; + unsigned char Payload_Data[64]; +} NCSI_Command_Packet; + +//NC-SI Response Packet +typedef struct { + unsigned char DA[6]; + unsigned char SA[6]; + unsigned short EtherType; //DMTF NC-SI +//NC-SI Control Packet + unsigned char MC_ID; //Management Controller should set this field to 0x00 + unsigned char Header_Revision; //For NC-SI 1.0 spec, this field has to set 0x01 + unsigned char Reserved_1; //Reserved has to set to 0x00 + unsigned char IID; //Instance ID + unsigned char Command; + unsigned char Channel_ID; + unsigned short Payload_Length; //Payload Length = 12 bits, 4 bits are reserved + unsigned short Reserved_2; + unsigned short Reserved_3; + unsigned short Reserved_4; + unsigned short Reserved_5; + + unsigned short Response_Code; + unsigned short Reason_Code; + unsigned char Payload_Data[64]; +} NCSI_Response_Packet; + +#endif // NCSI_H diff --git a/arch/arm/cpu/arm926ejs/aspeed/NCSI.c b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c new file mode 100644 index 0000000..7e86fb6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/NCSI.c @@ -0,0 +1,934 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define NCSI_C +static const char ThisFile[] = "NCSI.c"; + +#include "SWFUNC.H" + +#ifdef SLT_UBOOT + #include <common.h> + #include <command.h> + #include "COMMINF.H" + #include "NCSI.H" + #include "IO.H" +#endif +#ifdef SLT_DOS + #include <stdio.h> + #include <stdlib.h> + #include <conio.h> + #include <string.h> + #include "COMMINF.H" + #include "NCSI.H" + #include "IO.H" +#endif + +NCSI_Command_Packet NCSI_Request_SLT; +NCSI_Response_Packet NCSI_Respond_SLT; +int InstanceID; +int NCSI_RxTimeOutScale; +ULONG NCSI_RxDesBase; +ULONG NCSI_TxDWBUF[512]; +ULONG NCSI_RxDWBUF[512]; +char NCSI_CommandStr[512]; +unsigned char *NCSI_TxByteBUF; +unsigned char *NCSI_RxByteBUF; +unsigned char NCSI_Payload_Data[16]; +unsigned long Payload_Checksum_NCSI = 0x00000000; +ULONG select_flag[MAX_PACKAGE_NUM]; + +ULONG DWSwap_SLT (ULONG in) { + return( ((in & 0xff000000) >> 24) + | ((in & 0x00ff0000) >> 8) + | ((in & 0x0000ff00) << 8) + | ((in & 0x000000ff) << 24) + ); +} +USHORT WDSwap_SLT (USHORT in) { + return( ((in & 0xff00) >> 8) + | ((in & 0x00ff) << 8) + ); +} + +//------------------------------------------------------------ +int FindErr_NCSI (int value) { + NCSI_LinkFail_Val = NCSI_LinkFail_Val | value; + Err_Flag = Err_Flag | Err_NCSI_LinkFail; + if ( DbgPrn_ErrFlg ) + printf ("\nErr_Flag: [%08lx] NCSI_LinkFail_Val: [%08lx]\n", Err_Flag, NCSI_LinkFail_Val); + + return(1); +} + +//------------------------------------------------------------ +// PHY IC(NC-SI) +//------------------------------------------------------------ +void ncsi_respdump ( NCSI_Response_Packet *in ) { + printf ("DA : %02x %02x %02x %02x %02x %02x\n", in->DA[5], in->DA[4], in->DA[3], in->DA[2], in->DA[1], in->DA[0]); + printf ("SA : %02x %02x %02x %02x %02x %02x\n", in->SA[5], in->SA[4], in->SA[3], in->SA[2], in->SA[1], in->SA[0]); + printf ("EtherType : %04x\n", in->EtherType );//DMTF NC-SI + printf ("MC_ID : %02x\n", in->MC_ID );//Management Controller should set this field to 0x00 + printf ("Header_Revision: %02x\n", in->Header_Revision );//For NC-SI 1.0 spec, this field has to set 0x01 +// printf ("Reserved_1 : %02x\n", in->Reserved_1 ); //Reserved has to set to 0x00 + printf ("IID : %02x\n", in->IID );//Instance ID + printf ("Command : %02x\n", in->Command ); + printf ("Channel_ID : %02x\n", in->Channel_ID ); + printf ("Payload_Length : %04x\n", in->Payload_Length );//Payload Length = 12 bits, 4 bits are reserved +// printf ("Reserved_2 : %04x\n", in->Reserved_2 ); +// printf ("Reserved_3 : %04x\n", in->Reserved_3 ); +// printf ("Reserved_4 : %04x\n", in->Reserved_4 ); +// printf ("Reserved_5 : %04x\n", in->Reserved_5 ); + printf ("Response_Code : %04x\n", in->Response_Code ); + printf ("Reason_Code : %04x\n", in->Reason_Code ); + printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 3], in->Payload_Data[ 2], in->Payload_Data[ 1], in->Payload_Data[ 0]); +// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[ 7], in->Payload_Data[ 6], in->Payload_Data[ 5], in->Payload_Data[ 4]); +// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[11], in->Payload_Data[10], in->Payload_Data[ 9], in->Payload_Data[ 8]); +// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[15], in->Payload_Data[14], in->Payload_Data[13], in->Payload_Data[12]); +// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[19], in->Payload_Data[18], in->Payload_Data[17], in->Payload_Data[16]); +// printf ("Payload_Data : %02x%02x%02x%02x\n", in->Payload_Data[23], in->Payload_Data[22], in->Payload_Data[21], in->Payload_Data[20]); +} + +//------------------------------------------------------------ +void NCSI_Struct_Initialize_SLT (void) { + int i; + + ULONG NCSI_RxDatBase; + + InstanceID = 0; + NCSI_RxTimeOutScale = 1; + + for (i = 0; i < 6; i++) { + NCSI_Request_SLT.DA[i] = 0xFF; + } + + for (i = 0; i < 6; i++) { +// NCSI_Request.SA[i] = i<<2; + NCSI_Request_SLT.SA[i] = SA[i]; + } + + NCSI_Request_SLT.EtherType = WDSwap_SLT(0x88F8); // EtherType = 0x88F8 (DMTF NC-SI) page 50, table 8, NC-SI spec. version 1.0.0 + NCSI_Request_SLT.MC_ID = 0; + NCSI_Request_SLT.Header_Revision = 0x01; + NCSI_Request_SLT.Reserved_1 = 0; + NCSI_Request_SLT.Reserved_2 = 0; + NCSI_Request_SLT.Reserved_3 = 0; + + NCSI_TxByteBUF = (unsigned char *) &NCSI_TxDWBUF[0]; + NCSI_RxByteBUF = (unsigned char *) &NCSI_RxDWBUF[0]; + + NCSI_RxDesBase = H_RDES_BASE; + NCSI_RxDatBase = NCSI_RxDMA_BASE; + + for (i = 0; i < NCSI_RxDESNum - 1; i++) { + WriteSOC_DD( ( NCSI_RxDesBase + 0 ), 0x00000000 ); + WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 ); + WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 ); + WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730 + NCSI_RxDesBase += 16; + NCSI_RxDatBase += NCSI_RxDMA_PakSize; + } + WriteSOC_DD( ( NCSI_RxDesBase + 0 ), EOR_IniVal ); + WriteSOC_DD( ( NCSI_RxDesBase + 4 ), 0x00000000 ); + WriteSOC_DD( ( NCSI_RxDesBase + 8 ), 0x00000000 ); + WriteSOC_DD( ( NCSI_RxDesBase + 0x0C ), (NCSI_RxDatBase + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730 + + NCSI_RxDesBase = H_RDES_BASE; +} + +//------------------------------------------------------------ +void Calculate_Checksum_NCSI (unsigned char *buffer_base, int Length) { + ULONG CheckSum = 0; + ULONG Data; + ULONG Data1; + int i; + + // Calculate checksum is from byte 14 of ethernet Haeder and Control packet header + // Page 50, NC-SI spec. ver. 1.0.0 form DMTF + for (i = 14; i < Length; i += 2 ) { + Data = buffer_base[i]; + Data1 = buffer_base[i + 1]; + CheckSum += ((Data << 8) + Data1); + } + Payload_Checksum_NCSI = DWSwap_SLT(~(CheckSum) + 1); //2's complement +} + +//------------------------------------------------------------ +// return 0: it is PASS +// return 1: it is FAIL +//------------------------------------------------------------ +char NCSI_Rx_SLT (unsigned char command) { + +#define NCSI_RX_RETRY_TIME 2 + int timeout = 0; + int bytesize; + int dwsize; + int i; + int retry = 0; + char ret = 1; + + ULONG NCSI_RxDatBase; + ULONG NCSI_RxDesDat; + ULONG NCSI_RxData; + + + do { + WriteSOC_DD( ( H_MAC_BASE + 0x1C ), 0x00000000 );//Rx Poll + + do { + NCSI_RxDesDat = ReadSOC_DD(NCSI_RxDesBase); + if ( ++timeout > TIME_OUT_NCSI * NCSI_RxTimeOutScale ) { + #ifdef SLT_DOS + fprintf(fp_log, "[Cmd:%02X][NCSI-RxDesOwn] %08lX \n", command, NCSI_RxDesDat ); + #endif + return( FindErr(Err_NCSI_Check_RxOwnTimeOut) ); + } + } while( HWOwnRx(NCSI_RxDesDat) ); + + #ifdef CheckRxErr + if (NCSI_RxDesDat & 0x00040000) { + #ifdef SLT_DOS + fprintf(fp_log, "[RxDes] Error RxErr %08lx\n", NCSI_RxDesDat); + #endif + FindErr_Des(Check_Des_RxErr); + } + #endif + + #ifdef CheckOddNibble + if (NCSI_RxDesDat & 0x00400000) { + #ifdef SLT_DOS + fprintf(fp_log, "[RxDes] Odd Nibble %08lx\n", NCSI_RxDesDat); + #endif + FindErr_Des(Check_Des_OddNibble); + } + #endif + + #ifdef CheckCRC + if (NCSI_RxDesDat & 0x00080000) { + #ifdef SLT_DOS + fprintf(fp_log, "[RxDes] Error CRC %08lx\n", NCSI_RxDesDat); + #endif + FindErr_Des(Check_Des_CRC); + } + #endif + + #ifdef CheckRxFIFOFull + if (NCSI_RxDesDat & 0x00800000) { + #ifdef SLT_DOS + fprintf(fp_log, "[RxDes] Error Rx FIFO Full %08lx\n", NCSI_RxDesDat); + #endif + FindErr_Des(Check_Des_RxFIFOFull); + } + #endif + + // Get point of RX DMA buffer + NCSI_RxDatBase = ReadSOC_DD( NCSI_RxDesBase + 0x0C ); + NCSI_RxData = ReadSOC_DD( NCSI_RxDatBase + 0x0C ); + + if ( HWEOR( NCSI_RxDesDat ) ) { + // it is last the descriptor in the receive Ring + WriteSOC_DD( NCSI_RxDesBase , EOR_IniVal ); + NCSI_RxDesBase = H_RDES_BASE; + } + else { + WriteSOC_DD( NCSI_RxDesBase , 0x00000000 ); + NCSI_RxDesBase += 16; + } + + // Get RX valid data in offset 00h of RXDS#0 + bytesize = (NCSI_RxDesDat & 0x3fff); + + // Fill up to multiple of 4 + if ( ( bytesize % 4 ) != 0 ) + dwsize = ( bytesize >> 2 ) + 1; + else + dwsize = bytesize >> 2; + + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log ,"[Rx] %d bytes(%xh)\n", bytesize, bytesize); + #endif + + for (i = 0; i < dwsize; i++) { + NCSI_RxDWBUF[i] = ReadSOC_DD(NCSI_RxDatBase + ( i << 2 )); + if ( PrintNCSIEn ) { + if ( i == ( dwsize - 1 ) ) { + switch (bytesize % 4) { + case 0 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffffff; break; + case 3 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffffff ; break; + case 2 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xffff ; break; + case 1 : NCSI_RxDWBUF[i] = NCSI_RxDWBUF[i] & 0xff ; break; + } + #ifdef SLT_DOS + switch (bytesize % 4) { + case 0 : fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) ); break; + case 3 : fprintf(fp_log ,"[Rx%02d]--%06lx %06lx--\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 8 ); break; + case 2 : fprintf(fp_log ,"[Rx%02d]----%04lx %04lx----\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 16 ); break; + case 1 : fprintf(fp_log ,"[Rx%02d]------%02lx %02lx------\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i]) >> 24 ); break; + default : fprintf(fp_log ,"[Rx%02d]error", i); break; + } + #endif + } + else { + #ifdef SLT_DOS + fprintf(fp_log ,"[Rx%02d]%08lx %08lx\n", i, NCSI_RxDWBUF[i], DWSwap_SLT(NCSI_RxDWBUF[i])); + #endif + } + } + } // End for (i = 0; i < dwsize; i++) + + // EtherType field of the response packet should be 0x88F8 + if ((NCSI_RxData & 0xffff) == 0xf888) { + memcpy (&NCSI_Respond_SLT, NCSI_RxByteBUF, bytesize); + + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log ,"[Rx IID:%2d]\n", NCSI_Respond_SLT.IID); + #endif + + NCSI_Respond_SLT.EtherType = WDSwap_SLT( NCSI_Respond_SLT.EtherType ); + NCSI_Respond_SLT.Payload_Length = WDSwap_SLT( NCSI_Respond_SLT.Payload_Length ); + NCSI_Respond_SLT.Response_Code = WDSwap_SLT( NCSI_Respond_SLT.Response_Code ); + NCSI_Respond_SLT.Reason_Code = WDSwap_SLT( NCSI_Respond_SLT.Reason_Code ); + + ret = 0; + break; + } + else { + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log, "[Skip] Not NCSI Response: %08lx\n", NCSI_RxData); + #endif + + retry++; + } + } while ( retry < NCSI_RX_RETRY_TIME ); + + return( ret ); +} // End char NCSI_Rx_SLT (void) + +//------------------------------------------------------------ +char NCSI_Tx (void) { + int bytesize; + int dwsize; + int i; + int timeout = 0; + ULONG NCSI_TxDesDat; + + // Header of NC-SI command format is 34 bytes. page 58, NC-SI spec. ver 1.0.0 from DMTF + // The minimum size of a NC-SI package is 64 bytes. + bytesize = 34 + WDSwap_SLT(NCSI_Request_SLT.Payload_Length); + if ( bytesize < 64 ) { + memset (NCSI_TxByteBUF + bytesize, 0, 60 - bytesize); + bytesize = 64; + } + + // Fill up to multiple of 4 +// dwsize = (bytesize + 3) >> 2; + if ( ( bytesize % 4 ) != 0 ) + dwsize = ( bytesize >> 2 ) + 1; + else + dwsize = bytesize >> 2; + + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log ,"[Tx IID:%2d] %d bytes(%xh)\n", NCSI_Request_SLT.IID, bytesize, bytesize); + #endif + + // Copy data to DMA buffer + for (i = 0; i < dwsize; i++) { + WriteSOC_DD( DMA_BASE + (i << 2), NCSI_TxDWBUF[i] ); + if ( PrintNCSIEn ) { + if (i == (dwsize - 1)) { + switch (bytesize % 4) { + case 0 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0xffffffff; break; + case 3 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x00ffffff; break; + case 2 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x0000ffff; break; + case 1 : NCSI_TxDWBUF[i] = NCSI_TxDWBUF[i] & 0x000000ff; break; + } + #ifdef SLT_DOS + switch (bytesize % 4) { + case 0 : fprintf(fp_log ,"[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) ); break; + case 3 : fprintf(fp_log ,"[Tx%02d]--%06x %06x--\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 8 ); break; + case 2 : fprintf(fp_log ,"[Tx%02d]----%04x %04x----\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 16 ); break; + case 1 : fprintf(fp_log ,"[Tx%02d]------%02x %02x------\n", i, NCSI_TxDWBUF[i], DWSwap_SLT( NCSI_TxDWBUF[i]) >> 24 ); break; + default : fprintf(fp_log ,"[Tx%02d]error", i); break; + } + #endif + } + else { + #ifdef SLT_DOS + fprintf( fp_log , "[Tx%02d]%08x %08x\n", i, NCSI_TxDWBUF[i], DWSwap_SLT(NCSI_TxDWBUF[i]) ); + #endif + } + } + } // End for (i = 0; i < dwsize; i++) + + // Setting one TX descriptor + WriteSOC_DD( H_TDES_BASE + 0x04, 0 ); + WriteSOC_DD( H_TDES_BASE + 0x08, 0 ); + WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730 + WriteSOC_DD( H_TDES_BASE , 0xf0008000 + bytesize ); + // Fire + WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll + + do { + NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE); + if ( ++timeout > TIME_OUT_NCSI ) { + #ifdef SLT_DOS + fprintf(fp_log, "[NCSI-TxDesOwn] %08lx\n", NCSI_TxDesDat); + #endif + + return(FindErr(Err_NCSI_Check_TxOwnTimeOut)); + } + } while ( HWOwnTx(NCSI_TxDesDat) ); + + return(0); +} // End char NCSI_Tx (void) + +//------------------------------------------------------------ +char NCSI_ARP (void) { + int i; + int timeout = 0; + ULONG NCSI_TxDesDat; + + if ( ARPNumCnt ) { + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log ,"[ARP] 60 bytes x%d\n", ARPNumCnt); + #endif + + for (i = 0; i < 15; i++) { + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log ,"[Tx%02d] %08x %08x\n", i, ARP_data[i], DWSwap_SLT(ARP_data[i])); + #endif + WriteSOC_DD( DMA_BASE + ( i << 2 ), ARP_data[i] ); + } + WriteSOC_DD( H_TDES_BASE + 0x04, 0 ); + WriteSOC_DD( H_TDES_BASE + 0x08, 0 ); + WriteSOC_DD( H_TDES_BASE + 0x0C, (DMA_BASE + CPU_BUS_ADDR_SDRAM_OFFSET) ); // 20130730 + WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60 ); + + for (i = 0; i < ARPNumCnt; i++) { + WriteSOC_DD( H_TDES_BASE , 0xf0008000 + 60); + + WriteSOC_DD( H_MAC_BASE + 0x18, 0x00000000 );//Tx Poll + + timeout = 0; + do { + NCSI_TxDesDat = ReadSOC_DD(H_TDES_BASE); + + if (++timeout > TIME_OUT_NCSI) { + #ifdef SLT_DOS + fprintf(fp_log, "[ARP-TxDesOwn] %08lx\n", NCSI_TxDesDat); + #endif + + return(FindErr(Err_NCSI_Check_ARPOwnTimeOut)); + } + } while (HWOwnTx(NCSI_TxDesDat)); + } + } + return(0); +} // End char NCSI_ARP (void) + +//------------------------------------------------------------ +void WrRequest (unsigned char command, unsigned char id, unsigned short length) { + + NCSI_Request_SLT.IID = InstanceID; + NCSI_Request_SLT.Command = command; + NCSI_Request_SLT.Channel_ID = id; + NCSI_Request_SLT.Payload_Length = WDSwap_SLT(length); + + memcpy ( NCSI_TxByteBUF , &NCSI_Request_SLT , 30 ); + memcpy ((NCSI_TxByteBUF + 30 ), &NCSI_Payload_Data , length); + Calculate_Checksum_NCSI(NCSI_TxByteBUF, 30 + length); + memcpy ((NCSI_TxByteBUF + 30 + length), &Payload_Checksum_NCSI, 4 ); +} + +//------------------------------------------------------------ +void NCSI_PrintCommandStr (unsigned char command, unsigned iid) { + switch (command & 0x80) { + case 0x80 : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Respond]", iid, command); break; + default : sprintf(NCSI_CommandStr, "IID:%3d [%02x][Request]", iid, command); break; + } + switch (command & 0x7f) { + case 0x00 : sprintf(NCSI_CommandStr, "%s[CLEAR_INITIAL_STATE ]", NCSI_CommandStr); break; + case 0x01 : sprintf(NCSI_CommandStr, "%s[SELECT_PACKAGE ]", NCSI_CommandStr); break; + case 0x02 : sprintf(NCSI_CommandStr, "%s[DESELECT_PACKAGE ]", NCSI_CommandStr); break; + case 0x03 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL ]", NCSI_CommandStr); break; + case 0x04 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL ]", NCSI_CommandStr); break; + case 0x05 : sprintf(NCSI_CommandStr, "%s[RESET_CHANNEL ]", NCSI_CommandStr); break; + case 0x06 : sprintf(NCSI_CommandStr, "%s[ENABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break; + case 0x07 : sprintf(NCSI_CommandStr, "%s[DISABLE_CHANNEL_NETWORK_TX ]", NCSI_CommandStr); break; + case 0x08 : sprintf(NCSI_CommandStr, "%s[AEN_ENABLE ]", NCSI_CommandStr); break; + case 0x09 : sprintf(NCSI_CommandStr, "%s[SET_LINK ]", NCSI_CommandStr); break; + case 0x0A : sprintf(NCSI_CommandStr, "%s[GET_LINK_STATUS ]", NCSI_CommandStr); break; + case 0x0B : sprintf(NCSI_CommandStr, "%s[SET_VLAN_FILTER ]", NCSI_CommandStr); break; + case 0x0C : sprintf(NCSI_CommandStr, "%s[ENABLE_VLAN ]", NCSI_CommandStr); break; + case 0x0D : sprintf(NCSI_CommandStr, "%s[DISABLE_VLAN ]", NCSI_CommandStr); break; + case 0x0E : sprintf(NCSI_CommandStr, "%s[SET_MAC_ADDRESS ]", NCSI_CommandStr); break; + case 0x10 : sprintf(NCSI_CommandStr, "%s[ENABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break; + case 0x11 : sprintf(NCSI_CommandStr, "%s[DISABLE_BROADCAST_FILTERING ]", NCSI_CommandStr); break; + case 0x12 : sprintf(NCSI_CommandStr, "%s[ENABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break; + case 0x13 : sprintf(NCSI_CommandStr, "%s[DISABLE_GLOBAL_MULTICAST_FILTERING ]", NCSI_CommandStr); break; + case 0x14 : sprintf(NCSI_CommandStr, "%s[SET_NCSI_FLOW_CONTROL ]", NCSI_CommandStr); break; + case 0x15 : sprintf(NCSI_CommandStr, "%s[GET_VERSION_ID ]", NCSI_CommandStr); break; + case 0x16 : sprintf(NCSI_CommandStr, "%s[GET_CAPABILITIES ]", NCSI_CommandStr); break; + case 0x17 : sprintf(NCSI_CommandStr, "%s[GET_PARAMETERS ]", NCSI_CommandStr); break; + case 0x18 : sprintf(NCSI_CommandStr, "%s[GET_CONTROLLER_PACKET_STATISTICS ]", NCSI_CommandStr); break; + case 0x19 : sprintf(NCSI_CommandStr, "%s[GET_NCSI_STATISTICS ]", NCSI_CommandStr); break; + case 0x1A : sprintf(NCSI_CommandStr, "%s[GET_NCSI_PASS_THROUGH_STATISTICS ]", NCSI_CommandStr); break; + case 0x50 : sprintf(NCSI_CommandStr, "%s[OEM_COMMAND ]", NCSI_CommandStr); break; + default : sprintf(NCSI_CommandStr, "%s Not Support Command", NCSI_CommandStr); break ; + } +} // End void NCSI_PrintCommandStr (unsigned char command, unsigned iid) + +//------------------------------------------------------------ +void NCSI_PrintCommandType (unsigned char command, unsigned iid) { + NCSI_PrintCommandStr(command, iid); + printf ("%s\n", NCSI_CommandStr); +} + +//------------------------------------------------------------ +void NCSI_PrintCommandType2File (unsigned char command, unsigned iid) { + NCSI_PrintCommandStr(command, iid); + #ifdef SLT_DOS + fprintf(fp_log, "%s\n", NCSI_CommandStr); + #endif +} + +//------------------------------------------------------------ +char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length) { + int Retry = 0; + char ret; + + do { + InstanceID++; + WrRequest(command, id, length); + + ret = NCSI_Tx();
if ( ret != 0 ) + { + // printf("======> NCSI_Tx return code = %X\n", ret ); + return(1); + }
+#ifdef Print_PackageName + NCSI_PrintCommandType(command, InstanceID); +#endif + +#ifdef NCSI_EnableDelay_EachPackage + delay(Delay_EachPackage); +#endif + if ( NCSI_Rx_SLT( command ) ) + return(2); + + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log, "[Request] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x\n", WDSwap_SLT(NCSI_Request_SLT.EtherType), + NCSI_Request_SLT.MC_ID, + NCSI_Request_SLT.Header_Revision, + NCSI_Request_SLT.IID, + NCSI_Request_SLT.Command, + NCSI_Request_SLT.Channel_ID, + WDSwap_SLT(NCSI_Request_SLT.Payload_Length) ); + if ( PrintNCSIEn ) + fprintf(fp_log, "[Respond] ETyp:%04x MC_ID:%02x HeadVer:%02x IID:%02x Comm:%02x ChlID:%02x PayLen:%04x ResCd:%02x ReaCd:%02x\n", + NCSI_Respond_SLT.EtherType, + NCSI_Respond_SLT.MC_ID, + NCSI_Respond_SLT.Header_Revision, + NCSI_Respond_SLT.IID, + NCSI_Respond_SLT.Command, + NCSI_Respond_SLT.Channel_ID, + NCSI_Respond_SLT.Payload_Length, + NCSI_Respond_SLT.Response_Code, + NCSI_Respond_SLT.Reason_Code); + #endif + + if ( (NCSI_Respond_SLT.IID != InstanceID) || + (NCSI_Respond_SLT.Command != (command | 0x80)) || + (NCSI_Respond_SLT.Response_Code != COMMAND_COMPLETED) ) { + #ifdef SLT_DOS + if ( PrintNCSIEn ) + fprintf(fp_log, "Retry: Command = %x, Response_Code = %x\n", NCSI_Request_SLT.Command, NCSI_Respond_SLT.Response_Code); + + #endif + Retry++; + } + else { + if ( PrintNCSIEn ) + NCSI_PrintCommandType2File(command, InstanceID); + + return(0); + } + } while (Retry <= SENT_RETRY_COUNT); + + return( 3 ); +} // End char NCSI_SentWaitPacket (unsigned char command, unsigned char id, unsigned short length) + +//------------------------------------------------------------ +char Clear_Initial_State_SLT (int Channel_ID) {//Command:0x00 + return(NCSI_SentWaitPacket(CLEAR_INITIAL_STATE, (NCSI_Cap_SLT.Package_ID << 5) + Channel_ID, 0));//Internal Channel ID = 0 +} + +//------------------------------------------------------------ +char Select_Package_SLT (int Package_ID) {//Command:0x01 + memset ((void *)NCSI_Payload_Data, 0, 4); + NCSI_Payload_Data[3] = 1; //Arbitration Disable + + return(NCSI_SentWaitPacket(SELECT_PACKAGE, (Package_ID << 5) + 0x1F, 4));//Internal Channel ID = 0x1F, 0x1F means all channel +} + +//------------------------------------------------------------ +void Select_Active_Package_SLT (void) {//Command:0x01 + memset ((void *)NCSI_Payload_Data, 0, 4); + NCSI_Payload_Data[3] = 1; //Arbitration Disable + + if (NCSI_SentWaitPacket(SELECT_PACKAGE, (NCSI_Cap_SLT.Package_ID << 5) + 0x1F, 4)) {//Internal Channel ID = 0x1F + FindErr_NCSI(NCSI_LinkFail_Select_Active_Package); + } +} + +//------------------------------------------------------------ +void DeSelect_Package_SLT (int Package_ID) {//Command:0x02 + NCSI_SentWaitPacket(DESELECT_PACKAGE, (Package_ID << 5) + 0x1F, 0);//Internal Channel ID = 0x1F, 0x1F means all channel + +#ifdef NCSI_EnableDelay_DeSelectPackage + delay(Delay_DeSelectPackage); +#endif +} + +//------------------------------------------------------------ +void Enable_Channel_SLT (void) {//Command:0x03 + if ( NCSI_SentWaitPacket(ENABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) { + FindErr_NCSI(NCSI_LinkFail_Enable_Channel); + } +} + +//------------------------------------------------------------ +void Disable_Channel_SLT (void) {//Command:0x04 + memset ((void *)NCSI_Payload_Data, 0, 4); + NCSI_Payload_Data[3] = 0x1; //ALD + + if (NCSI_SentWaitPacket(DISABLE_CHANNEL, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4)) { + FindErr_NCSI(NCSI_LinkFail_Disable_Channel); + } +} +void Enable_Network_TX_SLT (void) {//Command:0x06 + if ( NCSI_SentWaitPacket(ENABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) { + FindErr_NCSI(NCSI_LinkFail_Enable_Network_TX); + } +} + +//------------------------------------------------------------ +void Disable_Network_TX_SLT (void) {//Command:0x07 + if ( NCSI_SentWaitPacket(DISABLE_CHANNEL_NETWORK_TX, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) { + FindErr_NCSI(NCSI_LinkFail_Disable_Network_TX); + } +} + +//------------------------------------------------------------ +void Set_Link_SLT (void) {//Command:0x09 + memset ((void *)NCSI_Payload_Data, 0, 8); + NCSI_Payload_Data[2] = 0x02; //full duplex +// NCSI_Payload_Data[3] = 0x04; //100M, auto-disable + NCSI_Payload_Data[3] = 0x05; //100M, auto-enable + + NCSI_SentWaitPacket(SET_LINK, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8); +} + +//------------------------------------------------------------ +char Get_Link_Status_SLT (void) {//Command:0x0a + + if (NCSI_SentWaitPacket(GET_LINK_STATUS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) { + return(0); + } + else { + if (NCSI_Respond_SLT.Payload_Data[3] & 0x20) { + if (NCSI_Respond_SLT.Payload_Data[3] & 0x40) { + if (NCSI_Respond_SLT.Payload_Data[3] & 0x01) + return(1); //Link Up or Not + else + return(0); + } else + return(0); //Auto Negotiate did not finish + } else { + if (NCSI_Respond_SLT.Payload_Data[3] & 0x01) + return(1); //Link Up or Not + else + return(0); + } + } +} // End char Get_Link_Status_SLT (void) + +//------------------------------------------------------------ +void Enable_Set_MAC_Address_SLT (void) {//Command:0x0e + int i; + + for ( i = 0; i < 6; i++ ) { + NCSI_Payload_Data[i] = NCSI_Request_SLT.SA[i]; + } + NCSI_Payload_Data[6] = 1; //MAC Address Num = 1 --> address filter 1, fixed in sample code + NCSI_Payload_Data[7] = UNICAST + 0 + ENABLE_MAC_ADDRESS_FILTER; //AT + Reserved + E + + if ( NCSI_SentWaitPacket(SET_MAC_ADDRESS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 8) ) { + FindErr_NCSI(NCSI_LinkFail_Enable_Set_MAC_Address); + } +} + +//------------------------------------------------------------ +void Enable_Broadcast_Filter_SLT (void) {//Command:0x10 + memset ((void *)NCSI_Payload_Data, 0, 4); + NCSI_Payload_Data[3] = 0xF; //ARP, DHCP, NetBIOS + + if (NCSI_SentWaitPacket(ENABLE_BROADCAST_FILTERING, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 4) ) { + FindErr_NCSI(NCSI_LinkFail_Enable_Broadcast_Filter); + } +} + +//------------------------------------------------------------ +void Get_Version_ID_SLT (void) {//Command:0x15 + + if (NCSI_SentWaitPacket(GET_VERSION_ID, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0) ) { + FindErr_NCSI(NCSI_LinkFail_Get_Version_ID); + } + else { +#ifdef Print_Version_ID + printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 0], NCSI_Respond_SLT.Payload_Data[ 1], NCSI_Respond_SLT.Payload_Data[ 2], NCSI_Respond_SLT.Payload_Data[ 3]); + printf ("NCSI Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 4], NCSI_Respond_SLT.Payload_Data[ 5], NCSI_Respond_SLT.Payload_Data[ 6], NCSI_Respond_SLT.Payload_Data[ 7]); + printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[ 8], NCSI_Respond_SLT.Payload_Data[ 9], NCSI_Respond_SLT.Payload_Data[10], NCSI_Respond_SLT.Payload_Data[11]); + printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[12], NCSI_Respond_SLT.Payload_Data[13], NCSI_Respond_SLT.Payload_Data[14], NCSI_Respond_SLT.Payload_Data[15]); + printf ("Firmware Name String: %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[16], NCSI_Respond_SLT.Payload_Data[17], NCSI_Respond_SLT.Payload_Data[18], NCSI_Respond_SLT.Payload_Data[19]); + printf ("Firmware Version : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[20], NCSI_Respond_SLT.Payload_Data[21], NCSI_Respond_SLT.Payload_Data[22], NCSI_Respond_SLT.Payload_Data[23]); + printf ("PCI DID/VID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[24], NCSI_Respond_SLT.Payload_Data[25], NCSI_Respond_SLT.Payload_Data[26], NCSI_Respond_SLT.Payload_Data[27]); + printf ("PCI SSID/SVID : %02x %02x/%02x %02x\n", NCSI_Respond_SLT.Payload_Data[28], NCSI_Respond_SLT.Payload_Data[29], NCSI_Respond_SLT.Payload_Data[30], NCSI_Respond_SLT.Payload_Data[31]); + printf ("Manufacturer ID : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[32], NCSI_Respond_SLT.Payload_Data[33], NCSI_Respond_SLT.Payload_Data[34], NCSI_Respond_SLT.Payload_Data[35]); + printf ("Checksum : %02x %02x %02x %02x\n", NCSI_Respond_SLT.Payload_Data[36], NCSI_Respond_SLT.Payload_Data[37], NCSI_Respond_SLT.Payload_Data[38], NCSI_Respond_SLT.Payload_Data[39]); +#endif + NCSI_Cap_SLT.PCI_DID_VID = (NCSI_Respond_SLT.Payload_Data[24]<<24) + | (NCSI_Respond_SLT.Payload_Data[25]<<16) + | (NCSI_Respond_SLT.Payload_Data[26]<< 8) + | (NCSI_Respond_SLT.Payload_Data[27] ); + NCSI_Cap_SLT.ManufacturerID = (NCSI_Respond_SLT.Payload_Data[32]<<24) + | (NCSI_Respond_SLT.Payload_Data[33]<<16) + | (NCSI_Respond_SLT.Payload_Data[34]<< 8) + | (NCSI_Respond_SLT.Payload_Data[35] ); + } +} // End void Get_Version_ID_SLT (void) + +//------------------------------------------------------------ +void Get_Capabilities_SLT (void) {//Command:0x16 + + if (NCSI_SentWaitPacket(GET_CAPABILITIES, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0)) { + FindErr_NCSI(NCSI_LinkFail_Get_Capabilities); + } + else { + NCSI_Cap_SLT.Capabilities_Flags = NCSI_Respond_SLT.Payload_Data[0]; + NCSI_Cap_SLT.Broadcast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[1]; + NCSI_Cap_SLT.Multicast_Packet_Filter_Capabilities = NCSI_Respond_SLT.Payload_Data[2]; + NCSI_Cap_SLT.Buffering_Capabilities = NCSI_Respond_SLT.Payload_Data[3]; + NCSI_Cap_SLT.AEN_Control_Support = NCSI_Respond_SLT.Payload_Data[4]; + } +} + +//------------------------------------------------------------ +void Get_Controller_Packet_Statistics (void) {//Command:0x18 + + NCSI_SentWaitPacket(GET_CONTROLLER_PACKET_STATISTICS, (NCSI_Cap_SLT.Package_ID << 5) + NCSI_Cap_SLT.Channel_ID, 0); +} + +//------------------------------------------------------------ +char phy_ncsi (void) { + ULONG Channel_Found = 0; + ULONG Package_Found = 0; + ULONG Re_Send; + ULONG Err_Flag_bak; + ULONG pkg_idx; + ULONG chl_idx; + ULONG Link_Status; + ULONG NCSI_LinkFail_Val_bak; + + number_chl = 0; + number_pak = 0; + + NCSI_LinkFail_Val = 0; +
#ifdef SLT_DOS + fprintf(fp_log, "\n\n======> Start:\n" ); + #endif
+ NCSI_Struct_Initialize_SLT(); + + #ifdef NCSI_Skip_Phase1_DeSelectPackage + #else + + //NCSI Start + //Disable Channel then DeSelect Package + for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) { + // Ignore error flag in the NCSI command + Err_Flag_bak = Err_Flag; + NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val; + select_flag[pkg_idx] = Select_Package_SLT (pkg_idx); // Command:0x01 + Err_Flag = Err_Flag_bak; + NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak; + + if ( select_flag[pkg_idx] == 0 ) { + NCSI_Cap_SLT.Package_ID = pkg_idx; + + for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) { + NCSI_Cap_SLT.Channel_ID = chl_idx; + // Ignore error flag in the NCSI command + Err_Flag_bak = Err_Flag; + NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val; + Disable_Channel_SLT(); // Command: 0x04 + Err_Flag = Err_Flag_bak; + NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak; + } + #ifdef NCSI_Skip_DeSelectPackage + #else + DeSelect_Package_SLT (pkg_idx); // Command:0x02 + #endif + } // End if ( select_flag[pkg_idx] == 0 ) + } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) + #endif + + //Select Package + for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) { + #ifdef NCSI_Skip_Phase1_DeSelectPackage + // Ignore error flag in the NCSI command + Err_Flag_bak = Err_Flag; + NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val; + select_flag[pkg_idx] = Select_Package_SLT (pkg_idx);//Command:0x01 + Err_Flag = Err_Flag_bak; + NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak; + #endif + + if (select_flag[pkg_idx] == 0) { + //NCSI_RxTimeOutScale = 1000; + NCSI_RxTimeOutScale = 10; + number_pak++; + Package_Found = 1; + NCSI_Cap_SLT.Package_ID = pkg_idx; + + if ( !(IOTiming||IOTimingBund) ) + printf ("====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID); + #ifdef SLT_DOS + fprintf(fp_log, "====Find Package ID: %d\n", NCSI_Cap_SLT.Package_ID); + #endif + + #ifdef NCSI_Skip_Phase1_DeSelectPackage + #else + Select_Package_SLT (pkg_idx);//Command:0x01 + #endif + + // Scan all channel in the package + for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) { + // backup error flag + Err_Flag_bak = Err_Flag; + NCSI_LinkFail_Val_bak = NCSI_LinkFail_Val; + if (Clear_Initial_State_SLT(chl_idx) == 0) { //Command:0x00 + number_chl++; + Channel_Found = 1; + NCSI_Cap_SLT.Channel_ID = chl_idx; + + if ( !(IOTiming || IOTimingBund) ) + printf ("--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID); + + #ifdef SLT_DOS + fprintf(fp_log, "--------Find Channel ID: %d\n", NCSI_Cap_SLT.Channel_ID); + #endif + // Get Version and Capabilities + Get_Version_ID_SLT(); //Command:0x15 + Get_Capabilities_SLT(); //Command:0x16 + Select_Active_Package_SLT(); //Command:0x01 + Enable_Set_MAC_Address_SLT(); //Command:0x0e + Enable_Broadcast_Filter_SLT(); //Command:0x10 + + // Enable TX + Enable_Network_TX_SLT(); //Command:0x06 + + // Enable Channel + Enable_Channel_SLT(); //Command:0x03 + + // Get Link Status + Re_Send = 0; + do { + #ifdef NCSI_EnableDelay_GetLinkStatus + if ( Re_Send >= 2 ) + delay(Delay_GetLinkStatus); + #endif + + Link_Status = Get_Link_Status_SLT();//Command:0x0a + + if ( Link_Status == LINK_UP ) { + if (!(IOTiming||IOTimingBund)) + printf (" This Channel is LINK_UP\n"); + + #ifdef SLT_DOS + fprintf(fp_log, " This Channel is LINK_UP\n"); + #endif + + NCSI_ARP (); + + break; + } + else if ( Link_Status == LINK_DOWN ) { + if ( Re_Send >= 2 ) { + if ( !(IOTiming || IOTimingBund) ) + printf (" This Channel is LINK_DOWN\n"); + + #ifdef SLT_DOS + fprintf(fp_log, " This Channel is LINK_DOWN\n"); + #endif + + break; + } + } // End if ( Link_Status == LINK_UP ) + } while ( Re_Send++ <= 2 ); + + #ifdef NCSI_Skip_DiSChannel + #else + if ( NCSI_DiSChannel ) { + // Disable TX + Disable_Network_TX_SLT(); //Command:0x07 + // Disable Channel + Disable_Channel_SLT(); //Command:0x04 + } + #endif + } + else { + Err_Flag = Err_Flag_bak; + NCSI_LinkFail_Val = NCSI_LinkFail_Val_bak; + } + } // End for ( chl_idx = 0; chl_idx < MAX_CHANNEL_NUM; chl_idx++ ) + + #ifdef NCSI_Skip_DeSelectPackage + #else + DeSelect_Package_SLT (pkg_idx);//Command:0x02 + #endif + NCSI_RxTimeOutScale = 1; + } + else { + if (!(IOTiming||IOTimingBund)) { + printf ("====Absence of Package ID: %ld\n", pkg_idx); + #ifdef SLT_DOS + fprintf(fp_log, "====Absence of Package ID: %ld\n", pkg_idx); + #endif + } + } // End if (select_flag[pkg_idx] == 0) + } // End for (pkg_idx = 0; pkg_idx < MAX_PACKAGE_NUM; pkg_idx++) + + if ( !Package_Found ) FindErr( Err_NCSI_No_PHY ); + if ( ChannelTolNum != number_chl ) FindErr( Err_NCSI_Channel_Num ); + if ( PackageTolNum != number_pak ) FindErr( Err_NCSI_Package_Num ); +// if ( !Channel_Found) FindErr(); + + if ( Err_Flag ) + return(1); + else + return(0); +} + diff --git a/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c new file mode 100644 index 0000000..77aac47 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/PCI_SPI.c @@ -0,0 +1,83 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define PCI_SPI_C
+static const char ThisFile[] = "PCI_SPI.c";
+
+#include "SWFUNC.H"
+
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+#endif
+#ifdef SLT_DOS
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <conio.h>
+ #include <string.h>
+ #include <dos.h>
+#endif
+
+#include "DEF_SPI.H"
+#include "LIB.H"
+#include "TYPEDEF.H"
+
+#ifdef SPI_BUS
+ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
+{
+ ULONG ulPCIBaseAddress, MMIOBaseAddress, LinearAddressBase, busnum, data;
+
+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE);
+ busnum = 0;
+ while (ulPCIBaseAddress == 0 && busnum < 256) {
+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, busnum);
+ if (ulPCIBaseAddress == 0) {
+ ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, busnum);
+ }
+ if (ulPCIBaseAddress == 0) {
+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1160, busnum);
+ }
+ if (ulPCIBaseAddress == 0) {
+ ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x1180, busnum);
+ }
+ busnum++;
+ }
+ printf ("ulPCIBaseAddress = %lx\n", ulPCIBaseAddress);
+ if (ulPCIBaseAddress != 0) {
+ VGAPCIInfo->ulPCIConfigurationBaseAddress = ulPCIBaseAddress;
+ VGAPCIInfo->usVendorID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF);
+ VGAPCIInfo->usDeviceID = ReadPCIReg(ulPCIBaseAddress, 0, 0xFFFF0000) >> 16;
+ LinearAddressBase = ReadPCIReg (ulPCIBaseAddress, 0x10, 0xFFFFFFF0);
+ VGAPCIInfo->ulPhysicalBaseAddress = MapPhysicalToLinear (LinearAddressBase, 64 * 1024 * 1024 + 0x200000);
+ MMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000);
+ VGAPCIInfo->ulMMIOBaseAddress = MapPhysicalToLinear (MMIOBaseAddress, 64 * 1024 * 1024);
+ VGAPCIInfo->usRelocateIO = ReadPCIReg (ulPCIBaseAddress, 0x18, 0x0000FF80);
+ OUTDWPORT(0xcf8, ulPCIBaseAddress + 0x4);
+ data = INDWPORT(0xcfc);
+ OUTDWPORT(0xcfc, data | 0x3);
+ return TRUE;
+ }
+ else {
+ return FALSE;
+ }
+} // End ULONG GetPCIInfo (DEVICE_PCI_INFO *VGAPCIInfo)
+
+BOOLEAN GetDevicePCIInfo (VIDEO_ENGINE_INFO *VideoEngineInfo)
+{
+ if (GetPCIInfo (&VideoEngineInfo->VGAPCIInfo) == TRUE) {
+ return TRUE;
+ }
+ else {
+ printf("Can not find PCI device!\n");
+ exit(0);
+ return FALSE;
+ }
+} // End
+#endif // End ifdef SPI_BUS
diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.H b/arch/arm/cpu/arm926ejs/aspeed/PHY.H new file mode 100644 index 0000000..81d9470 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.H @@ -0,0 +1,56 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef PHY_H
+#define PHY_H
+
+//
+// Define
+//
+#define Enable_SearchPHYID //[ON] (Search vlid PHY ID)
+#define Enable_CheckZeroPHYID //[ON] (Check PHY ID with value 0)
+
+#ifdef Enable_CheckZeroPHYID
+ #define PHY_IS_VALID( dat ) ( ( (dat & 0xffff) != 0xffff ) && ( ( dat & 0xffff ) != 0x0 ) )
+#else
+ #define PHY_IS_VALID( dat ) ( ( dat & 0xffff) != 0xffff )
+#endif
+
+// Define PHY basic register
+#define PHY_REG_BMCR 0x00 // Basic Mode Control Register
+#define PHY_REG_BMSR 0x01 // Basic Mode Status Register
+#define PHY_REG_ID_1 0x02
+#define PHY_REG_ID_2 0x03
+#define PHY_ANER 0x06 // Auto-negotiation Expansion Register
+#define PHY_GBCR 0x09 // 1000Base-T Control Register
+#define PHY_SR 0x11 // PHY Specific Status Register
+#define PHY_INER 0x12 // Interrupt Enable Register
+
+#define TIME_OUT_PHY_RW 10000
+#define TIME_OUT_PHY_Rst 10000
+
+#define PHYID3_Mask 0xfc00 //0xffc0
+
+/* --- Note for SettingPHY chip ---
+void phy_xxxx (int loop_phy) {
+
+ if ( BurstEnable ) {
+ // IEEE test
+ }
+ else if (loop_phy) {
+ // Internal loop back
+ }
+ else {
+ // external loop back
+ }
+}
+----------------------------------- */
+
+#endif // PHY_H
diff --git a/arch/arm/cpu/arm926ejs/aspeed/PHY.c b/arch/arm/cpu/arm926ejs/aspeed/PHY.c new file mode 100644 index 0000000..db73a70 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/PHY.c @@ -0,0 +1,1541 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define PHY_C
+static const char ThisFile[] = "PHY.c";
+
+#include "SWFUNC.H"
+
+#ifdef SLT_UBOOT
+ #include <common.h>
+ #include <command.h>
+ #include "COMMINF.H"
+ #include "STDUBOOT.H"
+#endif
+#ifdef SLT_DOS
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <conio.h>
+ #include <string.h>
+ #include "COMMINF.H"
+#endif
+
+#include "PHY.H"
+#include "TYPEDEF.H"
+#include "IO.H"
+
+ULONG PHY_09h;
+ULONG PHY_18h;
+ULONG PHY_1fh;
+ULONG PHY_06hA[7];
+ULONG PHY_11h;
+ULONG PHY_12h;
+ULONG PHY_15h;
+ULONG PHY_06h;
+char PHYID[256];
+ULONG PHY_00h;
+
+//------------------------------------------------------------
+// PHY R/W basic
+//------------------------------------------------------------
+void phy_write (int adr, ULONG data) {
+ int timeout = 0;
+
+ if (AST2300_NewMDIO) {
+ WriteSOC_DD( MAC_PHYBASE + 0x60, ( data << 16 ) | MAC_PHYWr_New | (PHY_ADR<<5) | (adr & 0x1f));
+
+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
+ if ( ++timeout > TIME_OUT_PHY_RW ) {
+ if (!BurstEnable)
+#ifdef SLT_DOS
+ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
+#endif
+ FindErr( Err_PHY_TimeOut );
+ break;
+ }
+ }
+ }
+ else {
+ WriteSOC_DD( MAC_PHYBASE + 0x64, data );
+
+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYWr | (PHY_ADR<<16) | ((adr & 0x1f) << 21));
+
+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYWr ) {
+ if ( ++timeout > TIME_OUT_PHY_RW ) {
+#ifdef SLT_DOS
+ if (!BurstEnable)
+ fprintf(fp_log, "[PHY-Write] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
+#endif
+ FindErr( Err_PHY_TimeOut );
+ break;
+ }
+ }
+ } // End if (AST2300_NewMDIO)
+
+ if ( DbgPrn_PHYRW )
+ printf ("[Wr ]%02d: %04lx\n", adr, data);
+} // End void phy_write (int adr, ULONG data)
+
+//------------------------------------------------------------
+ULONG phy_read (int adr) {
+ int timeout = 0;
+
+ if ( AST2300_NewMDIO ) {
+ WriteSOC_DD( MAC_PHYBASE + 0x60, MAC_PHYRd_New | (PHY_ADR << 5) | ( adr & 0x1f ) );
+
+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYBusy_New ) {
+ if ( ++timeout > TIME_OUT_PHY_RW ) {
+ if ( !BurstEnable )
+#ifdef SLT_DOS
+ fprintf(fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ));
+#endif
+ FindErr( Err_PHY_TimeOut );
+ break;
+ }
+ }
+
+ DELAY(Delay_PHYRd);
+ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) & 0xffff;
+ }
+ else {
+ WriteSOC_DD( MAC_PHYBASE + 0x60, MDC_Thres | MAC_PHYRd | (PHY_ADR << 16) | ((adr & 0x1f) << 21) );
+
+ while ( ReadSOC_DD( MAC_PHYBASE + 0x60 ) & MAC_PHYRd ) {
+ if ( ++timeout > TIME_OUT_PHY_RW ) {
+#ifdef SLT_DOS
+ if ( !BurstEnable )
+ fprintf( fp_log, "[PHY-Read] Time out: %08lx\n", ReadSOC_DD( MAC_PHYBASE + 0x60 ) );
+#endif
+ FindErr( Err_PHY_TimeOut );
+ break;
+ }
+ }
+
+ DELAY( Delay_PHYRd );
+ Dat_ULONG = ReadSOC_DD( MAC_PHYBASE + 0x64 ) >> 16;
+ }
+
+ if ( DbgPrn_PHYRW )
+ printf ("[Rd ]%02d: %04lx\n", adr, Dat_ULONG );
+
+ return( Dat_ULONG );
+} // End ULONG phy_read (int adr)
+
+//------------------------------------------------------------
+void phy_Read_Write (int adr, ULONG clr_mask, ULONG set_mask) {
+ if ( DbgPrn_PHYRW )
+ printf ("[RW ]%02d: clr:%04lx: set:%04lx\n", adr, clr_mask, set_mask);
+ phy_write(adr, ((phy_read(adr) & (~clr_mask)) | set_mask));
+}
+
+//------------------------------------------------------------
+void phy_out ( int adr ) {
+ printf ("%02d: %04lx\n", adr, phy_read(adr));
+}
+
+//------------------------------------------------------------
+//void phy_outchg ( int adr ) {
+// ULONG PHY_valold = 0;
+// ULONG PHY_val;
+//
+// while (1) {
+// PHY_val = phy_read(adr);
+// if (PHY_valold != PHY_val) {
+// printf ("%02d: %04lx\n", adr, PHY_val);
+// PHY_valold = PHY_val;
+// }
+// }
+//}
+
+//------------------------------------------------------------
+void phy_dump (char *name) {
+ int index;
+
+ printf ("[%s][%d]----------------\n", name, PHY_ADR);
+ for (index = 0; index < 32; index++) {
+ printf ("%02d: %04lx ", index, phy_read(index));
+
+ if ((index % 8) == 7)
+ printf ("\n");
+ }
+}
+
+//------------------------------------------------------------
+void phy_id (BYTE option) {
+
+ ULONG reg_adr;
+ CHAR PHY_ADR_org;
+ FILE_VAR
+
+ GET_OBJ( option )
+
+ PHY_ADR_org = PHY_ADR;
+ for (PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++) {
+
+ PRINT(OUT_OBJ "[%02d] ", PHY_ADR);
+
+ for (reg_adr = 2; reg_adr <= 3; reg_adr++)
+ PRINT(OUT_OBJ "%ld:%04lx ", reg_adr, phy_read(reg_adr));
+
+ if ((PHY_ADR % 4) == 3)
+ PRINT(OUT_OBJ "\n");
+ }
+ PHY_ADR = PHY_ADR_org;
+}
+
+
+//------------------------------------------------------------
+void phy_delay (int dt) {
+ DELAY( dt );
+}
+
+//------------------------------------------------------------
+// PHY IC
+//------------------------------------------------------------
+void phy_basic_setting (int loop_phy) {
+ phy_Read_Write(0, 0x7140, PHY_00h); //clr set
+ if ( DbgPrn_PHYRW )
+ printf ("[Set]00: %04lx\n", phy_read( PHY_REG_BMCR ));
+}
+
+//------------------------------------------------------------
+void phy_Wait_Reset_Done (void) {
+ int timeout = 0;
+
+ while ( phy_read( PHY_REG_BMCR ) & 0x8000 ) {
+ if (DbgPrn_PHYRW)
+ printf ("00: %04lx\n", phy_read( PHY_REG_BMCR ));
+
+ if (++timeout > TIME_OUT_PHY_Rst) {
+#ifdef SLT_DOS
+ if (!BurstEnable) fprintf(fp_log, "[PHY-Reset] Time out: %08lx\n", ReadSOC_DD(MAC_PHYBASE+0x60));
+#endif
+ FindErr(Err_PHY_TimeOut);
+ break;
+ }
+ }//wait Rst Done
+
+ if (DbgPrn_PHYRW) printf ("[Clr]00: %04lx\n", phy_read( PHY_REG_BMCR ));
+ DELAY(Delay_PHYRst);
+}
+
+//------------------------------------------------------------
+void phy_Reset (int loop_phy) {
+ phy_basic_setting(loop_phy);
+
+ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
+ phy_Wait_Reset_Done();
+
+ phy_basic_setting(loop_phy);
+ DELAY(Delay_PHYRst);
+}
+
+//------------------------------------------------------------
+void recov_phy_marvell (int loop_phy) {//88E1111
+ if ( BurstEnable ) {
+ }
+ else if ( loop_phy ) {
+ }
+ else {
+ if (GSpeed_sel[0]) {
+ phy_write(9, PHY_09h);
+
+ phy_Reset(loop_phy);
+
+ phy_write(29, 0x0007);
+ phy_Read_Write(30, 0x0008, 0x0000);//clr set
+ phy_write(29, 0x0010);
+ phy_Read_Write(30, 0x0002, 0x0000);//clr set
+ phy_write(29, 0x0012);
+ phy_Read_Write(30, 0x0001, 0x0000);//clr set
+
+ phy_write(18, PHY_12h);
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_marvell (int loop_phy) {//88E1111
+ int Retry;
+
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ if ( BurstEnable ) {
+ phy_Reset(loop_phy);
+ }
+ else if ( loop_phy ) {
+ phy_Reset(loop_phy);
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ PHY_09h = phy_read( PHY_GBCR );
+ PHY_12h = phy_read( PHY_INER );
+ phy_write ( 18, 0x0000 );
+ phy_Read_Write( 9, 0x0000, 0x1800 );//clr set
+ }
+
+ phy_Reset(loop_phy);
+
+ if (GSpeed_sel[0]) {
+ phy_write ( 29, 0x0007 );
+ phy_Read_Write( 30, 0x0000, 0x0008 );//clr set
+ phy_write ( 29, 0x0010 );
+ phy_Read_Write( 30, 0x0000, 0x0002 );//clr set
+ phy_write ( 29, 0x0012 );
+ phy_Read_Write( 30, 0x0000, 0x0001 );//clr set
+ }
+ }
+
+ Retry = 0;
+ do {
+ PHY_11h = phy_read( PHY_SR );
+ } while ( !( ( PHY_11h & 0x0400 ) | loop_phy | ( Retry++ > 20 ) ) );
+}
+
+//------------------------------------------------------------
+void recov_phy_marvell0 (int loop_phy) {//88E1310
+ if (BurstEnable) {
+ } else if (loop_phy) {
+ } else {
+ if (GSpeed_sel[0]) {
+ phy_write(22, 0x0006);
+ phy_Read_Write(16, 0x0020, 0x0000);//clr set
+ phy_write(22, 0x0000);
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_marvell0 (int loop_phy) {//88E1310
+ int Retry;
+
+ if (DbgPrn_PHYName)
+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_write( 22, 0x0002 );
+
+ PHY_15h = phy_read(21);
+ if (PHY_15h & 0x0030) {
+ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
+#ifdef SLT_DOS
+ if ( IOTiming )
+ fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
+ if ( !BurstEnable)
+ fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04lx]\n\n", PHY_15h);
+#endif
+// phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
+ phy_write(21, PHY_15h & 0xffcf); // Set [5]Rx Dly, [4]Tx Dly to 0
+ }
+ phy_write(22, 0x0000);
+
+ if ( BurstEnable ) {
+ phy_Reset(loop_phy);
+ }
+ else if ( loop_phy ) {
+ phy_write( 22, 0x0002 );
+
+ if ( GSpeed_sel[0] ) {
+ phy_Read_Write( 21, 0x6040, 0x0040 );//clr set
+ }
+ else if ( GSpeed_sel[1] ) {
+ phy_Read_Write( 21, 0x6040, 0x2000 );//clr set
+ }
+ else {
+ phy_Read_Write( 21, 0x6040, 0x0000 );//clr set
+ }
+ phy_write( 22, 0x0000 );
+ phy_Reset( loop_phy );
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 22, 0x0006 );
+ phy_Read_Write( 16, 0x0000, 0x0020 );//clr set
+ phy_write( 22, 0x0000 );
+ }
+
+ phy_Reset(loop_phy);
+ }
+
+ Retry = 0;
+ do {
+ PHY_11h = phy_read( PHY_SR );
+ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
+}
+
+//------------------------------------------------------------
+void recov_phy_marvell1 (int loop_phy) {//88E6176
+ CHAR PHY_ADR_org;
+
+ PHY_ADR_org = PHY_ADR;
+ for ( PHY_ADR = 16; PHY_ADR <= 22; PHY_ADR++ ) {
+ if ( BurstEnable ) {
+ }
+ else {
+ phy_write(6, PHY_06hA[PHY_ADR-16]);//06h[5]P5 loopback, 06h[6]P6 loopback
+ }
+ }
+ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
+ phy_write(1, 0x3); //01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+ }
+ PHY_ADR = PHY_ADR_org;
+}
+
+//------------------------------------------------------------
+void phy_marvell1 (int loop_phy) {//88E6176
+// ULONG PHY_01h;
+ CHAR PHY_ADR_org;
+
+ if (DbgPrn_PHYName)
+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ //The 88E6176 is switch with 7 Port(P0~P6) and the PHYAdr will be fixed at 0x10~0x16, and only P5/P6 can be connected to the MAC.
+ //Therefor, the 88E6176 only can run the internal loopback.
+ PHY_ADR_org = PHY_ADR;
+ for ( PHY_ADR = 16; PHY_ADR <= 20; PHY_ADR++ ) {
+ if ( BurstEnable ) {
+ }
+ else {
+ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
+ phy_write(6, 0x00);//06h[5]P5 loopback, 06h[6]P6 loopback
+ }
+ }
+
+ for ( PHY_ADR = 21; PHY_ADR <= 22; PHY_ADR++ ) {
+// PHY_01h = phy_read( PHY_REG_BMSR );
+// if (GSpeed_sel[0]) phy_write(1, (PHY_01h & 0xfffc) | 0x2);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+// else if (GSpeed_sel[1]) phy_write(1, (PHY_01h & 0xfffc) | 0x1);//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+// else phy_write(1, (PHY_01h & 0xfffc) );//[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+ if (GSpeed_sel[0]) phy_write(1, 0x2);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+ else if (GSpeed_sel[1]) phy_write(1, 0x1);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+ else phy_write(1, 0x0);//01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is not forced.
+
+ if (BurstEnable) {
+ }
+ else {
+ PHY_06hA[PHY_ADR-16] = phy_read( PHY_ANER );
+ if (PHY_ADR == 21) phy_write(6, 0x20);//06h[5]P5 loopback, 06h[6]P6 loopback
+ else phy_write(6, 0x40);//06h[5]P5 loopback, 06h[6]P6 loopback
+ }
+ }
+ PHY_ADR = PHY_ADR_org;
+}
+
+//------------------------------------------------------------
+void recov_phy_marvell2 (int loop_phy) {//88E1512
+ if (BurstEnable) {
+ }
+ else if (loop_phy) {
+ }
+ else {
+ if (GSpeed_sel[0]) {
+ phy_write(22, 0x0006);
+ phy_Read_Write(18, 0x0008, 0x0000);//clr set
+ phy_write(22, 0x0000);
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_marvell2 (int loop_phy) {//88E1512
+ int Retry = 0;
+ ULONG temp_reg;
+
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Marvell] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_write(22, 0x0002);
+ PHY_15h = phy_read(21);
+
+ if ( PHY_15h & 0x0030 ) {
+ printf ("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
+#ifdef SLT_DOS
+ if (IOTiming ) fprintf (fp_io, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
+ if (!BurstEnable) fprintf (fp_log, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15h_2:%04lx]\n\n", PHY_15h);
+#endif
+ // phy_Read_Write(21, 0x0030, 0x0000);//clr set//[5]Rx Dly, [4]Tx Dly
+// phy_write(21, PHY_15h & 0xffcf);
+ }
+ phy_write(22, 0x0000);
+
+ if ( BurstEnable ) {
+ phy_Reset(loop_phy);
+ }
+ else if (loop_phy) {
+ // Internal loopback funciton only support in copper mode
+ // switch page 18
+ phy_write(22, 0x0012);
+ // Change mode to Copper mode
+ phy_write(20, 0x8210);
+ // do software reset
+ do {
+ temp_reg = phy_read( 20 );
+ } while ( ( (temp_reg & 0x8000) == 0x8000 ) & (Retry++ < 20) );
+
+ // switch page 2
+ phy_write(22, 0x0002);
+ if (GSpeed_sel[0]) {
+ phy_Read_Write(21, 0x2040, 0x0040);//clr set
+ }
+ else if (GSpeed_sel[1]) {
+ phy_Read_Write(21, 0x2040, 0x2000);//clr set
+ }
+ else {
+ phy_Read_Write(21, 0x2040, 0x0000);//clr set
+ }
+ phy_write(22, 0x0000);
+
+ phy_Reset(loop_phy);
+ }
+ else {
+ if (GSpeed_sel[0]) {
+ phy_write(22, 0x0006);
+ phy_Read_Write(18, 0x0000, 0x0008);//clr set
+ phy_write(22, 0x0000);
+ }
+
+ phy_Reset(loop_phy);
+ }
+
+ Retry = 0;
+ do {
+ PHY_11h = phy_read( PHY_SR );
+ } while (!((PHY_11h & 0x0400) | loop_phy | (Retry++ > 20)));
+}
+
+//------------------------------------------------------------
+void phy_broadcom (int loop_phy) {//BCM5221
+ if (DbgPrn_PHYName)
+ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+
+ if (IEEETesting) {
+ if (IOTimingBund_arg == 0) {
+ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
+ }
+ else {
+ phy_Read_Write(24, 0x0000, 0x4000);//clr set//Force Link
+// phy_write( 0, PHY_00h);
+// phy_write(30, 0x1000);
+ }
+ }
+}
+
+//------------------------------------------------------------
+void recov_phy_broadcom0 (int loop_phy) {//BCM54612
+
+ // Need to do it for AST2400
+ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
+ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
+
+ if (BurstEnable) {
+ }
+ else if (loop_phy) {
+ phy_write( 0, PHY_00h);
+ }
+ else {
+ phy_write(0x00, PHY_00h);
+ phy_write(0x09, PHY_09h);
+ phy_write(0x18, PHY_18h);
+ }
+}
+
+//------------------------------------------------------------
+void phy_broadcom0 (int loop_phy) {//BCM54612
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Broadcom] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ // Need to do it for AST2400
+ phy_write(0x1C, 0x8C00); // Disable GTXCLK Clock Delay Enable
+ phy_write(0x18, 0xF0E7); // Disable RGMII RXD to RXC Skew
+
+ // Backup org value
+ // read reg 18H, Page 103, BCM54612EB1KMLG_Spec.pdf
+ phy_write(0x18, 0x7007);
+ PHY_18h = phy_read(0x18);
+
+ PHY_00h = phy_read( PHY_REG_BMCR );
+ PHY_09h = phy_read( PHY_GBCR );
+
+ if ( BurstEnable ) {
+ phy_basic_setting(loop_phy);
+ }
+ else if (loop_phy) {
+ phy_basic_setting(loop_phy);
+
+ // Enable Internal Loopback mode
+ // Page 58, BCM54612EB1KMLG_Spec.pdf
+ phy_write(0x0, 0x5140);
+ DELAY(Delay_PHYRst);
+ /* Only 1G Test is PASS, 100M and 10M is false @20130619 */
+
+// Waiting for BCM FAE's response
+// if (GSpeed_sel[0]) {
+// // Speed 1G
+// // Enable Internal Loopback mode
+// // Page 58, BCM54612EB1KMLG_Spec.pdf
+// phy_write(0x0, 0x5140);
+// }
+// else if (GSpeed_sel[1]) {
+// // Speed 100M
+// // Enable Internal Loopback mode
+// // Page 58, BCM54612EB1KMLG_Spec.pdf
+// phy_write(0x0, 0x7100);
+// phy_write(0x1E, 0x1000);
+// }
+// else if (GSpeed_sel[2]) {
+// // Speed 10M
+// // Enable Internal Loopback mode
+// // Page 58, BCM54612EB1KMLG_Spec.pdf
+// phy_write(0x0, 0x5100);
+// phy_write(0x1E, 0x1000);
+// }
+//
+// DELAY(Delay_PHYRst);
+ }
+ else {
+
+ if (GSpeed_sel[0]) {
+ // Page 60, BCM54612EB1KMLG_Spec.pdf
+ // need to insert loopback plug
+ phy_write( 9, 0x1800);
+ phy_write( 0, 0x0140);
+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
+ } else if (GSpeed_sel[1]) {
+ // Page 60, BCM54612EB1KMLG_Spec.pdf
+ // need to insert loopback plug
+ phy_write( 0, 0x2100);
+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
+ } else {
+ // Page 60, BCM54612EB1KMLG_Spec.pdf
+ // need to insert loopback plug
+ phy_write( 0, 0x0100);
+ phy_write( 0x18, 0x8400); // Enable Transmit test mode
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_realtek (int loop_phy) {//RTL8201N
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+}
+
+//------------------------------------------------------------
+//internal loop 100M: Don't support
+//internal loop 10M : no loopback stub
+void phy_realtek0 (int loop_phy) {//RTL8201E
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+
+// phy_Read_Write(25, 0x2800, 0x0000);//clr set
+// printf("Enable phy output RMII clock\n");
+ if (IEEETesting) {
+ phy_write(31, 0x0001);
+ if (IOTimingBund_arg == 0) {
+ phy_write(25, 0x1f01);//Force MDI //Measuring from channel A
+ }
+ else {
+ phy_write(25, 0x1f00);//Force MDIX //Measuring from channel B
+ }
+ phy_write(31, 0x0000);
+ }
+}
+
+//------------------------------------------------------------
+void recov_phy_realtek1 (int loop_phy) {//RTL8211D
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ if ( GSpeed_sel[0] ) {
+ if (IOTimingBund_arg == 0) {
+ //Test Mode 1
+ phy_write( 31, 0x0002 );
+ phy_write( 2, 0xc203 );
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x0000 );
+ }
+ else {
+ //Test Mode 4
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x0000 );
+ }
+
+ phy_write( 31, 0x0000 );
+ }
+ else if ( GSpeed_sel[1] ) {
+ phy_write( 23, 0x2100 );
+ phy_write( 16, 0x016e );
+ }
+ else {
+// phy_write( 31, 0x0006 );
+// phy_write( 0, 0x5a00 );
+// phy_write( 31, 0x0000 );
+ }
+ } // End if ( IEEETesting )
+ }
+ else if (loop_phy) {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0000 ); // new in Rev. 1.6
+ phy_write( 0, 0x1140 ); // new in Rev. 1.6
+ phy_write( 20, 0x8040 ); // new in Rev. 1.6
+ }
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0001 );
+ phy_write( 3, 0xdf41 );
+ phy_write( 2, 0xdf20 );
+ phy_write( 1, 0x0140 );
+ phy_write( 0, 0x00bb );
+ phy_write( 4, 0xb800 );
+ phy_write( 4, 0xb000 );
+
+ phy_write( 31, 0x0000 );
+// phy_write( 26, 0x0020 ); // Rev. 1.2
+ phy_write( 26, 0x0040 ); // new in Rev. 1.6
+ phy_write( 0, 0x1140 );
+// phy_write( 21, 0x0006 ); // Rev. 1.2
+ phy_write( 21, 0x1006 ); // new in Rev. 1.6
+ phy_write( 23, 0x2100 );
+// } else if ( GSpeed_sel[1] ) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0200 );
+// phy_write( 0, 0x1200 );
+// } else if ( GSpeed_sel[2] ) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0200 );
+// phy_write( 4, 0x05e1 );
+// phy_write( 0, 0x1200 );
+ }
+ } // End if ( BurstEnable )
+} // End void recov_phy_realtek1 (int loop_phy)
+
+//------------------------------------------------------------
+//internal loop 1G : no loopback stub
+//internal loop 100M: no loopback stub
+//internal loop 10M : no loopback stub
+void phy_realtek1 (int loop_phy) {//RTL8211D
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ if ( GSpeed_sel[0] ) {
+ if (IOTimingBund_arg == 0) {
+ //Test Mode 1
+ phy_write( 31, 0x0002 );
+ phy_write( 2, 0xc22b );
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x2000 );
+ }
+ else {
+ //Test Mode 4
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x8000 );
+ }
+ phy_write( 31, 0x0000 );
+ }
+ else if ( GSpeed_sel[1] ) {
+ if ( IOTimingBund_arg == 0 ) {
+ //From Channel A
+ phy_write( 23, 0xa102 );
+ phy_write( 16, 0x01ae );//MDI
+ }
+ else {
+ //From Channel B
+ phy_Read_Write( 17, 0x0008, 0x0000 ); // clr set
+ phy_write( 23, 0xa102 ); // MDI
+ phy_write( 16, 0x010e );
+ }
+ } else {
+// if ( IOTimingBund_arg == 0 ) {//Pseudo-random pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 0, 0x5a21 );
+// phy_write( 31, 0x0000 );
+// }
+// else if ( IOTimingBund_arg == 1 ) {//¡§FF¡¨ pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 2, 0x05ee );
+// phy_write( 0, 0xff21 );
+// phy_write( 31, 0x0000 );
+// } else {//¡§00¡¨ pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 2, 0x05ee );
+// phy_write( 0, 0x0021 );
+// phy_write( 31, 0x0000 );
+// }
+ }
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+ else if ( loop_phy ) {
+ phy_Reset(loop_phy);
+
+ if ( GSpeed_sel[0] ) {
+ phy_write(20, 0x0042);//new in Rev. 1.6
+ }
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0001 );
+ phy_write( 3, 0xff41 );
+ phy_write( 2, 0xd720 );
+ phy_write( 1, 0x0140 );
+ phy_write( 0, 0x00bb );
+ phy_write( 4, 0xb800 );
+ phy_write( 4, 0xb000 );
+
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x0040 );
+ phy_write( 24, 0x0008 );
+
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x0300 );
+ phy_write( 26, 0x0020 );
+ phy_write( 0, 0x0140 );
+ phy_write( 23, 0xa101 );
+ phy_write( 21, 0x0200 );
+ phy_write( 23, 0xa121 );
+ phy_write( 23, 0xa161 );
+ phy_write( 0, 0x8000 );
+ phy_Wait_Reset_Done();
+ phy_delay(200); // new in Rev. 1.6
+// }
+// else if ( GSpeed_sel[1] ) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0000 );
+// phy_write( 4, 0x0061 );
+// phy_write( 0, 0x1200 );
+// phy_delay(5000);
+// }
+// else if (GSpeed_sel[2]) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0000 );
+// phy_write( 4, 0x05e1 );
+// phy_write( 0, 0x1200 );
+// phy_delay(5000);
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+} // End void phy_realtek1 (int loop_phy)
+
+//------------------------------------------------------------
+void recov_phy_realtek2 (int loop_phy) {//RTL8211E
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ phy_write( 31, 0x0005 );
+ phy_write( 5, 0x8b86 );
+ phy_write( 6, 0xe201 );
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x0020 );
+ phy_write( 21, 0x1108 );
+ phy_write( 31, 0x0000 );
+
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0000 );
+ phy_write( 9, 0x0000 );
+ }
+ else if ( GSpeed_sel[1] ) {
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x002f );
+ phy_write( 23, 0xd88f );
+ phy_write( 30, 0x002d );
+ phy_write( 24, 0xf050 );
+ phy_write( 31, 0x0000 );
+ phy_write( 16, 0x006e );
+ }
+ else {
+ }
+ }
+ else {
+ }
+ }
+ else if (loop_phy) {
+ }
+ else {
+ if (GSpeed_sel[0]) {
+ //Rev 1.5 //not stable
+// phy_write( 31, 0x0000 );
+// phy_write( 0, 0x8000 );
+// phy_Wait_Reset_Done();
+// phy_delay(30);
+// phy_write( 23, 0x2160 );
+// phy_write( 31, 0x0007 );
+// phy_write( 30, 0x0040 );
+// phy_write( 24, 0x0004 );
+// phy_write( 24, 0x1a24 );
+// phy_write( 25, 0xfd00 );
+// phy_write( 24, 0x0000 );
+// phy_write( 31, 0x0000 );
+// phy_write( 0, 0x1140 );
+// phy_write( 26, 0x0040 );
+// phy_write( 31, 0x0007 );
+// phy_write( 30, 0x002f );
+// phy_write( 23, 0xd88f );
+// phy_write( 30, 0x0023 );
+// phy_write( 22, 0x0300 );
+// phy_write( 31, 0x0000 );
+// phy_write( 21, 0x1006 );
+// phy_write( 23, 0x2100 );
+/**/
+ //Rev 1.6
+ phy_write( 31, 0x0000 );
+ phy_write( 0, 0x8000 );
+ phy_Wait_Reset_Done();
+ phy_delay(30);
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x0042 );
+ phy_write( 21, 0x0500 );
+ phy_write( 31, 0x0000 );
+ phy_write( 0, 0x1140 );
+ phy_write( 26, 0x0040 );
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x002f );
+ phy_write( 23, 0xd88f );
+ phy_write( 30, 0x0023 );
+ phy_write( 22, 0x0300 );
+ phy_write( 31, 0x0000 );
+ phy_write( 21, 0x1006 );
+ phy_write( 23, 0x2100 );
+/**/
+// } else if (GSpeed_sel[1]) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0200 );
+// phy_write( 0, 0x1200 );
+// } else if (GSpeed_sel[2]) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0200 );
+// phy_write( 4, 0x05e1 );
+// phy_write( 0, 0x1200 );
+ }
+ }
+} // End void recov_phy_realtek2 (int loop_phy)
+
+//------------------------------------------------------------
+//internal loop 1G : no loopback stub
+//internal loop 100M: no loopback stub
+//internal loop 10M : no loopback stub
+void phy_realtek2 (int loop_phy) {//RTL8211E
+
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h ); // clr set // Rst PHY
+ phy_Wait_Reset_Done();
+ phy_delay(30);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ phy_write( 31, 0x0005 );
+ phy_write( 5, 0x8b86 );
+ phy_write( 6, 0xe200 );
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x0020 );
+ phy_write( 21, 0x0108 );
+ phy_write( 31, 0x0000 );
+
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0000 );
+
+ if ( IOTimingBund_arg == 0 ) {
+ phy_write( 9, 0x2000);//Test Mode 1
+ }
+ else {
+ phy_write( 9, 0x8000);//Test Mode 4
+ }
+ }
+ else if ( GSpeed_sel[1] ) {
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x002f );
+ phy_write( 23, 0xd818 );
+ phy_write( 30, 0x002d );
+ phy_write( 24, 0xf060 );
+ phy_write( 31, 0x0000 );
+
+ if ( IOTimingBund_arg == 0 ) {
+ phy_write(16, 0x00ae);//From Channel A
+ }
+ else {
+ phy_write(16, 0x008e);//From Channel B
+ }
+ }
+ else {
+ }
+ }
+ else {
+ phy_basic_setting(loop_phy);
+ phy_delay(30);
+ }
+ }
+ else if (loop_phy) {
+ phy_basic_setting(loop_phy);
+
+ phy_Read_Write(0, 0x0000, 0x8000 | PHY_00h);//clr set//Rst PHY
+ phy_Wait_Reset_Done();
+ phy_delay(30);
+
+ phy_basic_setting(loop_phy);
+ phy_delay(30);
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ //Rev 1.5 //not stable
+// phy_write( 23, 0x2160 );
+// phy_write( 31, 0x0007 );
+// phy_write( 30, 0x0040 );
+// phy_write( 24, 0x0004 );
+// phy_write( 24, 0x1a24 );
+// phy_write( 25, 0x7d00 );
+// phy_write( 31, 0x0000 );
+// phy_write( 23, 0x2100 );
+// phy_write( 31, 0x0007 );
+// phy_write( 30, 0x0040 );
+// phy_write( 24, 0x0000 );
+// phy_write( 30, 0x0023 );
+// phy_write( 22, 0x0006 );
+// phy_write( 31, 0x0000 );
+// phy_write( 0, 0x0140 );
+// phy_write( 26, 0x0060 );
+// phy_write( 31, 0x0007 );
+// phy_write( 30, 0x002f );
+// phy_write( 23, 0xd820 );
+// phy_write( 31, 0x0000 );
+// phy_write( 21, 0x0206 );
+// phy_write( 23, 0x2120 );
+// phy_write( 23, 0x2160 );
+/**/
+ //Rev 1.6
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x0042 );
+ phy_write( 21, 0x2500 );
+ phy_write( 30, 0x0023 );
+ phy_write( 22, 0x0006 );
+ phy_write( 31, 0x0000 );
+ phy_write( 0, 0x0140 );
+ phy_write( 26, 0x0060 );
+ phy_write( 31, 0x0007 );
+ phy_write( 30, 0x002f );
+ phy_write( 23, 0xd820 );
+ phy_write( 31, 0x0000 );
+ phy_write( 21, 0x0206 );
+ phy_write( 23, 0x2120 );
+ phy_write( 23, 0x2160 );
+ phy_delay(300);
+/**/
+// }
+// else if ( GSpeed_sel[1] ) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0000 );
+// phy_write( 4, 0x0061 );
+// phy_write( 0, 0x1200 );
+// phy_delay(5000);
+// }
+// else if ( GSpeed_sel[2] ) {//option
+// phy_write( 31, 0x0000 );
+// phy_write( 9, 0x0000 );
+// phy_write( 4, 0x05e1 );
+// phy_write( 0, 0x1200 );
+// phy_delay(5000);
+ }
+ else {
+ phy_basic_setting(loop_phy);
+ phy_delay(150);
+ }
+ }
+} // End void phy_realtek2 (int loop_phy)
+
+//------------------------------------------------------------
+void recov_phy_realtek3 (int loop_phy) {//RTL8211C
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 9, 0x0000 );
+ }
+ else if ( GSpeed_sel[1] ) {
+ phy_write( 17, PHY_11h );
+ phy_write( 14, 0x0000 );
+ phy_write( 16, 0x00a0 );
+ }
+ else {
+// phy_write( 31, 0x0006 );
+// phy_write( 0, 0x5a00 );
+// phy_write( 31, 0x0000 );
+ }
+ }
+ else {
+ }
+ }
+ else if (loop_phy) {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 11, 0x0000 );
+ }
+ phy_write( 12, 0x1006 );
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 31, 0x0001 );
+ phy_write( 4, 0xb000 );
+ phy_write( 3, 0xff41 );
+ phy_write( 2, 0xdf20 );
+ phy_write( 1, 0x0140 );
+ phy_write( 0, 0x00bb );
+ phy_write( 4, 0xb800 );
+ phy_write( 4, 0xb000 );
+
+ phy_write( 31, 0x0000 );
+ phy_write( 25, 0x8c00 );
+ phy_write( 26, 0x0040 );
+ phy_write( 0, 0x1140 );
+ phy_write( 14, 0x0000 );
+ phy_write( 12, 0x1006 );
+ phy_write( 23, 0x2109 );
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_realtek3 (int loop_phy) {//RTL8211C
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ if ( GSpeed_sel[0] ) {
+ if ( IOTimingBund_arg == 0 ) { //Test Mode 1
+ phy_write( 9, 0x2000);
+ }
+ else if (IOTimingBund_arg == 1) {//Test Mode 2
+ phy_write( 9, 0x4000);
+ }
+ else if (IOTimingBund_arg == 2) {//Test Mode 3
+ phy_write( 9, 0x6000);
+ }
+ else { //Test Mode 4
+ phy_write( 9, 0x8000);
+ }
+ }
+ else if ( GSpeed_sel[1] ) {
+ PHY_11h = phy_read( PHY_SR );
+ phy_write( 17, PHY_11h & 0xfff7 );
+ phy_write( 14, 0x0660 );
+
+ if ( IOTimingBund_arg == 0 ) {
+ phy_write( 16, 0x00a0 );//MDI //From Channel A
+ }
+ else {
+ phy_write( 16, 0x0080 );//MDIX //From Channel B
+ }
+ }
+ else {
+// if (IOTimingBund_arg == 0) {//Pseudo-random pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 0, 0x5a21 );
+// phy_write( 31, 0x0000 );
+// }
+// else if (IOTimingBund_arg == 1) {//¡§FF¡¨ pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 2, 0x05ee );
+// phy_write( 0, 0xff21 );
+// phy_write( 31, 0x0000 );
+// }
+// else {//¡§00¡¨ pattern
+// phy_write( 31, 0x0006 );
+// phy_write( 2, 0x05ee );
+// phy_write( 0, 0x0021 );
+// phy_write( 31, 0x0000 );
+// }
+ }
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+ else if (loop_phy) {
+ phy_write( 0, 0x9200);
+ phy_Wait_Reset_Done();
+ phy_delay(30);
+
+ phy_write( 17, 0x401c );
+ phy_write( 12, 0x0006 );
+
+ if ( GSpeed_sel[0] ) {
+ phy_write(11, 0x0002);
+ }
+ else {
+ phy_basic_setting(loop_phy);
+ }
+ }
+ else {
+ if (GSpeed_sel[0]) {
+ phy_write( 31, 0x0001 );
+ phy_write( 4, 0xb000 );
+ phy_write( 3, 0xff41 );
+ phy_write( 2, 0xd720 );
+ phy_write( 1, 0x0140 );
+ phy_write( 0, 0x00bb );
+ phy_write( 4, 0xb800 );
+ phy_write( 4, 0xb000 );
+
+ phy_write( 31, 0x0000 );
+ phy_write( 25, 0x8400 );
+ phy_write( 26, 0x0020 );
+ phy_write( 0, 0x0140 );
+ phy_write( 14, 0x0210 );
+ phy_write( 12, 0x0200 );
+ phy_write( 23, 0x2109 );
+ phy_write( 23, 0x2139 );
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+} // End void phy_realtek3 (int loop_phy)
+
+//------------------------------------------------------------
+void phy_realtek4 (int loop_phy) {//RTL8201F
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Realtek] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ phy_write( 31, 0x0004 );
+ phy_write( 16, 0x4077 );
+ phy_write( 21, 0xc5a0 );
+ phy_write( 31, 0x0000 );
+
+ if ( GSpeed_sel[1] ) {
+ phy_write( 0, 0x8000 ); // Reset PHY
+ phy_write( 24, 0x0310 ); // Disable ALDPS
+
+ if ( IOTimingBund_arg == 0 ) {
+ phy_write( 28, 0x40c2 ); //Force MDI //From Channel A (RJ45 pair 1, 2)
+ }
+ else {
+ phy_write( 28, 0x40c0 ); //Force MDIX//From Channel B (RJ45 pair 3, 6)
+ }
+ phy_write( 0, 0x2100); //Force 100M/Full Duplex)
+ }
+ } else {
+ phy_Reset(loop_phy);
+ }
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+}
+
+//------------------------------------------------------------
+void phy_smsc (int loop_phy) {//LAN8700
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[SMSC] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+}
+
+//------------------------------------------------------------
+void phy_micrel (int loop_phy) {//KSZ8041
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+
+// phy_write(24, 0x0600);
+}
+
+//------------------------------------------------------------
+void phy_micrel0 (int loop_phy) {//KSZ8031/KSZ8051
+ if ( DbgPrn_PHYName ) printf ("--->(%04lx %04lx)[Micrel] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ //For KSZ8051RNL only
+ //Reg1Fh[7] = 0(default): 25MHz Mode, XI, XO(pin 9, 8) is 25MHz(crystal/oscilator).
+ //Reg1Fh[7] = 1 : 50MHz Mode, XI(pin 9) is 50MHz(oscilator).
+ PHY_1fh = phy_read(31);
+ if (PHY_1fh & 0x0080) sprintf(PHYName, "%s-50MHz Mode", PHYName);
+ else sprintf(PHYName, "%s-25MHz Mode", PHYName);
+
+ if (IEEETesting) {
+ phy_Read_Write( 0, 0x0000, 0x8000 | PHY_00h );//clr set//Rst PHY
+ phy_Wait_Reset_Done();
+
+ phy_Read_Write( 31, 0x0000, 0x2000 );//clr set//1Fh[13] = 1: Disable auto MDI/MDI-X
+ phy_basic_setting(loop_phy);
+ phy_Read_Write( 31, 0x0000, 0x0800 );//clr set//1Fh[11] = 1: Force link pass
+
+// phy_delay(2500);//2.5 sec
+ }
+ else {
+ phy_Reset(loop_phy);
+
+ //Reg16h[6] = 1 : RMII B-to-B override
+ //Reg16h[1] = 1(default): RMII override
+ phy_Read_Write( 22, 0x0000, 0x0042 );//clr set
+ }
+
+ if ( PHY_1fh & 0x0080 )
+ phy_Read_Write( 31, 0x0000, 0x0080 );//clr set//Reset PHY will clear Reg1Fh[7]
+}
+
+//------------------------------------------------------------
+void recov_phy_vitesse (int loop_phy) {//VSC8601
+ if ( BurstEnable ) {
+// if (IEEETesting) {
+// } else {
+// }
+ }
+ else if ( loop_phy ) {
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ phy_write( 24, PHY_18h );
+ phy_write( 18, PHY_12h );
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_vitesse (int loop_phy) {//VSC8601
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)[VITESSE] %s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ if ( BurstEnable ) {
+ if ( IEEETesting ) {
+ phy_Reset(loop_phy);
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+ else if ( loop_phy ) {
+ phy_Reset(loop_phy);
+ }
+ else {
+ if ( GSpeed_sel[0] ) {
+ PHY_18h = phy_read( 24 );
+ PHY_12h = phy_read( PHY_INER );
+
+ phy_Reset(loop_phy);
+
+ phy_write( 24, PHY_18h | 0x0001 );
+ phy_write( 18, PHY_12h | 0x0020 );
+ }
+ else {
+ phy_Reset(loop_phy);
+ }
+ }
+}
+
+//------------------------------------------------------------
+void phy_default (int loop_phy) {
+ if ( DbgPrn_PHYName )
+ printf ("--->(%04lx %04lx)%s\n", PHY_ID2, PHY_ID3, PHYName);
+
+ phy_Reset(loop_phy);
+}
+
+//------------------------------------------------------------
+// PHY Init
+//------------------------------------------------------------
+BOOLEAN find_phyadr (void) {
+ ULONG PHY_val;
+ BOOLEAN ret = FALSE;
+
+ #ifdef DbgPrn_FuncHeader
+ printf ("find_phyadr\n");
+ Debug_delay();
+ #endif
+
+ do {
+ // Check current PHY address by user setting
+ PHY_val = phy_read( PHY_REG_ID_1 );
+ if ( PHY_IS_VALID(PHY_val) ) {
+ ret = TRUE;
+ break;
+ }
+
+ if ( Enable_SkipChkPHY ) {
+ PHY_val = phy_read( PHY_REG_BMCR );
+
+ if ((PHY_val & 0x8000) & Enable_InitPHY) {
+ // PHY is reseting and need to inital PHY
+ #ifndef Enable_SearchPHYID
+ break;
+ #endif
+ }
+ else {
+ ret = TRUE;
+ break;
+ }
+ }
+
+ #ifdef Enable_SearchPHYID
+ // Scan PHY address from 0 to 31
+ printf("Search PHY address\n");
+ for ( PHY_ADR = 0; PHY_ADR < 32; PHY_ADR++ ) {
+ PHY_val = phy_read( PHY_REG_ID_1 );
+ if ( PHY_IS_VALID(PHY_val) ) {
+ ret = TRUE;
+ break;
+ }
+ }
+ // Don't find PHY address
+ PHY_ADR = PHY_ADR_arg;
+ #endif
+ } while ( 0 );
+
+ if ( ret == TRUE ) {
+ if ( PHY_ADR_arg != PHY_ADR ) {
+
+ if ( !BurstEnable )
+ phy_id( FP_LOG );
+
+ phy_id( STD_OUT );
+ }
+ }
+ else {
+
+ if ( !BurstEnable )
+ phy_id( FP_LOG );
+
+ phy_id( STD_OUT );
+ FindErr( Err_PHY_Type );
+ }
+
+ return ret;
+} // End BOOLEAN find_phyadr (void)
+
+//------------------------------------------------------------
+char phy_chk (ULONG id2, ULONG id3, ULONG id3_mask) {
+ if ((PHY_ID2 == id2) && ((PHY_ID3 & id3_mask) == (id3 & id3_mask)))
+ return(1);
+ else
+ return(0);
+}
+
+//------------------------------------------------------------
+void phy_set00h (int loop_phy) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("phy_set00h\n");
+ Debug_delay();
+ #endif
+
+ if (BurstEnable) {
+ if (IEEETesting) {
+ if (GSpeed_sel[0]) PHY_00h = 0x0140;
+ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
+ else PHY_00h = 0x0100;
+ }
+ else {
+ if (GSpeed_sel[0]) PHY_00h = 0x1140;
+ else if (GSpeed_sel[1]) PHY_00h = 0x3100;
+ else PHY_00h = 0x1100;
+ }
+ }
+ else if (loop_phy) {
+ if (GSpeed_sel[0]) PHY_00h = 0x4140;
+ else if (GSpeed_sel[1]) PHY_00h = 0x6100;
+ else PHY_00h = 0x4100;
+ }
+ else {
+ if (GSpeed_sel[0]) PHY_00h = 0x0140;
+ else if (GSpeed_sel[1]) PHY_00h = 0x2100;
+ else PHY_00h = 0x0100;
+ }
+}
+
+//------------------------------------------------------------
+void phy_sel (int loop_phy) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("phy_sel\n");
+ Debug_delay();
+ #endif
+
+ PHY_ID2 = phy_read( PHY_REG_ID_1 );
+ PHY_ID3 = phy_read( PHY_REG_ID_2 );
+ phy_set00h(loop_phy);
+
+ if ((PHY_ID2 == 0xffff) && (PHY_ID3 == 0xffff) && !Enable_SkipChkPHY) {
+ sprintf(PHYName, "--");
+ FindErr(Err_PHY_Type);
+ }
+#ifdef Enable_CheckZeroPHYID
+ else if ((PHY_ID2 == 0x0000) && (PHY_ID3 == 0x0000) && !Enable_SkipChkPHY) {
+ sprintf(PHYName, "--"); FindErr(Err_PHY_Type);
+ }
+#endif
+
+ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) {sprintf(PHYName, "BCM54612" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54612 1G/100/10M RGMII
+ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) {sprintf(PHYName, "BCM54616S" ); if (Enable_InitPHY) phy_broadcom0(loop_phy);}//BCM54616A 1G/100/10M RGMII
+ else if (phy_chk(0x0040, 0x61e0, PHYID3_Mask)) {sprintf(PHYName, "BCM5221" ); if (Enable_InitPHY) phy_broadcom (loop_phy);}//BCM5221 100/10M MII, RMII
+ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) {sprintf(PHYName, "88E1512" ); if (Enable_InitPHY) phy_marvell2 (loop_phy);}//88E1512 1G/100/10M RGMII
+ else if (phy_chk(0xff00, 0x1761, 0xffff )) {sprintf(PHYName, "88E6176(IntLoop)"); if (Enable_InitPHY) phy_marvell1 (loop_phy);}//88E6176 1G/100/10M 2 RGMII Switch
+ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) {sprintf(PHYName, "88E1310" ); if (Enable_InitPHY) phy_marvell0 (loop_phy);}//88E1310 1G/100/10M RGMII
+ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) {sprintf(PHYName, "88E1111" ); if (Enable_InitPHY) phy_marvell (loop_phy);}//88E1111 1G/100/10M GMII, MII, RGMII
+ else if (phy_chk(0x001c, 0xc816, 0xffff )) {sprintf(PHYName, "RTL8201F" ); if (Enable_InitPHY) phy_realtek4 (loop_phy);}//RTL8201F 100/10M MII, RMII
+ else if (phy_chk(0x001c, 0xc815, 0xfff0 )) {sprintf(PHYName, "RTL8201E" ); if (Enable_InitPHY) phy_realtek0 (loop_phy);}//RTL8201E 100/10M MII, RMII(RTL8201E(L)-VC only)
+ else if (phy_chk(0x001c, 0xc912, 0xffff )) {sprintf(PHYName, "RTL8211C" ); if (Enable_InitPHY) phy_realtek3 (loop_phy);}//RTL8211C 1G/100/10M RGMII
+ else if (phy_chk(0x001c, 0xc914, 0xffff )) {sprintf(PHYName, "RTL8211D" ); if (Enable_InitPHY) phy_realtek1 (loop_phy);}//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
+ else if (phy_chk(0x001c, 0xc915, 0xffff )) {sprintf(PHYName, "RTL8211E" ); if (Enable_InitPHY) phy_realtek2 (loop_phy);}//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
+ else if (phy_chk(0x0000, 0x8201, PHYID3_Mask)) {sprintf(PHYName, "RTL8201N" ); if (Enable_InitPHY) phy_realtek (loop_phy);}//RTL8201N 100/10M MII, RMII
+ else if (phy_chk(0x0007, 0xc0c4, PHYID3_Mask)) {sprintf(PHYName, "LAN8700" ); if (Enable_InitPHY) phy_smsc (loop_phy);}//LAN8700 100/10M MII, RMII
+ else if (phy_chk(0x0022, 0x1555, 0xfff0 )) {sprintf(PHYName, "KSZ8031/KSZ8051" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8051/KSZ8031 100/10M RMII
+ else if (phy_chk(0x0022, 0x1560, 0xfff0 )) {sprintf(PHYName, "KSZ8081" ); if (Enable_InitPHY) phy_micrel0 (loop_phy);}//KSZ8081 100/10M RMII
+ else if (phy_chk(0x0022, 0x1512, 0xfff0 )) {sprintf(PHYName, "KSZ8041" ); if (Enable_InitPHY) phy_micrel (loop_phy);}//KSZ8041 100/10M RMII
+ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) {sprintf(PHYName, "VSC8601" ); if (Enable_InitPHY) phy_vitesse (loop_phy);}//VSC8601 1G/100/10M RGMII
+ else {sprintf(PHYName, "default" ); if (Enable_InitPHY) phy_default (loop_phy);}//
+}
+
+//------------------------------------------------------------
+void recov_phy (int loop_phy) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("recov_phy\n");
+ Debug_delay();
+ #endif
+
+ if (phy_chk(0x0362, 0x5e6a, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54612 1G/100/10M RGMII
+ else if (phy_chk(0x0362, 0x5d10, 0xfff0 )) recov_phy_broadcom0(loop_phy);//BCM54616A 1G/100/10M RGMII
+ else if (phy_chk(0x0141, 0x0dd0, 0xfff0 )) recov_phy_marvell2 (loop_phy);//88E1512 1G/100/10M RGMII
+ else if (phy_chk(0xff00, 0x1761, 0xffff )) recov_phy_marvell1 (loop_phy);//88E6176 1G/100/10M 2 RGMII Switch
+ else if (phy_chk(0x0141, 0x0e90, 0xfff0 )) recov_phy_marvell0 (loop_phy);//88E1310 1G/100/10M RGMII
+ else if (phy_chk(0x0141, 0x0cc0, PHYID3_Mask)) recov_phy_marvell (loop_phy);//88E1111 1G/100/10M GMII, MII, RGMII
+ else if (phy_chk(0x001c, 0xc914, 0xffff )) recov_phy_realtek1 (loop_phy);//RTL8211D 1G/100/10M GMII(RTL8211DN/RTL8211DG only), MII(RTL8211DN/RTL8211DG only), RGMII
+ else if (phy_chk(0x001c, 0xc915, 0xffff )) recov_phy_realtek2 (loop_phy);//RTL8211E 1G/100/10M GMII(RTL8211EG only), RGMII
+ else if (phy_chk(0x001c, 0xc912, 0xffff )) recov_phy_realtek3 (loop_phy);//RTL8211C 1G/100/10M RGMII
+ else if (phy_chk(0x0007, 0x0421, 0xfff0 )) recov_phy_vitesse (loop_phy);//VSC8601 1G/100/10M RGMII
+}
+
+//------------------------------------------------------------
+void init_phy (int loop_phy) {
+ #ifdef DbgPrn_FuncHeader
+ printf ("init_phy\n");
+ Debug_delay();
+ #endif
+
+ sprintf( PHYID, "PHY%d", SelectMAC + 1 );
+
+ if ( DbgPrn_PHYInit )
+ phy_dump( PHYID );
+
+ if ( find_phyadr() == TRUE )
+ phy_sel( loop_phy );
+
+ if ( DbgPrn_PHYInit )
+ phy_dump( PHYID );
+}
+
+
diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H new file mode 100644 index 0000000..6fa96e6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.H @@ -0,0 +1,50 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef PLLTESTU_H +#define PLLTESTU_H + +//PLL Mode Definition +#define NAND_PLLMODE 0x00 +#define DELAY_PLLMODE 0x04 +#define PCI_PLLMODE 0x08 +#define DPLL_PLLMODE 0x2c +#define MPLL_PLLMODE 0x10 +#define HPLL_PLLMODE 0x14 +#define LPC_PLLMODE 0x18 +#define VIDEOA_PLLMODE 0x1c +#define D2PLL_PLLMODE 0x0c +#define VIDEOB_PLLMODE 0x3c + +#define PCI_PLLMODE_AST1160 0x10 +#define MPLL_PLLMODE_AST1160 0x14 +#define HPLL_PLLMODE_AST1160 0x14 +#define DPLL_PLLMODE_AST1160 0x1c + +#define PCI_PLLMODE_AST2300 0x2c +#define MPLL_PLLMODE_AST2300 0x10 +#define HPLL_PLLMODE_AST2300 0x30 +#define DPLL_PLLMODE_AST2300 0x08 +#define DEL0_PLLMODE_AST2300 0x00 + +#define ERR_FATAL 0x00000001 + +typedef struct _VGAINFO { + USHORT usDeviceID; + UCHAR jRevision; + + ULONG ulMCLK; + ULONG ulDRAMBusWidth; + + ULONG ulCPUCLK; + ULONG ulAHBCLK; +} _VGAInfo; + +#endif // End PLLTESTU_H diff --git a/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c new file mode 100644 index 0000000..2414d57 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/PLLTESTU.c @@ -0,0 +1,409 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define PLLTEST_C +static const char ThisFile[] = "PLLTEST.c"; + +#include "SWFUNC.H" + +#include "COMMINF.H" +#include "STDUBOOT.H" +#include "TYPEDEF.H" +#include "IO.H" +#include "PLLTESTU.H" + +/* + * static + */ +static UCHAR jVersion[] = "v.0.57.00"; + +void print_usage( void ) +{ + printf(" PLLTest [pll mode] [err rate]\n"); + printf(" [pll mode] h-pll: ARM CPU Clock PLL\n"); + printf(" m-pll: Memory Clock PLL\n"); + printf(" [err rate] Error Rate: unit %\n"); + printf(" default is 1%\n"); +} + +BOOL CompareToRing(_VGAInfo *VGAInfo, ULONG ulPLLMode, ULONG ulDCLK, ULONG ulErrRate) +{ + ULONG ulCounter, ulLowLimit, ulHighLimit; + ULONG ulData, ulValue, ulDiv; + ULONG ulSCUBase; + double del0; + ULONG uldel0; + + if ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180)) + ulSCUBase = 0x80fc8200; + else + ulSCUBase = 0x1e6e2000; + + //Fixed AST2300 H-PLL can't Get Correct Value in VGA only mode, ycchen@081711 + if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == HPLL_PLLMODE_AST2300) ) + { + WriteSOC_DD(ulSCUBase, 0x1688a8a8); + ulData = ReadSOC_DD(ulSCUBase + 0x08); + WriteSOC_DD(ulSCUBase + 0x08, ulData & 0xFFFFFF00); + } + + ulCounter = (ulDCLK/1000) * 512 / 24000 - 1; + ulLowLimit = ulCounter * (100 - ulErrRate) / 100; + ulHighLimit = ulCounter * (100 + ulErrRate) / 100; + + DELAY(10); + WriteSOC_DD(ulSCUBase, 0x1688a8a8); + WriteSOC_DD(ulSCUBase + 0x28, (ulHighLimit << 16) | ulLowLimit); + WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode); + WriteSOC_DD(ulSCUBase + 0x10, ulPLLMode | 0x03); + DELAY(1); + do { + ulData = ReadSOC_DD(ulSCUBase + 0x10); + } while (!(ulData & 0x40)); + ulValue = ReadSOC_DD(ulSCUBase + 0x14); + + //Patch for AST1160/1180 DCLK calculate + if ( ((VGAInfo->usDeviceID == 0x1160) || (VGAInfo->usDeviceID == 0x1180)) && (ulPLLMode == DPLL_PLLMODE_AST1160) ) + { + ulData = ReadSOC_DD(0x80fc906c); + ulDiv = ulData & 0x000c0000; + ulDiv >>= 18; + ulDiv++; + ulValue /= ulDiv; + } + + if ( (VGAInfo->jRevision >= 0x20) && (ulPLLMode == DEL0_PLLMODE_AST2300) ) + { + del0 = (double)(24.0 * (ulValue + 1) / 512.0); + del0 = 1000/del0/16/8; + uldel0 = (ULONG) (del0 * 1000000); + if (uldel0 < ulDCLK) + { + printf( "[PASS][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000); + ulData |= 0x80; + } + else + { + printf( "[ERROR][DEL0] Actual DEL0:%f ns, Max. DEL0:%f ns \n", del0, (double)ulDCLK/1000000); + ulData == 0x00; + } + } + else + { + printf( "[INFO] PLL Predict Count = %x, Actual Count = %x \n", ulCounter, ulValue); + } + + WriteSOC_DD(ulSCUBase + 0x10, 0x2C); //disable ring + + if (ulData & 0x80) + return (TRUE); + else + return(FALSE); +} /* CompareToRing */ + +VOID GetDRAMInfo(_VGAInfo *VGAInfo) +{ + ULONG ulData, ulData2; + ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD; + + if (VGAInfo->jRevision >= 0x10) + { + WriteSOC_DD(0x1e6e2000, 0x1688A8A8); + + //Get DRAM Bus Width + ulData = ReadSOC_DD(0x1e6e0004); + if (ulData & 0x40) + VGAInfo->ulDRAMBusWidth = 16; + else + VGAInfo->ulDRAMBusWidth = 32; + + ulRefPLL = 24000; + if (VGAInfo->jRevision >= 0x30) //AST2400 + { + ulData = ReadSOC_DD(0x1e6e2070); + if (ulData & 0x00800000) //D[23] = 1 + ulRefPLL = 25000; + } + + ulData = ReadSOC_DD(0x1e6e2020); + ulDeNumerator = ulData & 0x0F; + ulNumerator = (ulData & 0x07E0) >> 5; + ulOD = (ulData & 0x10) ? 1:2; + + ulData = (ulData & 0x7000) >> 12; + switch (ulData) + { + case 0x07: + ulDivider = 16; + break; + case 0x06: + ulDivider = 8; + break; + case 0x05: + ulDivider = 4; + break; + case 0x04: + ulDivider = 2; + break; + default: + ulDivider = 0x01; + } + + VGAInfo->ulMCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * ulDivider * 1000); + } +} // GetDRAMInfo + +VOID GetCLKInfo( _VGAInfo *VGAInfo) +{ + ULONG ulData, ulCPUTrap, ulAHBTrap; + ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider, ulOD; + + if (VGAInfo->jRevision >= 0x30) + { + WriteSOC_DD(0x1e6e2000, 0x1688a8a8); + ulData = ReadSOC_DD(0x1e6e2024); + if (ulData & 0x40000) //from H-PLL + { + ulRefPLL = 24000; + ulData = ReadSOC_DD(0x1e6e2070); + if (ulData & 0x00800000) //D[23] = 1 + ulRefPLL = 25000; + + ulData = ReadSOC_DD(0x1e6e2024); + + ulDeNumerator = ulData & 0x0F; + ulNumerator = (ulData & 0x07E0) >> 5; + ulOD = (ulData & 0x10) ? 1:2; + + VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000); + + } + else //from trapping + { + ulRefPLL = 24; + ulData = ReadSOC_DD(0x1e6e2070); + if (ulData & 0x00800000) //D[23] = 1 + ulRefPLL = 25; + + ulCPUTrap = ulData & 0x0300; + ulCPUTrap >>= 8; + + switch (ulCPUTrap) + { + case 0x00: + VGAInfo->ulCPUCLK = ulRefPLL * 16; + break; + case 0x01: + VGAInfo->ulCPUCLK = ulRefPLL * 15; + break; + case 0x02: + VGAInfo->ulCPUCLK = ulRefPLL * 14; + break; + case 0x03: + VGAInfo->ulCPUCLK = ulRefPLL * 17; + break; + } + + } + + ulData = ReadSOC_DD(0x1e6e2070); + ulAHBTrap = ulData & 0x0c00; + ulAHBTrap >>= 10; + switch (ulAHBTrap) + { + case 0x00: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK; + break; + case 0x01: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2; + break; + case 0x02: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4; + break; + case 0x03: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3; + break; + } + + } //AST2400 + else if (VGAInfo->jRevision >= 0x20) + { + WriteSOC_DD(0x1e6e2000, 0x1688a8a8); + ulData = ReadSOC_DD(0x1e6e2024); + if (ulData & 0x40000) //from H-PLL + { + ulRefPLL = 24000; + + ulData = ReadSOC_DD(0x1e6e2024); + + ulDeNumerator = ulData & 0x0F; + ulNumerator = (ulData & 0x07E0) >> 5; + ulOD = (ulData & 0x10) ? 1:2; + + VGAInfo->ulCPUCLK = ulRefPLL * ulOD * (ulNumerator + 2) / ((ulDeNumerator + 1) * 1000); + + } + else //from trapping + { + ulData = ReadSOC_DD(0x1e6e2070); + ulCPUTrap = ulData & 0x0300; + ulCPUTrap >>= 8; + + switch (ulCPUTrap) + { + case 0x00: + VGAInfo->ulCPUCLK = 384; + break; + case 0x01: + VGAInfo->ulCPUCLK = 360; + break; + case 0x02: + VGAInfo->ulCPUCLK = 336; + break; + case 0x03: + VGAInfo->ulCPUCLK = 408; + break; + } + + } + + ulData = ReadSOC_DD(0x1e6e2070); + ulAHBTrap = ulData & 0x0c00; + ulAHBTrap >>= 10; + switch (ulAHBTrap) + { + case 0x00: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK; + break; + case 0x01: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 2; + break; + case 0x02: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 4; + break; + case 0x03: + VGAInfo->ulAHBCLK = VGAInfo->ulCPUCLK / 3; + break; + } + + } //AST2300 +} // GetCLKInfo + +int pll_function(int argc, char *argv[]) +{ + _VGAInfo *pVGAInfo; + ULONG ulErrRate = 1; + ULONG PLLMode; + ULONG RefClk; + CHAR *stop_at; + CHAR i; + + printf("**************************************************** \n"); + printf("*** ASPEED Graphics PLL Test %s Log *** \n", jVersion); + printf("*** for u-boot *** \n"); + printf("**************************************************** \n"); + printf("\n"); + + // Check chip type + switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) { + case 0x02010303 : + case 0x02000303 : + printf("The chip is AST2400\n" ); + pVGAInfo->usDeviceID = 0x2400; + pVGAInfo->jRevision = 0x30; + break; + + case 0x02010103 : + case 0x02000003 : + printf("The chip is AST1400\n" ); + pVGAInfo->usDeviceID = 0x1400; + pVGAInfo->jRevision = 0x30; + break; + + case 0x01010303 : + case 0x01000003 : + printf("The chip is AST2300\n" ); + pVGAInfo->usDeviceID = 0x2300; + pVGAInfo->jRevision = 0x20; + break; + + case 0x01010203 : + printf("The chip is AST1050\n" ); + pVGAInfo->usDeviceID = 0x1050; + pVGAInfo->jRevision = 0x20; + break; + + default : + printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) ); + return(1); + } + + + GetDRAMInfo( pVGAInfo ); + GetCLKInfo( pVGAInfo ); + + if ( ( argc <= 1 ) || ( argc >= 4 ) ){ + print_usage(); + return (ERR_FATAL); + } + else { + for ( i = 1; i < argc; i++ ) { + switch ( i ) { + case 1: + if (!strcmp(argv[i], "m-pll")) + { + if (pVGAInfo->jRevision >= 0x20) + PLLMode = MPLL_PLLMODE_AST2300; + else + PLLMode = MPLL_PLLMODE; + + RefClk = pVGAInfo->ulMCLK * 1000000; + if (pVGAInfo->jRevision >= 0x20) //dual-edge + RefClk /= 2; + } + else if (!strcmp(argv[i], "h-pll")) + { + if (pVGAInfo->jRevision >= 0x20) + PLLMode = HPLL_PLLMODE_AST2300; + else + PLLMode = HPLL_PLLMODE; + + //AST2300 only has HCLK ring test mode, ycchen@040512 + RefClk = pVGAInfo->ulCPUCLK * 1000000; //Other : H-PLL + if (pVGAInfo->jRevision >= 0x20) //AST2300: HCLK + RefClk = pVGAInfo->ulAHBCLK * 1000000; + } + else { + print_usage(); + return (ERR_FATAL); + } + break; + case 2: + ulErrRate = (ULONG) strtoul(argv[i], &stop_at, 10); + + break; + default: + break; + } // End switch() + } // End for + } + + /* Compare ring */ + if (CompareToRing(pVGAInfo, PLLMode, RefClk, ulErrRate ) == TRUE) + { + printf("[PASS] %s PLL Check Pass!! \n", argv[1]); + return 0; + } + else + { + printf("[ERROR] %s PLL Check Failed!! \n", argv[1]); + return (ERR_FATAL); + } +} diff --git a/arch/arm/cpu/arm926ejs/aspeed/SPIM.c b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c new file mode 100644 index 0000000..e1bdd07 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/SPIM.c @@ -0,0 +1,63 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define SPIM_C
+static const char ThisFile[] = "SPIM.c";
+
+#include "SWFUNC.H"
+
+#ifdef SPI_BUS
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <conio.h>
+#include <string.h>
+#include "TYPEDEF.H"
+#include "LIB_SPI.H"
+
+#define SPIM_CMD_WHA 0x01
+#define SPIM_CMD_RD 0x0B
+#define SPIM_CMD_DRD 0xBB
+#define SPIM_CMD_WR 0x02
+#define SPIM_CMD_DWR 0xD2
+#define SPIM_CMD_STA 0x05
+#define SPIM_CMD_ENBYTE 0x06
+#define SPIM_CMD_DISBYTE 0x04
+
+ULONG spim_cs;
+ULONG spim_base;
+ULONG spim_hadr;
+
+void spim_end()
+{
+ ULONG data;
+
+ data = MIndwm((ULONG)mmiobase, 0x1E620010 + (spim_cs << 2));
+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data | 0x4);
+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (spim_cs << 2), data);
+}
+
+//------------------------------------------------------------
+void spim_init(int cs)
+{
+ ULONG data;
+
+ spim_cs = cs;
+ MOutdwm( (ULONG)mmiobase, 0x1E620000, (0x2 << (cs << 1)) | (0x10000 << cs));
+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00000007);
+ MOutdwm( (ULONG)mmiobase, 0x1E620010 + (cs << 2), 0x00002003);
+ MOutdwm( (ULONG)mmiobase, 0x1E620004, 0x100 << cs);
+ data = MIndwm((ULONG)mmiobase, 0x1E620030 + (cs << 2));
+ spim_base = 0x20000000 | ((data & 0x007f0000) << 7);
+ MOutwm ( (ULONG)mmiobase, spim_base, SPIM_CMD_WHA);
+ spim_end();
+ spim_hadr = 0;
+}
+#endif // End SPI_BUS
diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H new file mode 100644 index 0000000..4e0adf6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.H @@ -0,0 +1,17 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef STDUBOOT_H +#define STDUBOOT_H + +unsigned long int strtoul(char *string, char **endPtr, int base); +int atoi( char s[] ); + +#endif // End STDUBOOT_H diff --git a/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c new file mode 100644 index 0000000..4b1f439 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/STDUBOOT.c @@ -0,0 +1,224 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define STDUBOOT_C +static const char ThisFile[] = "STDUBOOT.c"; + +#include "SWFUNC.H" + +#ifdef SLT_UBOOT + +int isspace ( char c ) +{ + if ( ( c == ' ' ) || ( c == 9 ) || ( c == 13 ) ) + return 1; + + return 0; +} + +/* + * strtoul.c -- + * + * Source code for the "strtoul" library procedure. + * + * Copyright 1988 Regents of the University of California + * Permission to use, copy, modify, and distribute this + * software and its documentation for any purpose and without + * fee is hereby granted, provided that the above copyright + * notice appear in all copies. The University of California + * makes no representations about the suitability of this + * software for any purpose. It is provided "as is" without + * express or implied warranty. + */ + +//#include <ctype.h> + +/* + * The table below is used to convert from ASCII digits to a + * numerical equivalent. It maps from '0' through 'z' to integers + * (100 for non-digit characters). + */ + +static char cvtIn[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* '0' - '9' */ + 100, 100, 100, 100, 100, 100, 100, /* punctuation */ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'A' - 'Z' */ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 34, 35, + 100, 100, 100, 100, 100, 100, /* punctuation */ + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, /* 'a' - 'z' */ + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 34, 35}; + +/* + *---------------------------------------------------------------------- + * + * strtoul -- + * + * Convert an ASCII string into an integer. + * + * Results: + * The return value is the integer equivalent of string. If endPtr + * is non-NULL, then *endPtr is filled in with the character + * after the last one that was part of the integer. If string + * doesn't contain a valid integer value, then zero is returned + * and *endPtr is set to string. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------- + */ + +unsigned long int +strtoul(char *string, char **endPtr, int base) + /* string; String of ASCII digits, possibly + * preceded by white space. For bases + * greater than 10, either lower- or + * upper-case digits may be used. + */ + /* **endPtr; Where to store address of terminating + * character, or NULL. */ + /* base; Base for conversion. Must be less + * than 37. If 0, then the base is chosen + * from the leading characters of string: + * "0x" means hex, "0" means octal, anything + * else means decimal. + */ +{ + register char *p; + register unsigned long int result = 0; + register unsigned digit; + int anyDigits = 0; + + /* + * Skip any leading blanks. + */ + + p = string; + while (isspace(*p)) { + p += 1; + } + + /* + * If no base was provided, pick one from the leading characters + * of the string. + */ + + if (base == 0) + { + if (*p == '0') { + p += 1; + if (*p == 'x') { + p += 1; + base = 16; + } else { + + /* + * Must set anyDigits here, otherwise "0" produces a + * "no digits" error. + */ + + anyDigits = 1; + base = 8; + } + } + else base = 10; + } else if (base == 16) { + + /* + * Skip a leading "0x" from hex numbers. + */ + + if ((p[0] == '0') && (p[1] == 'x')) { + p += 2; + } + } + + /* + * Sorry this code is so messy, but speed seems important. Do + * different things for base 8, 10, 16, and other. + */ + + if (base == 8) { + for ( ; ; p += 1) { + digit = *p - '0'; + if (digit > 7) { + break; + } + result = (result << 3) + digit; + anyDigits = 1; + } + } else if (base == 10) { + for ( ; ; p += 1) { + digit = *p - '0'; + if (digit > 9) { + break; + } + result = (10*result) + digit; + anyDigits = 1; + } + } else if (base == 16) { + for ( ; ; p += 1) { + digit = *p - '0'; + if (digit > ('z' - '0')) { + break; + } + digit = cvtIn[digit]; + if (digit > 15) { + break; + } + result = (result << 4) + digit; + anyDigits = 1; + } + } else { + for ( ; ; p += 1) { + digit = *p - '0'; + if (digit > ('z' - '0')) { + break; + } + digit = cvtIn[digit]; + if (digit >= base) { + break; + } + result = result*base + digit; + anyDigits = 1; + } + } + + /* + * See if there were any digits at all. + */ + + if (!anyDigits) { + p = string; + } + + if (endPtr != 0) { + *endPtr = p; + } + + return result; +} + +// ----------------------------------------------------------------------------- +int atoi( char s[] ) +{ + + int i; + int ans = 0; + + for( i = 0; s[i] >= '0' && s[i] <= '9'; ++i ) + ans = ( 10 * ans ) + ( s[i] - '0' ); + + return ans; +} + +#endif // End SLT_UBOOT diff --git a/arch/arm/cpu/arm926ejs/aspeed/STRESS.c b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c new file mode 100644 index 0000000..e86685e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/STRESS.c @@ -0,0 +1,144 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define STRESS_C
+static const char ThisFile[] = "STRESS.c";
+
+#include "SWFUNC.H"
+#include "COMMINF.H"
+#include "IO.H"
+
+#define TIMEOUT_DRAM 5000000
+
+/* ------------------------------------------------------------------------- */
+int MMCTestBurst(unsigned int datagen)
+{
+ unsigned int data;
+ unsigned int timeout = 0;
+
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+ WriteSOC_DD( 0x1E6E0070, (0x000000C1 | (datagen << 3)) );
+
+ do {
+ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
+
+ if( data & 0x2000 )
+ return(0);
+
+ if( ++timeout > TIMEOUT_DRAM ) {
+ printf("Timeout!!\n");
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+
+ return(0);
+ }
+ } while( !data );
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+
+ return(1);
+}
+
+/* ------------------------------------------------------------------------- */
+int MMCTestSingle(unsigned int datagen)
+{
+ unsigned int data;
+ unsigned int timeout = 0;
+
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+ WriteSOC_DD( 0x1E6E0070, (0x00000085 | (datagen << 3)) );
+
+ do {
+ data = ReadSOC_DD( 0x1E6E0070 ) & 0x3000;
+
+ if( data & 0x2000 )
+ return(0);
+
+ if( ++timeout > TIMEOUT_DRAM ){
+ printf("Timeout!!\n");
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+
+ return(0);
+ }
+ } while ( !data );
+ WriteSOC_DD( 0x1E6E0070, 0x00000000 );
+
+ return(1);
+}
+
+/* ------------------------------------------------------------------------- */
+int MMCTest()
+{
+ unsigned int pattern;
+
+ pattern = ReadSOC_DD( 0x1E6E2078 );
+ printf("Pattern = %08X : ",pattern);
+
+ WriteSOC_DD(0x1E6E0074, (DRAM_MapAdr | 0x7fffff) );
+ WriteSOC_DD(0x1E6E007C, pattern );
+
+ if(!MMCTestBurst(0)) return(0);
+ if(!MMCTestBurst(1)) return(0);
+ if(!MMCTestBurst(2)) return(0);
+ if(!MMCTestBurst(3)) return(0);
+ if(!MMCTestBurst(4)) return(0);
+ if(!MMCTestBurst(5)) return(0);
+ if(!MMCTestBurst(6)) return(0);
+ if(!MMCTestBurst(7)) return(0);
+ if(!MMCTestSingle(0)) return(0);
+ if(!MMCTestSingle(1)) return(0);
+ if(!MMCTestSingle(2)) return(0);
+ if(!MMCTestSingle(3)) return(0);
+ if(!MMCTestSingle(4)) return(0);
+ if(!MMCTestSingle(5)) return(0);
+ if(!MMCTestSingle(6)) return(0);
+ if(!MMCTestSingle(7)) return(0);
+
+ return(1);
+}
+
+/* ------------------------------------------------------------------------- */
+int dram_stress_function(int argc, char *argv[])
+{
+ unsigned int Pass;
+ unsigned int PassCnt = 0;
+ unsigned int Testcounter = 0;
+ int ret = 1;
+ char *stop_at;
+
+ printf("**************************************************** \n");
+ printf("*** ASPEED Stress DRAM *** \n");
+ printf("*** 20131107 for u-boot *** \n");
+ printf("**************************************************** \n");
+ printf("\n");
+
+ if ( argc != 2 ){
+ ret = 0;
+ return ( ret );
+ }
+ else {
+ Testcounter = (unsigned int) strtoul(argv[1], &stop_at, 10);
+ }
+
+ WriteSOC_DD(0x1E6E0000, 0xFC600309);
+
+ while( ( Testcounter > PassCnt ) || ( Testcounter == 0 ) ){
+ if( !MMCTest() ) {
+ printf("FAIL...%d/%d\n", PassCnt, Testcounter);
+ ret = 0;
+
+ break;
+ }
+ else {
+ PassCnt++;
+ printf("Pass %d/%d\n", PassCnt, Testcounter);
+ }
+ } // End while()
+
+ return( ret );
+}
diff --git a/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H new file mode 100644 index 0000000..4671612 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/SWFUNC.H @@ -0,0 +1,137 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef SWFUNC_H +#define SWFUNC_H + + +//--------------------------------------------------------- +// Program information +//--------------------------------------------------------- +#define VER_NAME "Ver 0.34 version @2014/03/25 0932" + +/* == Step 1: ====== Support OS system =================== */ +// LinuxAP +// #define Windows +#define SLT_UBOOT +//#define SLT_DOS + +/* == Step 2:======== Support interface ================== */ +/* Choose One */ +//#define SPI_BUS +//#define USE_LPC +//#define USE_P2A // PCI or PCIe bus to AHB bus + +/* == Step 3:========== Support Chip ================== */ +//#define AST1010_CHIP +//#define AST3200_IOMAP +//#define FPGA + +#ifdef AST1010_CHIP + #ifdef SLT_UBOOT + #define AST1010_IOMAP 1 + #endif + #ifdef SLT_DOS + #define AST1010_IOMAP 2 + + // AST1010 only has LPC interface + #undef USE_P2A + #undef SPI_BUS + #define USE_LPC + #endif +#endif + +/* == Step 4:========== Select PHY ================== */ +//#define SUPPORT_PHY_LAN9303 // Initial PHY via I2C bus +#define LAN9303_I2C_BUSNUM 6 // 1-based +#define LAN9303_I2C_ADR 0x14 + +/* ====================== Program ======================== */ +// The "PHY_NCSI" option is only for DOS compiler +#if defined (PHY_NCSI) + #ifdef SLT_UBOOT + #error Wrong setting...... + #endif +#endif + +#if defined (PHY_NCSI) + #ifdef SUPPORT_PHY_LAN9303 + #error Wrong setting (Can NOT support LAN9303)...... + #endif +#endif + +/* ================= Check setting ===================== */ +#ifdef SLT_UBOOT + #ifdef SLT_DOS + #error Can NOT support two OS + #endif +#endif +#ifdef SLT_DOS + #ifdef SLT_UBOOT + #error Can NOT support two OS + #endif +#endif + +#ifdef USE_P2A + #ifdef SLT_UBOOT + #error Can NOT be set PCI bus in Uboot + #endif +#endif +#ifdef USE_LPC + #ifdef SLT_UBOOT + #error Can NOT be set LPC bus in Uboot + #endif +#endif +#ifdef SPI_BUS + #ifdef SLT_UBOOT + #error Can NOT be set SPI bus in Uboot + #endif +#endif + +/* ======================== Program flow control ======================== */ +#define RUN_STEP 5 +// 0: read_scu +// 1: parameter setup +// 2: init_scu1, +// 3: init_scu_macrst +// 4: Data Initial +// 5: ALL + +/* ====================== Switch print debug message ====================== */ +#define DbgPrn_Enable_Debug_delay 0 +//#define DbgPrn_FuncHeader 0 //1 +#define DbgPrn_ErrFlg 0 +#define DbgPrn_BufAdr 0 //1 +#define DbgPrn_Bufdat 0 +#define DbgPrn_BufdatDetail 0 +#define DbgPrn_PHYRW 0 +#define DbgPrn_PHYInit 0 +#define DbgPrn_PHYName 0 +#define DbgPrn_DumpMACCnt 0 +#define DbgPrn_Info 0 //1 +#define DbgPrn_FRAME_LEN 0 + + +/* ============ Enable or Disable Check item of the descriptor ============ */ +#define CheckRxOwn +#define CheckRxErr +//#define CheckOddNibble +#define CheckCRC +#define CheckRxFIFOFull +#define CheckRxLen +//#define CheckDataEveryTime + +//#define CheckRxbufUNAVA +#define CheckRPktLost +//#define CheckNPTxbufUNAVA +#define CheckTPktLost +#define CheckRxBuf + +#endif // SWFUNC_H diff --git a/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c new file mode 100644 index 0000000..24ec0c5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/TRAPTEST.c @@ -0,0 +1,151 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define PLLTEST_C +static const char ThisFile[] = "PLLTEST.c"; + +#include "SWFUNC.H" + +#include "COMMINF.H" +#include "TYPEDEF.H" +#include "IO.H" + +#define ASTCHIP_2400 0 +#define ASTCHIP_2300 1 +#define ASTCHIP_1400 2 +#define ASTCHIP_1300 3 +#define ASTCHIP_1050 4 + +const UCHAR jVersion[] = "v.0.60.06"; + +typedef struct _TRAPINFO { + USHORT CPU_clk; + UCHAR CPU_AHB_ratio; +} _TrapInfo; + +const _TrapInfo AST_default_trap_setting[] = { + // CPU_clk, CPU_AHB_ratio + { 384, 2 }, // AST2400 or AST1250 ( ASTCHIP_2400 ) + { 384, 2 }, // AST2300 ( ASTCHIP_2300 ) + { 384, 0xFF }, // AST1400 ( ASTCHIP_1400 ) + { 384, 0xFF }, // AST1300 ( ASTCHIP_1300 ) + { 384, 2 } // AST1050 ( ASTCHIP_1050 ) +}; + +int trap_function(int argc, char *argv[]) +{ + UCHAR chiptype; + ULONG ulData, ulTemp; + UCHAR status = TRUE; + USHORT val_trap; + + printf("**************************************************** \n"); + printf("*** ASPEED Trap Test %s Log *** \n", jVersion); + printf("*** for u-boot *** \n"); + printf("**************************************************** \n"); + printf("\n"); + + // Check chip type + switch ( ReadSOC_DD( 0x1e6e2000 + 0x7c ) ) { + case 0x02010303 : + case 0x02000303 : + printf("The chip is AST2400 or AST1250\n" ); + chiptype = ASTCHIP_2400; + break; + + case 0x02010103 : + case 0x02000003 : + printf("The chip is AST1400\n" ); + chiptype = ASTCHIP_1400; + break; + + case 0x01010303 : + case 0x01000003 : + printf("The chip is AST2300\n" ); + chiptype = ASTCHIP_2300; + break; + + case 0x01010203 : + printf("The chip is AST1050\n" ); + chiptype = ASTCHIP_1050; + break; + + case 0x01010003 : + printf("The chip is AST1300\n" ); + chiptype = ASTCHIP_1300; + break; + + default : + printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", ReadSOC_DD( 0x1e6e2000 + 0x7c ) ); + return(1); + } + + WriteSOC_DD(0x1e6e2000, 0x1688A8A8); + ulData = ReadSOC_DD(0x1e6e2070); + + // Check CPU clock + ulTemp = ulData; + ulTemp &= 0x0300; + ulTemp >>= 8; + + switch (ulTemp) + { + case 0x00: + val_trap = 384; + break; + case 0x01: + val_trap = 360; + break; + case 0x02: + val_trap = 336; + break; + case 0x03: + val_trap = 408; + break; + } + + if (AST_default_trap_setting[chiptype].CPU_clk != val_trap) + { + printf("[ERROR] CPU CLK: Correct is %d; Real is %d \n", AST_default_trap_setting[chiptype].CPU_clk, val_trap); + status = FALSE; + } + + // Check cpu_ahb_ratio + ulTemp = ulData; + ulTemp &= 0x0c00; + ulTemp >>= 10; + + switch (ulTemp) + { + case 0x00: + val_trap = 1; + break; + case 0x01: + val_trap = 2; + break; + case 0x02: + val_trap = 4; + break; + case 0x03: + val_trap = 3; + break; + } + + if (AST_default_trap_setting[chiptype].CPU_AHB_ratio != val_trap) + { + printf("[ERROR] CPU:AHB: Correct is %x:1; Real is %x:1 \n", AST_default_trap_setting[chiptype].CPU_AHB_ratio, val_trap); + status = FALSE; + } + + if ( status == TRUE ) + printf("[PASS] hardware trap for CPU clock and CPU\\AHB ratio.\n"); + + return status; +} diff --git a/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H new file mode 100644 index 0000000..3053ad7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/TYPEDEF.H @@ -0,0 +1,74 @@ +/*
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef TYPEDEF_H
+#define TYPEDEF_H
+
+#include "SWFUNC.H"
+
+//
+// Define
+//
+#define PCI 1
+#define PCIE 2
+#define AGP 3
+#define ACTIVE 4
+
+#if defined(LinuxAP)
+ #ifndef FLONG
+ #define FLONG unsigned long
+ #endif
+ #ifndef ULONG
+ #define ULONG unsigned long
+ #endif
+ #ifndef LONG
+ #define LONG long
+ #endif
+ #ifndef USHORT
+ #define USHORT unsigned short
+ #endif
+ #ifndef SHORT
+ #define SHORT short
+ #endif
+ #ifndef UCHAR
+ #define UCHAR unsigned char
+ #endif
+ #ifndef CHAR
+ #define CHAR char
+ #endif
+ #ifndef BYTE
+ #define BYTE unsigned char
+ #endif
+ #ifndef VOID
+ #define VOID void
+ #endif
+ #ifndef SCHAR
+ #define SCHAR signed char
+ #endif
+#else
+/* DOS Program */
+ #define VOID void
+ #define FLONG unsigned long
+ #define ULONG unsigned long
+ #define USHORT unsigned short
+ #define UCHAR unsigned char
+ #define LONG long
+ #define SHORT short
+ #define CHAR char
+ #define BYTE UCHAR
+ #define BOOL SHORT
+ #define BOOLEAN unsigned short
+ #define PULONG ULONG *
+ #define SCHAR signed char
+#endif
+ #define TRUE 1
+ #define FALSE 0
+
+#endif // TYPEDEF_H
diff --git a/arch/arm/cpu/arm926ejs/aspeed/mactest.c b/arch/arm/cpu/arm926ejs/aspeed/mactest.c new file mode 100644 index 0000000..62a696d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/mactest.c @@ -0,0 +1,1214 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define MACTEST_C +static const char ThisFile[] = "MACTEST.c"; + +#include "SWFUNC.H" + +#ifdef SLT_UBOOT + #include <common.h> + #include <command.h> + #include <post.h> + #include <malloc.h> + #include <net.h> + #include "COMMINF.H" + #include "STDUBOOT.H" + #include "IO.H" +#else + #include <stdlib.h> + #include <string.h> + #include "LIB.H" + #include "COMMINF.H" + #include "IO.H" +#endif + +const BYTE Val_Array[16] = {0,1, 2,3, 4,5, 6,7, 8,9, 10,11, 12,13, 14,15}; // AST2300-A1 +const BYTE Val_Array_A0[16] = {8,1, 10,3, 12,5, 14,7, 0,9, 2,11, 4,13, 6,15}; // AST2300-A0 + +#ifdef SLT_UBOOT +int main_function(int argc, char *argv[]) +#endif +#ifdef SLT_DOS +int main(int argc, char *argv[]) +#endif +{ + CHAR MAC2_Valid; + CHAR MAC_1GEn; + CHAR MAC1_RMII; + CHAR Enable_IntLoopPHY; + CHAR Disable_RecovPHY; + CHAR Force1G; + CHAR Force10M; + CHAR Force100M; + CHAR *stop_at; + ULONG IOStr_val; + ULONG IOStr_max; + ULONG IOStr_shf; + ULONG IOdly_val; + ULONG Err_Flag_allapeed; + int DES_LowNumber; + int index; + int i; + int j; + #ifdef Enable_NCSI_LOOP_INFINI + BYTE GSpeed_org[3]; + #endif + +#ifdef SPI_BUS + VIDEO_ENGINE_INFO VideoEngineInfo; +#else + // ( USE_P2A | USE_LPC ) + UCHAR *ulMMIOLinearBaseAddress; +#endif + + #ifdef SLT_UBOOT + #else + time(×tart); + #endif + + // For DOS system + #if defined(PHY_NCSI) + // For DOS compiler OPEN WATCOM + ModeSwitch = MODE_NSCI; + #else + #ifdef SLT_DOS + ModeSwitch = MODE_DEDICATED; + #endif + #endif + +//------------------------------------------------------------ +// Argument Initial +//------------------------------------------------------------ + Err_Flag_allapeed = 0; + Err_Flag = 0; + Err_Flag_PrintEn = 1; + Loop_rl[0] = 0; + Loop_rl[1] = 0; + Loop_rl[2] = 0; + +//------------------------------------------------------------ +// Bus Initial +//------------------------------------------------------------ +#if defined(LinuxAP) +#else + //DOS system + #ifdef SPI_BUS + #endif + #ifdef USE_LPC + + if ( findlpcport( 0x0d ) == 0) { + printf("Failed to find proper LPC port \n"); + + return(1); + } + open_aspeed_sio_password(); + enable_aspeed_LDU( 0x0d ); + #endif + #ifdef USE_P2A + // PCI bus + #ifdef DOS_PMODEW + if (CheckDOS()) return 1; + #endif + + #ifdef DbgPrn_FuncHeader + printf ("Initial-MMIO\n"); + Debug_delay(); + #endif + ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2000, ACTIVE); + if ( ulPCIBaseAddress == 0 ) + ulPCIBaseAddress = FindPCIDevice (0x1688, 0x2000, ACTIVE); + if ( ulPCIBaseAddress == 0 ) + ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x0200, ACTIVE); + if ( ulPCIBaseAddress == 0 ) + ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x3000, ACTIVE); + if ( ulPCIBaseAddress == 0 ) + ulPCIBaseAddress = FindPCIDevice (0x1A03, 0x2010, ACTIVE); + if ( ulPCIBaseAddress == 0 ) { + printf ("Can't find device\n"); + + return(1); + } + + WritePCIReg (ulPCIBaseAddress, 0x04, 0xFFFFFFFc, 0x3); + ulMMIOBaseAddress = ReadPCIReg (ulPCIBaseAddress, 0x14, 0xFFFF0000); + ulMMIOLinearBaseAddress = (UCHAR *)MapPhysicalToLinear (ulMMIOBaseAddress, 64 * 1024 * 1024); + #endif // #ifdef USE_P2A +#endif // End defined(LinuxAP) + +#ifdef SPI_BUS + GetDevicePCIInfo (&VideoEngineInfo); + mmiobase = VideoEngineInfo.VGAPCIInfo.ulMMIOBaseAddress; + spim_init(SPI_CS); +#else + // ( USE_P2A | USE_LPC ) + mmiobase = ulMMIOLinearBaseAddress; +#endif + +//------------------------------------------------------------ +// Check Chip Feature +//------------------------------------------------------------ + read_scu(); + + if (RUN_STEP >= 1) { + switch (SCU_7ch_old) { +// case 0x02000003 : sprintf(ASTChipName, "[ ]AST3200-FPGA" ); ASTChipType = 6; AST1100 = 0; break; + + case 0x03020003 : sprintf(ASTChipName, "[ ]AST1010-A2" ); ASTChipType = 5; AST1100 = 0; break; + case 0x03010003 : sprintf(ASTChipName, "[ ]AST1010-A1" ); ASTChipType = 5; AST1100 = 0; break; + case 0x03000003 : sprintf(ASTChipName, "[*]AST1010-A0" ); ASTChipType = 5; AST1100 = 0; break; + + case 0x02010303 : sprintf(ASTChipName, "[*]AST2400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A1 + case 0x02000303 : sprintf(ASTChipName, "[ ]AST2400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST2400-A0 + case 0x02010103 : sprintf(ASTChipName, "[*]AST1400-A1" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A1 + case 0x02000003 : sprintf(ASTChipName, "[ ]AST1400-A0" ); ASTChipType = 4; AST1100 = 0; break;//AST1400-A0 + + case 0x01010303 : sprintf(ASTChipName, "[*]AST2300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A1 + case 0x01010203 : sprintf(ASTChipName, "[*]AST1050-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1050-A1 + case 0x01010003 : sprintf(ASTChipName, "[*]AST1300-A1" ); ASTChipType = 3; AST1100 = 0; break;//AST1300-A1 + case 0x01000003 : sprintf(ASTChipName, "[ ]AST2300-A0" ); ASTChipType = 3; AST1100 = 0; break;//AST2300-A0 +// case 0x01860003 : sprintf(ASTChipName, "[ ]AST2300-FPGA" ); ASTChipType = 3; AST1100 = 0; break; + + case 0x00000102 : sprintf(ASTChipName, "[*]AST2200-A1" ); ASTChipType = 2; AST1100 = 0; break;//AST2200-A1/A0 + + case 0x00000302 : sprintf(ASTChipName, "[*]AST2100-A3" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A3/A2 + case 0x00000301 : sprintf(ASTChipName, "[ ]AST2100-A1" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A1 + case 0x00000300 : sprintf(ASTChipName, "[ ]AST2100-A0" ); ASTChipType = 1; AST1100 = 0; break;//AST2100-A0 + case 0x00000202 : sprintf(ASTChipName, "[*]AST2050/AST1100-A3, AST2150-A1"); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A3/A2 AST2150-A1/A0 + case 0x00000201 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A1" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A1 + case 0x00000200 : sprintf(ASTChipName, "[ ]AST2050/AST1100-A0" ); ASTChipType = 1; AST1100 = 1; break;//AST2050/AST1100-A0 + + default : + printf ("Error Silicon Revision ID(SCU7C) %08lx!!!\n", SCU_7ch_old); + return(1); + } // End switch (SCU_7ch_old) + + switch (ASTChipType) { + case 6 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 1; break; + case 5 : AST2300 = 1; AST2400 = 1; AST1010 = 1; AST3200 = 0; break; + case 4 : AST2300 = 1; AST2400 = 1; AST1010 = 0; AST3200 = 0; break; + case 3 : AST2300 = 1; AST2400 = 0; AST1010 = 0; AST3200 = 0; break; + default : AST2300 = 0; AST2400 = 0; AST1010 = 0; AST3200 = 0; break; + } // End switch (ASTChipType) + + if (ASTChipType == 3) { +#ifdef Force_Enable_MAC34 + WriteSOC_DD( SCU_BASE + 0xf0, 0xAEED0001 ); //enable mac34 + Enable_MAC34 = 1; +#else + if (SCU_f0h_old & 0x00000001) + Enable_MAC34 = 1; + else + Enable_MAC34 = 0; +#endif + } + else { + Enable_MAC34 = 0; + } // End if (ASTChipType == 3) + + Setting_scu(); + +//------------------------------------------------------------ +// Argument Input +//------------------------------------------------------------ + // Load default value + UserDVal = DEF_USER_DEF_PACKET_VAL; + IOTimingBund_arg = DEF_IOTIMINGBUND; + PHY_ADR_arg = DEF_PHY_ADR; + TestMode = DEF_TESTMODE; + LOOP_INFINI = 0; + LOOP_MAX_arg = 0; + GCtrl = ( DEF_MAC_LOOP_BACK << 6 ) | ( DEF_SKIP_CHECK_PHY << 5 ) | ( DEF_INIT_PHY << 3 ); + GSpeed = DEF_SPEED; + + // Get setting information by user + GRun_Mode = (BYTE)atoi(argv[1]); + + if ( ModeSwitch == MODE_NSCI ) { + ARPNumCnt = DEF_ARPNUMCNT; + ChannelTolNum = DEF_CHANNEL2NUM; + PackageTolNum = DEF_PACKAGE2NUM; + GSpeed = SET_100MBPS; // In NCSI mode, we set to 100M bps + } + + // Setting user's configuration + if (argc > 1) { + if ( ModeSwitch == MODE_NSCI ) + switch (argc) { + case 7: ARPNumCnt = (ULONG)atoi(argv[6]); + case 6: IOTimingBund_arg = (BYTE)atoi(argv[5]); + case 5: TestMode = (BYTE)atoi(argv[4]); + case 4: ChannelTolNum = (BYTE)atoi(argv[3]); + case 3: PackageTolNum = (BYTE)atoi(argv[2]); + default: break; + } + else + switch (argc) { + case 9: UserDVal = strtoul (argv[8], &stop_at, 16); + case 8: IOTimingBund_arg = (BYTE)atoi(argv[7]); + case 7: PHY_ADR_arg = (BYTE)atoi(argv[6]); + case 6: TestMode = (BYTE)atoi(argv[5]); + case 5: strcpy(LOOP_Str, argv[4]); + if (!strcmp(LOOP_Str, "#")) LOOP_INFINI = 1; + else LOOP_MAX_arg = (ULONG)atoi(LOOP_Str); + case 4: GCtrl = (BYTE)atoi(argv[3]); + case 3: GSpeed = (BYTE)atoi(argv[2]); + default: break; + } + + IOTimingBund = IOTimingBund_arg; + PHY_ADR = PHY_ADR_arg; + } + else { + // Wrong parameter + if ( ModeSwitch == MODE_NSCI ) { + if (AST2300) + printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode> <IO margin>\n\n"); + else + printf ("\nNCSITEST.exe run_mode <package_num> <channel_num> <test_mode>\n\n"); + PrintMode (); + PrintPakNUm(); + PrintChlNUm(); + PrintTest (); + if (AST2300) + PrintIOTimingBund (); + } + else { + if (AST2300) + printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr> <IO margin>\n\n"); + else + printf ("\nMACTEST.exe run_mode <speed> <ctrl> <loop_max> <test_mode> <phy_adr>\n\n"); + PrintMode (); + PrintSpeed (); + PrintCtrl (); + PrintLoop (); + PrintTest (); + PrintPHYAdr (); + if (AST2300) + PrintIOTimingBund (); + } + Finish_Close(); + + return(1); + } // End if (argc > 1) + +//------------------------------------------------------------ +// Check Argument +//------------------------------------------------------------ + switch ( GRun_Mode ) { + case 0: printf ("\n[MAC1]\n"); SelectMAC = 0; H_MAC_BASE = MAC_BASE1; break; + case 1: printf ("\n[MAC2]\n"); SelectMAC = 1; H_MAC_BASE = MAC_BASE2; break; + case 2: if (Enable_MAC34) {printf ("\n[MAC3]\n"); SelectMAC = 2; H_MAC_BASE = MAC_BASE3; break;} + else + goto Error_MAC_Mode; + case 3: if (Enable_MAC34) {printf ("\n[MAC4]\n"); SelectMAC = 3; H_MAC_BASE = MAC_BASE4; break;} + else + goto Error_MAC_Mode; + default: +Error_MAC_Mode: + printf ("Error run_mode!!!\n"); + PrintMode (); + + return(1); + } // End switch ( GRun_Mode ) + + H_TDES_BASE = TDES_BASE1; + H_RDES_BASE = RDES_BASE1; + MAC_PHYBASE = H_MAC_BASE; + + Force1G = 0; + Force10M = 0; + Force100M = 0; + GSpeed_sel[0] = 0;//1G + GSpeed_sel[1] = 0;//100M + GSpeed_sel[2] = 0;//10M + + switch ( GSpeed ) { + case SET_1GBPS : Force1G = 1; GSpeed_sel[0] = 1; break; + case SET_100MBPS : Force100M = 1; GSpeed_sel[1] = 1; break; + case SET_10MBPS : Force10M = 1; GSpeed_sel[2] = 1; break; + case SET_1G_100M_10MBPS : break; + default: printf ("Error speed!!!\n"); + PrintSpeed (); + return(1); + } // End switch ( GSpeed ) + + if ( ModeSwitch == MODE_NSCI ) { + Enable_MACLoopback = 0; // For mactest function + Enable_SkipChkPHY = 0; // For mactest function + Enable_IntLoopPHY = 0; // For mactest function + Enable_InitPHY = 0; // For mactest function + Disable_RecovPHY = 0; // For mactest function + BurstEnable = 0; // For mactest function + + PrintNCSIEn = (ARPNumCnt & 0x1); + ARPNumCnt = ARPNumCnt & 0xfffffffe; + + // Check parameter + if ((PackageTolNum < 1) || (PackageTolNum > 8)) { + PrintPakNUm(); + return(1); + } +// if ((ChannelTolNum < 0) || (ChannelTolNum > 32)) { + if (ChannelTolNum > 32) { + PrintChlNUm(); + return(1); + } + + switch (TestMode) { + case 0 : NCSI_DiSChannel = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break; + case 1 : NCSI_DiSChannel = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break; + case 6 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; break;} + else + goto Error_Test_Mode_NCSI; + case 7 : if (AST2300) {NCSI_DiSChannel = 1; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; break;} + else + goto Error_Test_Mode_NCSI; + default: + // Wrong parameter +Error_Test_Mode_NCSI: + printf ("Error test_mode!!!\n"); + PrintTest (); + return(1); + } // End switch (TestMode) + } + else { + if ( GCtrl & 0xffffff83 ) { + printf ("Error ctrl!!!\n"); + PrintCtrl (); + return(1); + } + else { + Enable_MACLoopback = ( GCtrl >> 6 ) & 0x1; // ?? + Enable_SkipChkPHY = ( GCtrl >> 5 ) & 0x1; // ?? + Enable_IntLoopPHY = ( GCtrl >> 4 ) & 0x1; + Enable_InitPHY = ( GCtrl >> 3 ) & 0x1; + Disable_RecovPHY = ( GCtrl >> 2 ) & 0x1; // ?? + + if (!AST2400 && Enable_MACLoopback) { + printf ("Error ctrl!!!\n"); + PrintCtrl (); + return(1); + } + } // End if ( GCtrl & 0xffffff83 ) + + if (!LOOP_MAX_arg) { + switch (GSpeed) { + case SET_1GBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 200; break; // 20140325 + case SET_100MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 20 ; break; // 20140325 + case SET_10MBPS : LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325 + case SET_1G_100M_10MBPS: LOOP_MAX_arg = DEF_LOOP_MAX * 10 ; break; // 20140325 + } + } // End if (!LOOP_MAX_arg) + + LOOP_MAX = LOOP_MAX_arg * 10; // 20140325 + Calculate_LOOP_CheckNum(); + + switch (TestMode) { + case 0 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break; + case 1 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; + case 2 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; + case 3 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; + case 4 : BurstEnable = 1; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ?? + case 5 : BurstEnable = 1; IEEETesting = 1; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ?? + case 6 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;} + else + goto Error_Test_Mode; + case 7 : if (AST2300) {BurstEnable = 0; IEEETesting = 0; IOTiming = 1; IOStrength = 1; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 0; break;} + else + goto Error_Test_Mode; + case 8 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 0; DataDelay = 0; break; // ?? + case 9 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 0; RxDataEnable = 1; DataDelay = 0; break; // ?? + case 10 : BurstEnable = 0; IEEETesting = 0; IOTiming = 0; IOStrength = 0; TxDataEnable = 1; RxDataEnable = 1; DataDelay = 1; break; // ?? + default: +Error_Test_Mode: + printf ("Error test_mode!!!\n"); + PrintTest (); + return(1); + } // End switch (TestMode) + + if ( PHY_ADR > 31 ) { + printf ("Error phy_adr!!!\n"); + PrintPHYAdr (); + return(1); + } // End if (PHY_ADR > 31) + } // End if ( ModeSwitch == MODE_NSCI ) + + if ( BurstEnable ) { + IOTimingBund = 0; + } + else { + if ( ~DataDelay && AST2300 ) { + if ( !( ( (7 >= IOTimingBund) && (IOTimingBund & 0x1) ) || + ( IOTimingBund == 0 ) ) ) { + printf ("Error IO margin!!!\n"); + PrintIOTimingBund (); + return(1); + } + } + else { + IOTimingBund = 0; + } // End if ( ~DataDelay && AST2300 ) + + // Define Output file name + if ( ModeSwitch == MODE_NSCI ) + sprintf(FileNameMain, "%d", SelectMAC+1); + else { + if (Enable_IntLoopPHY) + sprintf(FileNameMain, "%dI", SelectMAC+1); + else + sprintf(FileNameMain, "%dE", SelectMAC+1); + } + + #ifndef SLT_UBOOT + if ( IOTiming ) { + if ( IOStrength ) + sprintf(FileName, "MIOD%sS.log", FileNameMain); + else + sprintf(FileName, "MIOD%s.log", FileNameMain); + + fp_log = fopen(FileName,"w"); + + if ( IOStrength ) + sprintf(FileName, "MIO%sS.log", FileNameMain); + else + sprintf(FileName, "MIO%s.log", FileNameMain); + + fp_io = fopen(FileName,"w"); + } + else { + sprintf(FileName, "MAC%s.log", FileNameMain); + + fp_log = fopen(FileName,"w"); + } + #endif + } // End if (BurstEnable) + +//------------------------------------------------------------ +// Check Definition +//------------------------------------------------------------ + for (i = 0; i < 16; i++) + valary[i] = Val_Array[i]; + + if ( AST3200 ) { + MAC_Mode = (SCU_70h_old >> 6) & 0x1; + MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII + MAC2_1GEn = 0; + + MAC1_RMII = !MAC1_1GEn; + MAC2_RMII = 0; + MAC2_Valid = 0; + } + else if ( AST1010 ) { + MAC_Mode = 0; + MAC1_1GEn = 0; + MAC2_1GEn = 0; + + MAC1_RMII = 1; + MAC2_RMII = 0; + MAC2_Valid = 0; + } + else if ( AST2300 ) { + if (SCU_7ch_old == 0x01000003) { + //AST2300-A0 + for (i = 0; i < 16; i++) { + valary[i] = Val_Array_A0[i]; + } + } + + MAC_Mode = (SCU_70h_old >> 6) & 0x3; + MAC1_1GEn = (MAC_Mode & 0x1) ? 1 : 0;//1:RGMII, 0:RMII + MAC2_1GEn = (MAC_Mode & 0x2) ? 1 : 0;//1:RGMII, 0:RMII + + MAC1_RMII = !MAC1_1GEn; + MAC2_RMII = !MAC2_1GEn; + MAC2_Valid = 1; + } + else { + MAC_Mode = (SCU_70h_old >> 6) & 0x7; + MAC1_1GEn = (MAC_Mode == 0x0) ? 1 : 0; + MAC2_1GEn = 0; + + switch ( MAC_Mode ) { + case 0 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //000: Select GMII(MAC#1) only + case 1 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 1; break; //001: Select MII (MAC#1) and MII(MAC#2) + case 2 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 1; break; //010: Select RMII(MAC#1) and MII(MAC#2) + case 3 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //011: Select MII (MAC#1) only + case 4 : MAC1_RMII = 1; MAC2_RMII = 0; MAC2_Valid = 0; break; //100: Select RMII(MAC#1) only +// case 5 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //101: Reserved + case 6 : MAC1_RMII = 1; MAC2_RMII = 1; MAC2_Valid = 1; break; //110: Select RMII(MAC#1) and RMII(MAC#2) +// case 7 : MAC1_RMII = 0; MAC2_RMII = 0; MAC2_Valid = 0; break; //111: Disable dual MAC + default: return(Finish_Check(Err_MACMode)); + } + } // End if ( AST3200 ) + + if ( SelectMAC == 0 ) { + Enable_RMII = MAC1_RMII; + MAC_1GEn = MAC1_1GEn; + + if ( Force1G & !MAC1_1GEn ) { + printf ("\nMAC1 don't support 1Gbps !!!\n"); + return( Finish_Check(Err_MACMode) ); + } + } else if (SelectMAC == 1) { + Enable_RMII = MAC2_RMII; + MAC_1GEn = MAC2_1GEn; + + if ( Force1G & !MAC2_1GEn ) { + printf ("\nMAC2 don't support 1Gbps !!!\n"); + return(Finish_Check(Err_MACMode)); + } + if ( !MAC2_Valid ) { + printf ("\nMAC2 not valid !!!\n"); + return(Finish_Check(Err_MACMode)); + } + } + else { + Enable_RMII = 1; + MAC_1GEn = 0; + + if (Force1G) { + printf ("\nMAC3/MAC4 don't support 1Gbps !!!\n"); + return(Finish_Check(Err_MACMode)); + } + } // End if ( SelectMAC == 0 ) + + if ( ModeSwitch == MODE_NSCI ) { + if (!Enable_RMII) { + printf ("\nNCSI must be RMII interface !!!\n"); + return(Finish_Check(Err_MACMode)); + } + } + + if ( GSpeed == SET_1G_100M_10MBPS ) { + GSpeed_sel[0] = MAC_1GEn; + GSpeed_sel[1] = 1; + GSpeed_sel[2] = 1; + } + + if ( AST1010 ) { + // Check bit 13:12 + Dat_ULONG = SCU_08h_old & 0x00003000; + if (Dat_ULONG != 0x00000000) + return(Finish_Check(Err_MHCLK_Ratio)); + } + else if ( AST2300 ) { + Dat_ULONG = (SCU_08h_old >> 16) & 0x7; + if (MAC1_1GEn | MAC2_1GEn) { + if ( (Dat_ULONG == 0) || (Dat_ULONG > 2) ) + return(Finish_Check(Err_MHCLK_Ratio)); + } + else { + if (Dat_ULONG != 4) + return(Finish_Check(Err_MHCLK_Ratio)); + } + } // End if (AST1010) + + //MAC + MAC_08h_old = ReadSOC_DD( H_MAC_BASE + 0x08 ); + MAC_0ch_old = ReadSOC_DD( H_MAC_BASE + 0x0c ); + MAC_40h_old = ReadSOC_DD( H_MAC_BASE + 0x40 ); + + if ( ((MAC_08h_old == 0x0000) && (MAC_0ch_old == 0x00000000)) + || ((MAC_08h_old == 0xffff) && (MAC_0ch_old == 0xffffffff)) +// || (MAC_0ch_old & 0x1) +// || (MAC_0ch_old & 0x2) + ) + { + // Load default for MAC address + SA[0] = 0x00; + SA[1] = 0x57; + SA[2] = 0x89; + SA[3] = 0x56; + SA[4] = 0x88; + SA[5] = 0x38; + } + else { + SA[0] = (MAC_08h_old >> 8) & 0xff; + SA[1] = (MAC_08h_old ) & 0xff; + SA[2] = (MAC_0ch_old >> 24) & 0xff; + SA[3] = (MAC_0ch_old >> 16) & 0xff; + SA[4] = (MAC_0ch_old >> 8) & 0xff; + SA[5] = (MAC_0ch_old ) & 0xff; + } + // printf ("%08x %08x: %02x %02x %02x %02x %02x %02x\n", MAC_08h_old, MAC_0ch_old, SA[0], SA[1], SA[2], SA[3], SA[4], SA[5]); + + if ( AST2300 ) { +#ifdef Force_Enable_NewMDIO + AST2300_NewMDIO = 1; + WriteSOC_DD(H_MAC_BASE+0x40, MAC_40h_old | 0x80000000) +#else + AST2300_NewMDIO = (MAC_40h_old & 0x80000000) ? 1 : 0; +#endif + } + else { + AST2300_NewMDIO = 0; + } // End if (AST2300) + +//------------------------------------------------------------ +// Parameter Initial +//------------------------------------------------------------ + if ( AST3200 ) { + SCU_04h = 0x0c000800; //Reset Engine + } + else if (AST1010) { + SCU_04h = 0x00000010; //Reset Engine + } + else if (AST2300) { + SCU_04h = 0x0c001800; //Reset Engine + } + else { + SCU_04h = 0x00001800; //Reset Engine + } // End if ( AST3200 ) + + if ( ModeSwitch == MODE_NSCI ) + // Set to 100Mbps and Enable RX broabcast packets and CRC_APD and Full duplex + MAC_50h = 0x000a0500; + else { + // RX_ALLADR and CRC_APD and Full duplex + MAC_50h = 0x00004500; + + #ifdef Enable_Runt + MAC_50h = MAC_50h | 0x00001000; + #endif + + #ifdef Enable_Jumbo + MAC_50h = MAC_50h | 0x00002000; + #endif + } // End if ( ModeSwitch == MODE_NSCI ) + +//------------------------------------------------------------ +// Descriptor Number +//------------------------------------------------------------ + if ( ModeSwitch == MODE_DEDICATED ) { + + #ifdef Enable_Jumbo + DES_LowNumber = 1; + #else + DES_LowNumber = IOTiming; + #endif + if ( Enable_SkipChkPHY && ( TestMode == 0 ) ) { + DES_NUMBER = 114;//for SMSC's LAN9303 issue + } + else { + if ( AST1010 | AST3200 ) { + DES_NUMBER = (IOTimingBund) ? 100 : 256; + } + else { + switch ( GSpeed ) { + case SET_1GBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325 + case SET_100MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 50 : 400; break; // 20140325 + case SET_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325 + case SET_1G_100M_10MBPS : DES_NUMBER = (IOTimingBund) ? 10 : (DES_LowNumber) ? 10 : 80; break; // 20140325 + } + } // End if ( Enable_SkipChkPHY && ( TestMode == 0 ) ) + } + + #ifdef SelectDesNumber + DES_NUMBER = SelectDesNumber; + #endif + + #ifdef USE_LPC + DES_NUMBER /= 8; + #endif + + #ifdef ENABLE_ARP_2_WOL + if ( TestMode == 4 ) { + DES_NUMBER = 1; + } + #endif + + DES_NUMBER_Org = DES_NUMBER; + + if ( DbgPrn_Info ) { + printf ("CheckBuf_MBSize : %ld\n", CheckBuf_MBSize); + printf ("LOOP_CheckNum : %ld\n", LOOP_CheckNum); + printf ("DES_NUMBER : %ld\n", DES_NUMBER); + printf ("DMA_BufSize : %ld bytes\n", DMA_BufSize); + printf ("DMA_BufNum : %d\n", DMA_BufNum); + printf ("\n"); + } +// if (3 > DMA_BufNum) +// return( Finish_Check(Err_DMABufNum) ); + + if (2 > DMA_BufNum) + return( Finish_Check(Err_DMABufNum) ); + } // End if ( ModeSwitch == MODE_DEDICATED ) + } // End if (RUN_STEP >= 1) + +//------------------------------------------------------------ +// SCU Initial +//------------------------------------------------------------ + if ( RUN_STEP >= 2 ) { + init_scu1(); + } + + if ( RUN_STEP >= 3 ) { + init_scu_macrst(); + } + +//------------------------------------------------------------ +// Data Initial +//------------------------------------------------------------ + if (RUN_STEP >= 4) { + setup_arp(); + if ( ModeSwitch == MODE_DEDICATED ) { + + FRAME_LEN = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG )); + wp_lst = (ULONG *)malloc(DES_NUMBER * sizeof( ULONG )); + + if ( !FRAME_LEN ) + return( Finish_Check( Err_MALLOC_FrmSize ) ); + + if ( !wp_lst ) + return( Finish_Check( Err_MALLOC_LastWP )); + + // Setup data and length + TestingSetup(); + } // End if ( ModeSwitch == MODE_DEDICATED ) + + // Get bit (shift) of IO driving strength register + if ( IOStrength ) { + if (AST1010) { + IOStr_max = 1;//0~1 + } + else if (AST2400) { + IOStr_max = 1;//0~1 + switch (SelectMAC) { + case 0 : IOStr_shf = 9; break; + case 1 : IOStr_shf = 11; break; + } + } + else { + IOStr_max = 3;//0~3 + switch (SelectMAC) { + case 0 : IOStr_shf = 8; break; + case 1 : IOStr_shf = 10; break; + case 2 : IOStr_shf = 12; break; + case 3 : IOStr_shf = 14; break; + } + } + } + else { + IOStr_max = 0; + IOStr_shf = 0; + } // End if (IOStrength) + + // Get current clock delay value of TX(out) and RX(in) in the SCU48 register + // and setting test range + if ( Enable_RMII ) { + switch (GRun_Mode) { + case 0 : IOdly_out_shf = 24; IOdly_in_shf = 8; break; + case 1 : IOdly_out_shf = 25; IOdly_in_shf = 12; break; + case 2 : IOdly_out_shf = 26; IOdly_in_shf = 16; break; + case 3 : IOdly_out_shf = 27; IOdly_in_shf = 20; break; + } + IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf; + IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0x1; + } + else { + switch (GRun_Mode) { + case 0 : IOdly_out_shf = 0; IOdly_in_shf = 8; break; + case 1 : IOdly_out_shf = 4; IOdly_in_shf = 12; break; + } + IOdly_in_reg = (SCU_48h_old >> IOdly_in_shf ) & 0xf; + IOdly_out_reg = (SCU_48h_old >> IOdly_out_shf) & 0xf; + } // End if ( Enable_RMII ) + + // Find the coordinate in X-Y axis + for ( index = 0; index <= 15; index++ ) + if ( IOdly_in_reg == valary[index] ) { + IOdly_in_reg_idx = index; + break; + } + for ( index = 0; index <= 15; index++ ) + if ( IOdly_out_reg == valary[index] ) { + IOdly_out_reg_idx = index; + break; + } + + // Get the range for testmargin block + if ( IOTiming ) { + if ( Enable_RMII ) { + IOdly_incval = 1; + IOdly_in_str = 0; + IOdly_in_end = 15; + IOdly_out_str = 0; + IOdly_out_end = 1; + } + else { + IOdly_incval = 1; + IOdly_in_str = 0; + IOdly_in_end = 15; + IOdly_out_str = 0; + IOdly_out_end = 15; + } + } + else if ( IOTimingBund ) { + if ( Enable_RMII ) { + IOdly_incval = 1; + IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 ); + IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 ); + IOdly_out_str = IOdly_out_reg_idx; + IOdly_out_end = IOdly_out_reg_idx; + } + else { + IOdly_incval = 1; + IOdly_in_str = IOdly_in_reg_idx - ( IOTimingBund >> 1 ); + IOdly_in_end = IOdly_in_reg_idx + ( IOTimingBund >> 1 ); + IOdly_out_str = IOdly_out_reg_idx - ( IOTimingBund >> 1 ); + IOdly_out_end = IOdly_out_reg_idx + ( IOTimingBund >> 1 ); + } + if ((IOdly_in_str < 0) || (IOdly_in_end > 15)) + return( Finish_Check( Err_IOMarginOUF ) ); + + if ((IOdly_out_str < 0) || (IOdly_out_end > 15)) + return( Finish_Check( Err_IOMarginOUF ) ); + +// if (IOdly_in_str < 0) IOdly_in_str = 0; +// if (IOdly_in_end > 15) IOdly_in_end = 15; +// if (IOdly_out_str < 0) IOdly_out_str = 0; +// if (IOdly_out_end > 15) IOdly_out_end = 15; + } + else { + IOdly_incval = 1; + IOdly_in_str = 0; + IOdly_in_end = 0; + IOdly_out_str = 0; + IOdly_out_end = 0; + } // End if (IOTiming) + } // End if (RUN_STEP >= 4) + +//------------------------------------------------------------ +// main +//------------------------------------------------------------ + if (RUN_STEP >= 5) { + #ifdef DbgPrn_FuncHeader + printf ("GSpeed_sel: %d %d %d\n", GSpeed_sel[0], GSpeed_sel[1], GSpeed_sel[2]); + Debug_delay(); + #endif + + if ( ModeSwitch == MODE_NSCI ) { + #ifdef Enable_NCSI_LOOP_INFINI + for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) { + GSpeed_org[GSpeed_idx] = GSpeed_sel[GSpeed_idx]; + } +NCSI_LOOP_INFINI:; + for ( GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++ ) { + GSpeed_sel[GSpeed_idx] = GSpeed_org[GSpeed_idx]; + } + #endif + } // End if ( ModeSwitch == MODE_NSCI ) + + for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++) { + Err_Flag_PrintEn = 1; + if ( GSpeed_sel[GSpeed_idx] ) { + // Setting the LAN speed + if ( ModeSwitch == MODE_DEDICATED ) { + + + // Test three speed of LAN, we will modify loop number + if (GSpeed == SET_1G_100M_10MBPS) { + if (GSpeed_sel[0]) LOOP_MAX = LOOP_MAX_arg; + else if (GSpeed_sel[1]) LOOP_MAX = LOOP_MAX_arg / 10; + else LOOP_MAX = LOOP_MAX_arg / 100; + + if ( !LOOP_MAX ) + LOOP_MAX = 1; + + Calculate_LOOP_CheckNum(); + } + + // Setting speed of LAN + if (GSpeed_sel[0]) MAC_50h_Speed = 0x00000200; + else if (GSpeed_sel[1]) MAC_50h_Speed = 0x00080000; + else MAC_50h_Speed = 0x00000000; + + //------------------------------------------------------------ + // PHY Initial + //------------------------------------------------------------ + if ( AST1100 ) + init_scu2(); + + if ( Enable_InitPHY ) { +#ifdef SUPPORT_PHY_LAN9303 + LAN9303(LAN9303_I2C_BUSNUM, PHY_ADR_arg, GSpeed_idx, Enable_IntLoopPHY | (BurstEnable<<1) | IEEETesting); +#else + init_phy( Enable_IntLoopPHY ); +#endif + DELAY( Delay_PHYRst * 10 ); + } // End if (Enable_InitPHY) + + if ( AST1100 ) + init_scu3(); + + if ( Err_Flag ) + return( Finish_Check( 0 ) ); + } // End if ( ModeSwitch == MODE_DEDICATED ) + + //------------------------------------------------------------ + // Start + //------------------------------------------------------------ + + // The loop is for different IO strength + for ( IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++ ) { + + // Print Header of report to monitor and log file + if ( IOTiming || IOTimingBund ) { + if ( IOStrength ) { + if ( AST1010 ) { + IOStr_val = (SCU_ach_old & 0xfff0ffff) | ((IOStr_i) ? 0xf0000 : 0x0); + } + else { + IOStr_val = (SCU_90h_old & 0xffff00ff) | (IOStr_i << IOStr_shf); + } + //printf("\nIOStrength_val= %08x, ", IOStr_val); + //printf("SCU90h: %08x ->", ReadSOC_DD(SCU_BASE+0x90)); + WriteSOC_DD( SCU_BASE + 0x90, IOStr_val ); + //printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x90)); + + #ifndef SLT_UBOOT + if (GSpeed_sel[0]) fprintf(fp_log, "[Strength %d][1G ]========================================\n", IOStr_i); + else if (GSpeed_sel[1]) fprintf(fp_log, "[Strength %d][100M]========================================\n", IOStr_i); + else fprintf(fp_log, "[Strength %d][10M ]========================================\n", IOStr_i); + #endif + } + else { + #ifndef SLT_UBOOT + if (GSpeed_sel[0]) fprintf(fp_log, "[1G ]========================================\n"); + else if (GSpeed_sel[1]) fprintf(fp_log, "[100M]========================================\n"); + else fprintf(fp_log, "[10M ]========================================\n"); + #endif + } + + if ( IOTimingBund ) + PrintIO_Header(FP_LOG); + if ( IOTiming ) + PrintIO_Header(FP_IO); + + PrintIO_Header(STD_OUT); + + } + else { + if ( ModeSwitch == MODE_DEDICATED ) { + + if (!BurstEnable) + Print_Header(FP_LOG); + + Print_Header(STD_OUT); + } + } // End if (IOTiming || IOTimingBund) + +#ifdef Enable_Old_Style + for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) { + IOdly_in = valary[IOdly_i]; +#else + for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) { + IOdly_out = valary[IOdly_j]; +#endif + + if (IOTiming || IOTimingBund) { +#ifdef Enable_Fast_SCU + #ifdef Enable_Old_Style + WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_in << IOdly_in_shf)); + #else + WriteSOC_DD(SCU_BASE + 0x48, SCU_48h_mix | (IOdly_out << IOdly_out_shf)); + #endif +#endif + + if ( IOTimingBund ) + PrintIO_LineS(FP_LOG); + if ( IOTiming ) + PrintIO_LineS(FP_IO); + + PrintIO_LineS(STD_OUT); + } // End if (IOTiming || IOTimingBund) + + //------------------------------------------------------------ + // SCU Initial + //------------------------------------------------------------ +#ifdef Enable_Fast_SCU + init_scu_macrst(); +#endif +#ifdef Enable_Old_Style + for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) { + IOdly_out = valary[IOdly_j]; +#else + for (IOdly_i = IOdly_in_str; IOdly_i <= IOdly_in_end; IOdly_i+=IOdly_incval) { + IOdly_in = valary[IOdly_i]; +#endif + if ( IOTiming || IOTimingBund ) { + IOdly_val = (IOdly_in << IOdly_in_shf) | (IOdly_out << IOdly_out_shf); + +//printf("\nIOdly_val= %08x, ", IOdly_val); +//printf("SCU48h: %08x ->", ReadSOC_DD( SCU_BASE + 0x48 ) ); + WriteSOC_DD( SCU_BASE + 0x48, SCU_48h_mix | IOdly_val ); +//printf(" %08x\n", ReadSOC_DD(SCU_BASE+0x48)); + } // End if (IOTiming || IOTimingBund) + + //------------------------------------------------------------ + // SCU Initial + //------------------------------------------------------------ +#ifdef Enable_Fast_SCU +#else + init_scu_macrst(); +#endif + + //------------------------------------------------------------ + // MAC Initial + //------------------------------------------------------------ + init_mac(H_MAC_BASE, H_TDES_BASE, H_RDES_BASE); + if ( Err_Flag ) + return( Finish_Check(0) ); + + // Testing + if ( ModeSwitch == MODE_NSCI ) + dlymap[IOdly_i][IOdly_j] = phy_ncsi(); + else + dlymap[IOdly_i][IOdly_j] = TestingLoop(LOOP_CheckNum); + + + // Display to Log file and monitor + if ( IOTiming || IOTimingBund ) { + + if ( IOTimingBund ) + PrintIO_Line(FP_LOG); + + if ( IOTiming ) + PrintIO_Line(FP_IO); + + PrintIO_Line(STD_OUT); + + // Find the range of current setting + if ( ( IOdly_in_reg == IOdly_in ) && ( IOdly_out_reg == IOdly_out ) ) { + IOdly_i_min = IOdly_i - ( IOTimingBund >> 1 ); + IOdly_i_max = IOdly_i + ( IOTimingBund >> 1 ); + + if ( Enable_RMII ) { + IOdly_j_min = IOdly_j; + IOdly_j_max = IOdly_j; + } + else { + IOdly_j_min = IOdly_j - (IOTimingBund >> 1 ); + IOdly_j_max = IOdly_j + (IOTimingBund >> 1 ); + } + } + + PrintIO_Line_LOG(); + FPri_ErrFlag(FP_LOG); + +// Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag; + Err_Flag = 0; + } + }// End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) +#ifndef SLT_UBOOT + if ( IOTiming || IOTimingBund ) { + if ( IOTimingBund ) + fprintf(fp_log, "\n"); + if (IOTiming ) + fprintf(fp_io, "\n"); + } +#endif + printf("\n"); + } // End for (IOdly_j = IOdly_out_str; IOdly_j <= IOdly_out_end; IOdly_j+=IOdly_incval) + + //------------------------------------------------------------ + // End + //------------------------------------------------------------ + + if ( IOTiming || IOTimingBund ) { + if ( ( IOdly_i_min < 0 ) || ( IOdly_i_max > 15 ) ) + FindErr(Err_IOMarginOUF); + if ( ( IOdly_j_min < 0 ) || ( IOdly_j_max > 15 ) ) + FindErr(Err_IOMarginOUF); + + if ( IOdly_i_min < 0 ) IOdly_i_min = 0; + if ( IOdly_i_max > 15 ) IOdly_i_max = 15; + if ( IOdly_j_min < 0 ) IOdly_j_min = 0; + if ( IOdly_j_max > 15 ) IOdly_j_max = 15; + +#ifdef Enable_Old_Style + for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++) + for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++) +#else + for (IOdly_j = IOdly_j_min; IOdly_j <= IOdly_j_max; IOdly_j++) + for (IOdly_i = IOdly_i_min; IOdly_i <= IOdly_i_max; IOdly_i++) +#endif + { + if ( dlymap[IOdly_i][IOdly_j] ) { +#ifdef SLT_DOS + if ( IOTiming ) { +#ifdef Enable_Old_Style + for (i = IOdly_i_min; i <= IOdly_i_max; i++) +#else + for (j = IOdly_j_min; j <= IOdly_j_max; j++) +#endif + { +#ifdef Enable_Old_Style + for (j = IOdly_j_min; j <= IOdly_j_max; j++) +#else + for (i = IOdly_i_min; i <= IOdly_i_max; i++) +#endif + { + if (dlymap[i][j]) fprintf(fp_io, "x "); + else fprintf(fp_io, "o "); + } + fprintf(fp_io, "\n"); + } + } // End if ( IOTiming ) +#endif // End SLT_DOS + FindErr(Err_IOMargin); + goto Find_Err_IOMargin; + } // End if ( dlymap[IOdly_i][IOdly_j] ) + } + } // End if ( IOTiming || IOTimingBund ) + +Find_Err_IOMargin:; + if ( !BurstEnable ) + FPri_ErrFlag(FP_LOG); + if ( IOTiming ) + FPri_ErrFlag(FP_IO); + + FPri_ErrFlag(STD_OUT); + + Err_Flag_allapeed = Err_Flag_allapeed | Err_Flag; + Err_Flag = 0; + } // End for (IOStr_i = 0; IOStr_i <= IOStr_max; IOStr_i++) + + if ( ModeSwitch == MODE_DEDICATED ) { + if ( Enable_InitPHY & !Disable_RecovPHY ) + recov_phy(Enable_IntLoopPHY); + } + + GSpeed_sel[GSpeed_idx] = 0; + } // End if (GSpeed_sel[GSpeed_idx]) + + Err_Flag_PrintEn = 0; + } // End for (GSpeed_idx = 0; GSpeed_idx < 3; GSpeed_idx++) + + Err_Flag = Err_Flag_allapeed; + + if ( ModeSwitch == MODE_NSCI ) { + #ifdef Enable_NCSI_LOOP_INFINI + if (Err_Flag == 0) { + if (fp_log) { + fclose(fp_log); + fp_log = fopen(FileName,"w"); + } + goto NCSI_LOOP_INFINI; + } + #endif + } + + } // End if (RUN_STEP >= 5) + + return(Finish_Check(0)); + +} diff --git a/arch/arm/cpu/arm926ejs/aspeed/reset.c b/arch/arm/cpu/arm926ejs/aspeed/reset.c new file mode 100644 index 0000000..ce8dba1 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/reset.c @@ -0,0 +1,24 @@ +/* + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <common.h> +#include <asm/io.h> + +#define AST_WDT_BASE 0x1e785000 +void reset_cpu(ulong addr) +{ + __raw_writel(0x10 , AST_WDT_BASE+0x04); + __raw_writel(0x4755, AST_WDT_BASE+0x08); + __raw_writel(0x23, AST_WDT_BASE+0x0c); /* reset the full chip */ + + while (1) + /*nothing*/; +} diff --git a/arch/arm/cpu/arm926ejs/aspeed/timer.c b/arch/arm/cpu/arm926ejs/aspeed/timer.c new file mode 100644 index 0000000..add4c0e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/aspeed/timer.c @@ -0,0 +1,135 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if CONFIG_ASPEED_TIMER_CLK < CONFIG_SYS_HZ +#error "CONFIG_ASPEED_TIMER_CLK must be as large as CONFIG_SYS_HZ" +#endif + +#define TIMER_LOAD_VAL 0xffffffff +#define CLK_PER_HZ (CONFIG_ASPEED_TIMER_CLK / CONFIG_SYS_HZ) + +/* macro to read the 32 bit timer */ +#define READ_CLK (*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0)) +#define READ_TIMER (READ_CLK / CLK_PER_HZ) + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 4) = TIMER_LOAD_VAL; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x30) = 0x3; /* enable timer1 */ + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + ulong last = READ_CLK; + ulong clks; + ulong elapsed = 0; + + /* translate usec to clocks */ + clks = (usec / 1000) * CLK_PER_HZ; + clks += (usec % 1000) * CLK_PER_HZ / 1000; + + while (clks > elapsed) { + ulong now = READ_CLK; + if (now <= last) { + elapsed += last - now; + } else { + elapsed += TIMER_LOAD_VAL - (now - last); + } + last = now; + } +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + (TIMER_LOAD_VAL / CLK_PER_HZ) - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + __udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + return CONFIG_SYS_HZ; +} |
