diff options
Diffstat (limited to 'arch/arm/mach-aspeed')
53 files changed, 5646 insertions, 0 deletions
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 0000000..b3ea0a0 --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,229 @@ +if ARCH_ASPEED + +choice + prompt "ASPEED Processor Family" + default CONFIG_IRMP + +config IRMP + bool "IRMP Serials" + +config PCEXT + bool "PC Extender Serials" + +config REMOTEFX + bool "RemoteFX Zero-Client Serials" + +endchoice + +if IRMP + +choice + prompt "IRMP Serials" + default CONFIG_ARCH_AST2300 + +config ARCH_AST1100 + bool "AST1100" + +config ARCH_AST2100 + bool "AST2100" + +config ARCH_AST2200 + bool "AST2200" + +config ARCH_AST2300 + bool "AST2300" + +config ARCH_AST2400 + select USB_ARCH_HAS_EHCI + bool "AST2400" + +config ARCH_AST2500 + select USB_ARCH_HAS_EHCI + bool "AST2500" + +endchoice + +endif + +if PCEXT + +choice + prompt "PC Extender Serials" + default CONFIG_ARCH_AST1510 + +config ARCH_AST1500 + bool "AST1500" + +config ARCH_AST1510 + bool "AST1510" + +config ARCH_AST1520 + select USB_ARCH_HAS_EHCI + bool "AST1520" + +endchoice + +endif + +if REMOTEFX + +choice + prompt "RemoteFX Zero-Client Serials" + default CONFIG_ARCH_AST3100 + +config ARCH_AST3100 + select USB_ARCH_HAS_EHCI + bool "AST3100" + +config ARCH_AST3200 + select USB_ARCH_HAS_EHCI + bool "AST3200" + +endchoice + +endif + +menu "FLASH Chip Select" + +choice + prompt "CS0 Config" + default CONFIG_AST_CS0_SPI + +config AST_CS0_NOR + bool "NOR" + +config AST_CS0_NAND + bool "NAND" + +config AST_CS0_SPI + bool "SPI_NOR" + +config AST_CS0_NONE + bool "NONE" + +endchoice + +choice + prompt "CS1 Config" + default CONFIG_AST_CS1_SPI + +config AST_CS1_NOR + bool "NOR" + +config AST_CS1_NAND + bool "NAND" + +config AST_CS1_SPI + bool "SPI_NOR" + +config AST_CS1_NONE + bool "NONE" + +endchoice + +choice + prompt "CS2 Config" + default CONFIG_AST_CS2_SPI + +config AST_CS2_NOR + bool "NOR" + +config AST_CS2_NAND + bool "NAND" + +config AST_CS2_SPI + bool "SPI_NOR" + +config AST_CS2_NONE + bool "NONE" + +endchoice + +choice + prompt "CS3 Config" + default CONFIG_AST_CS3_SPI + +config AST_CS3_NOR + bool "NOR" + +config AST_CS3_NAND + bool "NAND" + +config AST_CS3_SPI + bool "SPI_NOR" + +config AST_CS3_NONE + bool "NONE" + +endchoice + +choice + prompt "CS4 Config" + default CONFIG_AST_CS4_SPI + +config AST_CS4_NOR + bool "NOR" + +config AST_CS4_NAND + bool "NAND" + +config AST_CS4_SPI + bool "SPI_NOR" + +config AST_CS4_NONE + bool "NONE" + +endchoice + +endmenu + +config ARCH_AST1070 + bool "AST1070 Comapnion chip combination" + +config AST1070_NR + int "Number of AST1070 Comapniion Chip combination" + depends on ARCH_AST1070 + default "1" + help + Set this to the number of ast1070 + +choice + prompt "Connect Bus Interface" + depends on ARCH_AST1070 + default CONFIG_AST_LPC_PLUS + +config AST_LPC_PLUS + bool "LPC PLUS" + +config AST_LPC + bool "LPC" + +endchoice + +config AST_SCU_LOCK + bool "AST SCU Protection Key" + +config WEDGE + bool "Facebook Wedge/6-Pack" + +config WEDGE100 + bool "Facebook Wedge100" + +config YOSEMITE + bool "Facebook Yosemite" + +config FBPLATFORM1 + bool "Facebook Platform1" + +config ASUSPLATFORM + bool "ASUS ASMB4 Platforms" + +# Support PCIE +config PCIE + bool "ASPEED PCIE support" + depends on PCI && ARCH_ASPEED + select ARCH_SUPPORTS_MSI + help + Socle PCIE support + +endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 0000000..bb958ad --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,22 @@ +# +# Makefile for the linux kernel. +# + +# Common support (must be linked before board specific support) + +# Specific board support +obj-$(CONFIG_ARCH_AST1100) += ast1100.o +obj-$(CONFIG_ARCH_AST2100) += ast2100.o gpio.o ast-lpc.o +obj-$(CONFIG_ARCH_AST2300) += ast2300.o gpio.o ast-lpc.o +obj-$(CONFIG_ARCH_AST2400) += ast2400.o gpio.o ast-lpc.o ast-lpc_plus.o +obj-$(CONFIG_ARCH_AST2500) += ast2500.o ast-mctp.o +#PC Ext +obj-$(CONFIG_ARCH_AST1510) += ast1510.o gpio.o +obj-$(CONFIG_ARCH_AST1520) += ast1520.o ast-mctp.o + +#RemoteFx Zero client +obj-$(CONFIG_ARCH_AST3100) += ast3100.o gpio.o +obj-$(CONFIG_ARCH_AST3200) += ast3200.o ast-mctp.o + +#BMC Comapnion Controller +obj-$(CONFIG_ARCH_AST1070) += ast1070.o diff --git a/arch/arm/mach-aspeed/Makefile.boot b/arch/arm/mach-aspeed/Makefile.boot new file mode 100644 index 0000000..f8eed93 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile.boot @@ -0,0 +1,48 @@ +ifeq ($(CONFIG_ARCH_AST1510),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2100),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2300),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2400),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST2500),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + +ifeq ($(CONFIG_ARCH_AST3100),y) + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 +endif + +ifeq ($(CONFIG_ARCH_AST1520),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + +ifeq ($(CONFIG_ARCH_AST3200),y) + zreladdr-y := 0x80008000 +params_phys-y := 0x80000100 +initrd_phys-y := 0x80800000 +endif + diff --git a/arch/arm/mach-aspeed/ast-lpc.c b/arch/arm/mach-aspeed/ast-lpc.c new file mode 100644 index 0000000..cf86d7f --- /dev/null +++ b/arch/arm/mach-aspeed/ast-lpc.c @@ -0,0 +1,423 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-lpc.c +* Author : Ryan Chen +* Description : AST LPC +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> +#include <linux/interrupt.h> + +#include <mach/hardware.h> + +#include <plat/regs-lpc.h> +#include <plat/ast-snoop.h> +#include <plat/ast-lpc.h> +#ifdef CONFIG_ARCH_AST1070 +#include <plat/ast1070-scu.h> +#include <plat/ast1070-devs.h> +#include <plat/regs-ast1070-intc.h> +#include <plat/ast1070-uart-dma.h> +#endif + +//#define AST_LPC_DEBUG + +#ifdef AST_LPC_DEBUG +#define LPCDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define LPCDBUG(fmt, args...) +#endif + +#if 0 +static inline u32 +ast_lpc_read(u32 reg) +{ + u32 val; + + val = readl(ast_lpc_base + reg); + + LPCDBUG("ast_lpc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_lpc_write(u32 val, u32 reg) +{ + LPCDBUG("ast_lpc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); + writel(val, ast_lpc_base + reg); +} + +/******************************************************************************/ + +//Suppose you are going to snoop 0x80 ~ 0x87 +//snoop_init(0x80, 0x7, WORD_MODE, buf_dma, (SNOOP_DMA_BOUNDARY / 4)); //register in unit of DWORD +#if 0 +extern void +ast_lpc_snoop_dma_enable(u16 port_number, u8 port_mask, u8 mode, dma_addr_t dma_base, u16 size) +{ + write_register(0x1e789134, (port_mask << 16) + port_number); + write_register(0x1e7890d0, dma_base); + write_register(0x1e7890d4, (size - 1)); + write_register(0x1e789130, (mode << 4) | ENABLE_DMA_INTERRUPT | ENABLE_POST_CODE_FUNCTION | ENABLE_SNOOP_DMA_MODE); + + //Enable error interrupt to check LPC reset + write_register_or(0x1e789008, 1); + +} + +EXPORT_SYMBOL(ast_lpc_snoop_dma_init); +#endif + +extern irqreturn_t ast_snoop_handler(int this_irq, void *dev_id) +{ + u32 snoop_sts; + struct ast_snoop *snoop = dev_id; + + snoop_sts = ast_lpc_read(AST_LPC_HICR6); + if((snoop_sts & (LPC_HICR6_STR_SNP1W | LPC_HICR6_STR_SNP0W)) == 0) + return IRQ_NONE; + + if(snoop_sts & LPC_HICR6_STR_SNP0W) { + snoop->snoop_ch0->snoop_data = GET_LPC_SNPD0(ast_lpc_read(AST_LPC_SNPWDR)); + //clear + ast_lpc_write(LPC_HICR6_STR_SNP0W, AST_LPC_HICR6); + } + + if(snoop_sts & LPC_HICR6_STR_SNP1W) { + snoop->snoop_ch1->snoop_data = GET_LPC_SNPD1(ast_lpc_read(AST_LPC_SNPWDR)); + //clear + ast_lpc_write(LPC_HICR6_STR_SNP1W, AST_LPC_HICR6); + + } + + return IRQ_HANDLED; + +} +EXPORT_SYMBOL(ast_snoop_handler); + +extern irqreturn_t ast_snoop_dma_handler(int this_irq, void *dev_id) +{ + u32 snoop_dma_sts, lpc_sts; + struct ast_snoop_dma_channel *snoop_dma_ch = dev_id; + + snoop_dma_sts = ast_lpc_read(AST_LPC_PCCR2); + + lpc_sts = ast_lpc_read(AST_LPC_HICR2); + + printk("ISR : snoop_dma_sts = %x , lpc_sts = %x \n",snoop_dma_sts, lpc_sts); + + if(lpc_sts & LPC_LRST) { + printk("LPC RST === > \n"); + //clear fifo ?? + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) | LPC_RX_FIFO_CLR, AST_LPC_PCCR0); + //clear + ast_lpc_write(lpc_sts & ~LPC_LRST, AST_LPC_HICR2); + + } + + if(snoop_dma_sts & LPC_POST_CODE_DMA_RDY) { + + + } + + + return IRQ_HANDLED; + +} +EXPORT_SYMBOL(ast_snoop_dma_handler); + +extern void ast_snoop_channel_int_enable(struct ast_snoop_channel *ast_ch, u8 enable) +{ + printk("ch[%d]int : %s , snoop port : %x",ast_ch->snoop_ch, enable? "Enable":"Disable", ast_ch->snoop_port); + + if(enable) { + switch(ast_ch->snoop_ch) { + case 0: + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0INT_EN, + AST_LPC_HICR5); + break; + case 1: + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + break; + }; + + } else { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0INT_EN, + AST_LPC_HICR5); + + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + }; + + } + +} +EXPORT_SYMBOL(ast_snoop_channel_int_enable); + +extern void ast_snoop_channel_enable(struct ast_snoop_channel *ast_ch, u8 enable) +{ + printk("ch[%d] : %s , snoop port : %x",ast_ch->snoop_ch, enable? "Enable":"Disable", ast_ch->snoop_port); + + if(enable) { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_SNPWADR) & ~LPC_SNOOP_ADDR0_MASK) | + ast_ch->snoop_port, + AST_LPC_SNPWADR); + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_SNPWADR) & ~LPC_SNOOP_ADDR1_MASK) | + ast_ch->snoop_port, + AST_LPC_SNPWADR); + //enable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + break; + }; + + } else { + switch(ast_ch->snoop_ch) { + case 0: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP0W_EN, + AST_LPC_HICR5); + + break; + case 1: + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) & ~LPC_HICR5_SNP1W_EN, + AST_LPC_HICR5); + + }; + + } + +} +EXPORT_SYMBOL(ast_snoop_channel_enable); + +extern void ast_snoop_dma_ch_enable(struct ast_snoop_dma_channel *ast_dma_ch, u8 enable) +{ + printk("ch[%d] : %s , snoop port : %x",ast_dma_ch->snoop_ch, enable? "Enable":"Disable", ast_dma_ch->snoop_port); + + if(enable) { + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_EN, + AST_LPC_PCCR0); + + //set port address + ast_lpc_write((ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_ADDR_MASK) | + LPC_CAPTURE_ADDR_MASK(ast_dma_ch->snoop_mask) | + LPC_CAPTURE_BASE_ADDR(ast_dma_ch->snoop_port), + AST_LPC_PCCR0); + + ast_lpc_write(ast_dma_ch->dma_addr, AST_LPC_PCCR4); + ast_lpc_write(ast_dma_ch->dma_size - 1 , AST_LPC_PCCR5); + + //enable + ast_lpc_write((ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_MODE_MASK) | + LPC_POST_CODE_MODE(ast_dma_ch->snoop_mode) | + LPC_POST_DMA_MODE_EN | + LPC_POST_CODE_EN, + AST_LPC_PCCR0); + + } else { + //disable + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) & ~LPC_POST_CODE_EN, + AST_LPC_PCCR0); + } + +} +EXPORT_SYMBOL(ast_snoop_dma_ch_enable); + +extern int ast_snoop_init(struct ast_snoop *snoop) +{ + int ret=0; + + ast_snoop_channel_enable(snoop->snoop_ch0, 1); + ast_snoop_channel_enable(snoop->snoop_ch1, 1); + //request irq + ret = request_irq(IRQ_LPC, ast_snoop_handler, IRQF_SHARED, + "ast-snoop", snoop); + + //enable irq + ast_lpc_write(ast_lpc_read(AST_LPC_HICR5) | LPC_HICR5_SNP0INT_EN | LPC_HICR5_SNP1INT_EN, + AST_LPC_HICR5); + return ret; +} +EXPORT_SYMBOL(ast_snoop_init); + +extern void ast_snoop_dma_init(struct ast_snoop_dma_channel *ast_dma_ch) +{ + int ret=0; + + ast_snoop_dma_ch_enable(ast_dma_ch, 1); + + //request irq + ret = request_irq(IRQ_LPC, ast_snoop_dma_handler, IRQF_SHARED, + "ast-snoop", ast_dma_ch); + + //enable irq + ast_lpc_write(ast_lpc_read(AST_LPC_PCCR0) | + LPC_POST_DMA_INT_EN, + AST_LPC_PCCR0); + + return ret; + +} +EXPORT_SYMBOL(ast_snoop_dma_init); +#endif +static struct ast_lpc_driver_data *lpc_driver_data; + +static int __devinit ast_lpc_probe(struct platform_device *pdev) +{ +// const struct platform_device_id *id = platform_get_device_id(pdev); + struct resource *res; + int ret = 0; + + lpc_driver_data = kzalloc(sizeof(struct ast_lpc_driver_data), GFP_KERNEL); + if (lpc_driver_data == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + lpc_driver_data->pdev = pdev; + + lpc_driver_data->bus_info = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free; + } + + res = request_mem_region(res->start, resource_size(res), pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free; + } + + lpc_driver_data->reg_base = ioremap(res->start, resource_size(res)); + if (lpc_driver_data->reg_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + +#ifdef CONFIG_ARCH_AST1070 + int i; + if(lpc_driver_data->bus_info->bus_scan) { + printk("LPC Scan Device... \n"); + for(i=0;i<lpc_driver_data->bus_info->scan_node;i++) { + ast1070_scu_init(i ,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + printk("C%d-[%x] ", i, ast1070_revision_id_info(i)); + ast1070_vic_init(i, (lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000), IRQ_C0_VIC_CHAIN + i, IRQ_C0_VIC_CHAIN_START + (i*AST_CVIC_NUM)); + ast1070_scu_dma_init(i); + ast1070_uart_dma_init(i, lpc_driver_data->bus_info->bridge_phy_addr); + ast_add_device_cuart(i,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + ast_add_device_ci2c(i,lpc_driver_data->bus_info->bridge_phy_addr + i*0x10000); + } + printk("\n"); + + } + +#endif + + platform_set_drvdata(pdev, lpc_driver_data); + return 0; + +err_free_mem: + release_mem_region(res->start, resource_size(res)); +err_free: + kfree(lpc_driver_data); + + return ret; +} + +static int __devexit ast_lpc_remove(struct platform_device *pdev) +{ + struct ast_lpc_driver_data *lpc_driver_data; + struct resource *res; + + lpc_driver_data = platform_get_drvdata(pdev); + if (lpc_driver_data == NULL) + return -ENODEV; + + iounmap(lpc_driver_data->reg_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + kfree(lpc_driver_data); + + return 0; +} + +static struct platform_driver ast_lpc_driver = { + .driver = { + .name = "ast_lpc", + .owner = THIS_MODULE, + }, + .probe = ast_lpc_probe, + .remove = __devexit_p(ast_lpc_remove), +// .id_table = pwm_id_table, +}; + +static int __init ast_lpc_init(void) +{ + return platform_driver_register(&ast_lpc_driver); +} +arch_initcall(ast_lpc_init); + +static void __exit ast_lpc_exit(void) +{ + platform_driver_unregister(&ast_lpc_driver); +} +module_exit(ast_lpc_exit); + +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-aspeed/ast-lpc_plus.c b/arch/arm/mach-aspeed/ast-lpc_plus.c new file mode 100644 index 0000000..187b8b8 --- /dev/null +++ b/arch/arm/mach-aspeed/ast-lpc_plus.c @@ -0,0 +1,182 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-lpc_plus.c +* Author : Ryan Chen +* Description : AST LPC +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2013/05/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> +#include <linux/interrupt.h> + +#include <mach/hardware.h> + +#include <plat/regs-lpc.h> +#include <plat/ast-snoop.h> +#include <plat/ast-lpc.h> +#ifdef CONFIG_ARCH_AST1070 +#include <plat/ast1070-scu.h> +#include <plat/ast1070-devs.h> +#include <plat/regs-ast1070-intc.h> +#include <plat/ast1070-uart-dma.h> +#endif + +//#define AST_LPCP_DEBUG + +#ifdef AST_LPCP_DEBUG +#define LPCP_DBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define LPCP_DBUG(fmt, args...) +#endif + +#if 0 +static inline u32 +ast_lpc_plus_write(u32 reg) +{ + u32 val; + + val = readl(ast_lpc_base + reg); + + LPCDBUG("ast_lpc_read : reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_lpc_plus_write(u32 val, u32 reg) +{ + LPCDBUG("ast_lpc_write : reg = 0x%08x, val = 0x%08x\n", reg, val); + writel(val, ast_lpc_base + reg); +} +#endif + +static int __devinit ast_lpc_plus_probe(struct platform_device *pdev) +{ + static struct ast_lpc_driver_data *lpc_plus_driver_data; +// const struct platform_device_id *id = platform_get_device_id(pdev); + struct resource *res; + int ret = 0; + int i; + + lpc_plus_driver_data = kzalloc(sizeof(struct ast_lpc_driver_data), GFP_KERNEL); + if (lpc_plus_driver_data == NULL) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + lpc_plus_driver_data->pdev = pdev; + + lpc_plus_driver_data->bus_info = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + ret = -ENODEV; + goto err_free; + } + + res = request_mem_region(res->start, resource_size(res), pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + ret = -EBUSY; + goto err_free; + } + + lpc_plus_driver_data->reg_base = ioremap(res->start, resource_size(res)); + if (lpc_plus_driver_data->reg_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap() registers\n"); + ret = -ENODEV; + goto err_free_mem; + } + +#ifdef CONFIG_ARCH_AST1070 + if(lpc_plus_driver_data->bus_info->bus_scan) { + printk("LPC PLUS Scan Device... "); + for(i=0;i<lpc_plus_driver_data->bus_info->scan_node;i++) { + ast1070_scu_init(i ,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + printk("C%d-[%x] ", i, ast1070_revision_id_info(i)); + ast1070_vic_init(i, (lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000), IRQ_C0_VIC_CHAIN + i, IRQ_C0_VIC_CHAIN_START + (i*AST_CVIC_NUM)); + ast1070_scu_dma_init(i); + ast1070_uart_dma_init(i, lpc_plus_driver_data->bus_info->bridge_phy_addr); + ast_add_device_cuart(i,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + ast_add_device_ci2c(i,lpc_plus_driver_data->bus_info->bridge_phy_addr + i*0x10000); + } + printk("\n"); + + } + +#endif + + platform_set_drvdata(pdev, lpc_plus_driver_data); + return 0; + +err_free_mem: + release_mem_region(res->start, resource_size(res)); +err_free: + kfree(lpc_plus_driver_data); + + return ret; +} + +static int __devexit ast_lpc_plus_remove(struct platform_device *pdev) +{ + struct ast_lpc_driver_data *lpc_plus_driver_data; + struct resource *res; + + lpc_plus_driver_data = platform_get_drvdata(pdev); + if (lpc_plus_driver_data == NULL) + return -ENODEV; + + iounmap(lpc_plus_driver_data->reg_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + + kfree(lpc_plus_driver_data); + + return 0; +} + +static struct platform_driver ast_lpc_plus_driver = { + .driver = { + .name = "ast_lpc_plus", + .owner = THIS_MODULE, + }, + .probe = ast_lpc_plus_probe, + .remove = __devexit_p(ast_lpc_plus_remove), +// .id_table = pwm_id_table, +}; + +static int __init ast_lpc_plus_init(void) +{ + return platform_driver_register(&ast_lpc_plus_driver); +} +arch_initcall(ast_lpc_plus_init); + +static void __exit ast_lpc_plus_exit(void) +{ + platform_driver_unregister(&ast_lpc_plus_driver); +} +module_exit(ast_lpc_plus_exit); + +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-aspeed/ast-mctp.c b/arch/arm/mach-aspeed/ast-mctp.c new file mode 100644 index 0000000..1dd746b --- /dev/null +++ b/arch/arm/mach-aspeed/ast-mctp.c @@ -0,0 +1,153 @@ +/******************************************************************************** +* File Name : arch/arm/mach-aspeed/ast-mctp.c +* Author : Ryan Chen +* Description : AST MCTP Ctrl +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +* History : +* 1. 2013/07/15 Ryan Chen Create +* +********************************************************************************/ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <mach/platform.h> +#include <asm/io.h> + +#include <mach/hardware.h> +#include <plat/regs-mctp.h> +#include <plat/ast_mctp.h> + +//#define AST_MCTP_DEBUG 1 + +#ifdef AST_MCTP_DEBUG +#define MCTPDBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#else +#define MCTPDBUG(fmt, args...) +#endif + +static u32 ast_mctp_base = 0; +static u8 txTag = 0; +static inline u32 +ast_mctp_read(u32 reg) +{ + u32 val; + + val = readl(ast_mctp_base + reg); + + MCTPDBUG("reg = 0x%08x, val = 0x%08x\n", reg, val); + + return val; +} + +static inline void +ast_mctp_write(u32 val, u32 reg) +{ + MCTPDBUG("reg = 0x%08x, val = 0x%08x\n", reg, val); + + writel(val, ast_mctp_base + reg); +} + +//***********************************Information *********************************** + +extern void ast_pcie_cfg_read(u8 type, u32 bdf_offset, u32 *value) +{ + u32 timeout =0; + u32 desc3,desc2; + txTag %= 0xf; +// printf("type = %d, busfunc = %x \n",type, bdf); + if((ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE) != 0) + printk("EEEEEEEE \n"); + + ast_mctp_write(0x4000001 | (type << 24), AST_MCTP_TX_DESC3); + ast_mctp_write(0x200f | (txTag << 8), AST_MCTP_TX_DESC2); + ast_mctp_write(bdf_offset, AST_MCTP_TX_DESC1); + ast_mctp_write(0, AST_MCTP_TX_DESC0); +// ast_mctp_write(0, AST_MCTP_TX_DATA); + + //trigger + ast_mctp_write(7, AST_MCTP_CTRL); + //wait +// printf("trigger \n"); + while(!(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE)) { + timeout++; + if(timeout > 10000) { + printk("time out \n"); + *value = 0xffffffff; + goto out; + } + }; + + //read + desc3 = ast_mctp_read(AST_MCTP_RX_DESC3); + desc2 = ast_mctp_read(AST_MCTP_RX_DESC2); + ast_mctp_read(AST_MCTP_RX_DESC1); + + if( ((desc3 >> 24) == 0x4A) && + ((desc3 & 0xfff) == 0x1) && + ((desc2 & 0xe000) == 0)) { + *value = ast_mctp_read(AST_MCTP_RX_DATA); + + } else { + *value = 0xffffffff; + + } + +out: + txTag++; + ast_mctp_write(0x15, AST_MCTP_CTRL); + ast_mctp_write(0x3, AST_MCTP_INT); + //wait + while(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE); + +} + +extern void ast_pcie_cfg_write(u8 type, u32 bdf_offset, u32 data) +{ + txTag %= 0xf; + + ast_mctp_write(0x44000001 | (type << 24), AST_MCTP_TX_DESC3); + ast_mctp_write(0x200f | (txTag << 8), AST_MCTP_TX_DESC2); + ast_mctp_write(bdf_offset, AST_MCTP_TX_DESC1); + ast_mctp_write(0, AST_MCTP_TX_DESC0); + ast_mctp_write(data, AST_MCTP_TX_DATA); + + //trigger + ast_mctp_write(7, AST_MCTP_CTRL); +// printf("trigger \n"); + //wait + while(!(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE)); + + //read + ast_mctp_read(AST_MCTP_RX_DESC3); + ast_mctp_read(AST_MCTP_RX_DESC2); + ast_mctp_read(AST_MCTP_RX_DESC1); + txTag++; + ast_mctp_write(0x15, AST_MCTP_CTRL); + ast_mctp_write(0x3, AST_MCTP_INT); + //wait + while(ast_mctp_read(AST_MCTP_INT) & MCTP_RX_COMPLETE); + +} + +static int __init ast_mctp_init(void) +{ + MCTPDBUG("\n"); + ast_mctp_base = (u32)ioremap(AST_MCTP_BASE , SZ_256); + return 0; +} + +subsys_initcall(ast_mctp_init); + diff --git a/arch/arm/mach-aspeed/ast1070.c b/arch/arm/mach-aspeed/ast1070.c new file mode 100644 index 0000000..12ede8b --- /dev/null +++ b/arch/arm/mach-aspeed/ast1070.c @@ -0,0 +1,60 @@ +/* + * linux/arch/arm/mach-ast1070/ast1070.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <plat/devs.h> +#include <plat/ast1070-scu.h> +#include <plat/ast1070-uart-dma.h> +#include <mach/time.h> +#include <mach/gpio.h> + +static int __init ast1070_init(void) +{ + int i=0; + u8 num = 0; + if(gpio_get_value(PIN_GPIOI2)) + num = 2; //dual 1070 + else + num = 1; //single 1070 + + if(CONFIG_AST1070_NR != num) + printk("Please check Configuration !!! \n"); + +#if 0 + if(gpio_get_value(PIN_GPIOI1)) + printk("Use LPC+ Bus Access \n"); + else + printk("Use LPC Bus Access \n"); +#endif + + for(i=0; i< CONFIG_AST1070_NR;i++) { + ast1070_scu_revision_id(i); + ast1070_dma_init(i); + ast1070_uart_dma_init(i); + } + + return 0; +} + +subsys_initcall(ast1070_init); + diff --git a/arch/arm/mach-aspeed/ast1100.c b/arch/arm/mach-aspeed/ast1100.c new file mode 100644 index 0000000..e2629f1 --- /dev/null +++ b/arch/arm/mach-aspeed/ast1100.c @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-ast2000/ast2000.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <mach/time.h> + +extern void aspeed_map_io(void); +extern void aspeed_init_irq(void); +extern struct sys_timer aspeed_timer; + +static void __init aspeed_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST1100") + .phys_io = ASPEED_IO_START, +// .phys_ram = ASPEED_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(IO_START)>>18) & 0xfffc, + .map_io = aspeed_map_io, + .timer = &aspeed_timer, + .init_irq = aspeed_init_irq, + .init_machine = aspeed_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2100.c b/arch/arm/mach-aspeed/ast2100.c new file mode 100644 index 0000000..a4a2d9c --- /dev/null +++ b/arch/arm/mach-aspeed/ast2100.c @@ -0,0 +1,152 @@ +/* + * linux/arch/arm/mach-ast2100/ast2100.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/sysdev.h> +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/time.h> +#include <mach/hardware.h> +#include <plat/devs.h> + +#include "core.h" + +extern void ast_map_io(void); +extern void ast_init_irq(void); +extern struct sys_timer ast_timer; + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDMC_BASE), + .pfn = __phys_to_pfn(AST_SDMC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIDEO_BASE), + .pfn = __phys_to_pfn(AST_VIDEO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC0_BASE), + .pfn = __phys_to_pfn(AST_MAC0_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UDC11_BASE ), + .pfn = __phys_to_pfn(AST_UDC11_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init aspeed_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2100") + .phys_io = AST_IO_START, +// .phys_ram = ASPEED_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = aspeed_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2300.c b/arch/arm/mach-aspeed/ast2300.c new file mode 100644 index 0000000..a223d74 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2300.c @@ -0,0 +1,206 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/sysdev.h> +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/time.h> +#include <mach/hardware.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDMC_BASE), + .pfn = __phys_to_pfn(AST_SDMC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC0_BASE), + .pfn = __phys_to_pfn(AST_MAC0_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART4_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { +#if defined(CONFIG_ARCH_AST1070) + .virtual = IO_ADDRESS2(AST_C0_VIC_BASE), + .pfn = __phys_to_pfn(AST_C0_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_SCU_BASE), + .pfn = __phys_to_pfn(AST_C0_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_I2C_BASE), + .pfn = __phys_to_pfn(AST_C0_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART0_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART1_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART2_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART3_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + + .length = SZ_1K, + .type = MT_DEVICE, + }, { +#endif + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2300") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast2400.c b/arch/arm/mach-aspeed/ast2400.c new file mode 100644 index 0000000..3567d3c --- /dev/null +++ b/arch/arm/mach-aspeed/ast2400.c @@ -0,0 +1,255 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/sysdev.h> +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/time.h> +#include <mach/hardware.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDMC_BASE), + .pfn = __phys_to_pfn(AST_SDMC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIDEO_BASE), + .pfn = __phys_to_pfn(AST_VIDEO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC0_BASE), + .pfn = __phys_to_pfn(AST_MAC0_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_JTAG_BASE), + .pfn = __phys_to_pfn(AST_JTAG_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_16K*2, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART4_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UDC11_BASE ), + .pfn = __phys_to_pfn(AST_UDC11_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { +#if defined(CONFIG_ARCH_AST1070) + .virtual = IO_ADDRESS2(AST_C0_VIC_BASE), + .pfn = __phys_to_pfn(AST_C0_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_SCU_BASE), + .pfn = __phys_to_pfn(AST_C0_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_I2C_BASE), + .pfn = __phys_to_pfn(AST_C0_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_VIC_BASE), + .pfn = __phys_to_pfn(AST_C1_VIC_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_SCU_BASE), + .pfn = __phys_to_pfn(AST_C1_SCU_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_I2C_BASE), + .pfn = __phys_to_pfn(AST_C1_I2C_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART0_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART1_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART2_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C0_UART3_BASE), + .pfn = __phys_to_pfn(AST_C0_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART0_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART1_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART2_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS2(AST_C1_UART3_BASE), + .pfn = __phys_to_pfn(AST_C1_UART0_BASE), + .length = SZ_1K, + .type = MT_DEVICE, + }, { +#endif + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2400") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/ast3100.c b/arch/arm/mach-aspeed/ast3100.c new file mode 100644 index 0000000..cf220e7 --- /dev/null +++ b/arch/arm/mach-aspeed/ast3100.c @@ -0,0 +1,230 @@ +/* + * linux/arch/arm/mach-ast2300/ast2300.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +//#include <linux/config.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <mach/time.h> + +#include <asm/mach/map.h> +#include <plat/devs.h> + +#include "core.h" + +static struct map_desc ast_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(AST_AHB_CTRL_BASE), + .pfn = __phys_to_pfn(AST_AHB_CTRL_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_NEW_SMC_CONTROLLER_BASE), + .pfn = __phys_to_pfn(AST_NEW_SMC_CONTROLLER_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_SPI_CONTROLLER_BASE), + .pfn = __phys_to_pfn(AST_LPC_SPI_CONTROLLER_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MIC_BASE), + .pfn = __phys_to_pfn(AST_MIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC1_BASE), + .pfn = __phys_to_pfn(AST_MAC1_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MAC2_BASE), + .pfn = __phys_to_pfn(AST_MAC2_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIC_BASE), + .pfn = __phys_to_pfn(AST_VIC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SCU_BASE), + .pfn = __phys_to_pfn(AST_SCU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_CRYPTO_BASE), + .pfn = __phys_to_pfn(AST_CRYPTO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_JTAG_BASE), + .pfn = __phys_to_pfn(AST_JTAG_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_I2S_BASE), + .pfn = __phys_to_pfn(AST_I2S_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GRAPHIC_BASE), + .pfn = __phys_to_pfn(AST_GRAPHIC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_XDMA_BASE), + .pfn = __phys_to_pfn(AST_XDMA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_MCTP_BASE), + .pfn = __phys_to_pfn(AST_MCTP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_ADC_BASE), + .pfn = __phys_to_pfn(AST_ADC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VIDEO_BASE), + .pfn = __phys_to_pfn(AST_VIDEO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SRAM_BASE), + .pfn = __phys_to_pfn(AST_SRAM_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_SDHC_BASE), + .pfn = __phys_to_pfn(AST_SDHC_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_2D_BASE), + .pfn = __phys_to_pfn(AST_2D_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_GPIO_BASE), + .pfn = __phys_to_pfn(AST_GPIO_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_RTC_BASE), + .pfn = __phys_to_pfn(AST_RTC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_TIMER_BASE), + .pfn = __phys_to_pfn(AST_TIMER_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART0_BASE), + .pfn = __phys_to_pfn(AST_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART1_BASE), + .pfn = __phys_to_pfn(AST_UART1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_WDT_BASE), + .pfn = __phys_to_pfn(AST_WDT_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PWM_BASE), + .pfn = __phys_to_pfn(AST_PWM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_VUART0_BASE), + .pfn = __phys_to_pfn(AST_VUART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PUART_BASE), + .pfn = __phys_to_pfn(AST_PUART_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_LPC_BASE), + .pfn = __phys_to_pfn(AST_LPC_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_I2C_BASE), + .pfn = __phys_to_pfn(AST_I2C_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_PECI_BASE), + .pfn = __phys_to_pfn(AST_PECI_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART2_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART3_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(AST_UART4_BASE), + .pfn = __phys_to_pfn(AST_UART2_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +void __init ast_map_io(void) +{ + iotable_init(ast_io_desc, ARRAY_SIZE(ast_io_desc)); +} + +static void __init ast_init(void) +{ + ast_add_all_devices(); +} + +MACHINE_START(ASPEED, "AST2300") + .phys_io = AST_IO_START, +// .phys_ram = AST_SDRAM_BASE, + .io_pg_offst = (IO_ADDRESS(AST_IO_START)>>18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = ast_map_io, + .timer = &ast_timer, + .init_irq = ast_init_irq, + .init_machine = ast_init, +MACHINE_END diff --git a/arch/arm/mach-aspeed/core.h b/arch/arm/mach-aspeed/core.h new file mode 100644 index 0000000..eb5ac89 --- /dev/null +++ b/arch/arm/mach-aspeed/core.h @@ -0,0 +1,25 @@ +/* + * linux/arch/arm/mach-aspeed/core.h + * +* Copyright (C) ASPEED Tech. Corp. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +* + */ + +#ifndef __ASM_ARCH_ASPEED_CORE_H +#define __ASM_ARCH_ASPEED_CORE_H + +extern struct sys_timer ast_timer; + +extern void __init ast_init_irq(void); +#endif diff --git a/arch/arm/mach-aspeed/gpio.c b/arch/arm/mach-aspeed/gpio.c new file mode 100644 index 0000000..e1dbf2c --- /dev/null +++ b/arch/arm/mach-aspeed/gpio.c @@ -0,0 +1,637 @@ +/* + * linux/arch/arm/plat-aspeed/gpio.c + * + * Support functions for ASPEED GPIO + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Written by Ryan Chen <ryan_chen@aspeedtech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/sysdev.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <asm/irq.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <asm/mach/irq.h> + +#include <plat/regs-gpio.h> +#include <asm-generic/gpio.h> + +//#define AST_GPIO_DEBUG + +#ifdef AST_GPIO_DEBUG +//#define GPIODBUG(fmt, args...) printk("%s() " fmt, __FUNCTION__, ## args) +#define GPIODBUG(fmt, args...) printk(fmt, ## args) + +#else +#define GPIODBUG(fmt, args...) +#endif + +/*************************************************************/ +//GPIO group structure +struct ast_gpio_bank { + int irq; + u32 base; +//TODO remove base + u32 index; + u32 data_offset; + u32 dir_offset; + u32 int_en_offset; + u32 int_type_offset; + u32 int_sts_offset; + u32 rst_tol_offset; + u32 debounce_offset; + u32 cmd_source_offset; + struct gpio_chip chip; + +//#ifdef CONFIG_PM +//#define NR_REGS (7) +// u32 regs[NR_REGS]; +//#endif +}; + +int ast_gpio_to_irq(unsigned gpio) +{ + return (gpio + IRQ_GPIO_CHAIN_START); +} + +EXPORT_SYMBOL(ast_gpio_to_irq); + +int ast_irq_to_gpio(unsigned irq) +{ + return (irq - IRQ_GPIO_CHAIN_START); +} + +EXPORT_SYMBOL(ast_irq_to_gpio); + +static inline u32 +ast_gpio_read(struct ast_gpio_bank *ast_gpio ,u32 offset) +{ + GPIODBUG("base = 0x%08x, offset = 0x%08x \n", ast_gpio->base, offset); + + return readl(ast_gpio->base + offset); +} + +static inline void +ast_gpio_write(struct ast_gpio_bank *ast_gpio , u32 val, u32 offset) +{ + GPIODBUG("base = 0x%08x, offset = 0x%08x, val = 0x%08x\n", ast_gpio->base, offset, val); + writel(val, ast_gpio->base + offset); +} + +/***************************************************************************************/ +static int +ast_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + int ret = -1; + + GPIODBUG("dir_in %s[%d] \n",chip->label, offset); + + local_irq_save(flags); + + v = ast_gpio_read(ast_gpio, ast_gpio->dir_offset); + + v &= ~(GPIO_OUTPUT_MODE << (offset + (ast_gpio->index * 8))); + ast_gpio_write(ast_gpio, v, ast_gpio->dir_offset); + + ret = 0; + + local_irq_restore(flags); + return ret; + +} + +static int +ast_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + int ret = -1; + GPIODBUG("dir_out %s[%d], val %d \n",chip->label, offset, val); + + local_irq_save(flags); + + /* Drive as an output */ + v = ast_gpio_read(ast_gpio, ast_gpio->dir_offset); + + v |= (GPIO_OUTPUT_MODE << (offset + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, v, ast_gpio->dir_offset); + + local_irq_restore(flags); + + ret = 0; + return ret; +} + +static int +ast_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + + GPIODBUG("Get %s[%d] \n",chip->label, offset); + + local_irq_save(flags); + + v = ast_gpio_read(ast_gpio, ast_gpio->data_offset); + + v &= (1 << (offset + (ast_gpio->index * 8))); + + if(v) + v = 1; + else + v = 0; + + local_irq_restore(flags); + + return v; +} + +static void +ast_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct ast_gpio_bank *ast_gpio = container_of(chip, struct ast_gpio_bank, chip); + unsigned long flags; + u32 v; + GPIODBUG("Set %s[%d] = %d\n",chip->label, offset, val); + + local_irq_save(flags); + + /* Set the value */ + + v = ast_gpio_read(ast_gpio, ast_gpio->data_offset); + + if (val) + v |= (1 << (offset + (ast_gpio->index * 8))); + else + v &= ~(1 << (offset + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, v, ast_gpio->data_offset); + + local_irq_restore(flags); +} + + +#define AST_GPIO_BANK(name, gpio_base, index_no, data, dir, int_en, int_type, int_sts, rst_tol, debounce, cmd_s) \ + { \ + .base = gpio_base, \ + .index = index_no, \ + .data_offset = data, \ + .dir_offset = dir, \ + .int_en_offset = int_en, \ + .int_type_offset = int_type, \ + .int_sts_offset = int_sts, \ + .rst_tol_offset = rst_tol, \ + .debounce_offset = debounce, \ + .cmd_source_offset = cmd_s, \ + .chip = { \ + .label = name, \ + .direction_input = ast_gpio_direction_input, \ + .direction_output = ast_gpio_direction_output, \ + .get = ast_gpio_get, \ + .set = ast_gpio_set, \ + .ngpio = GPIO_PER_PORT_PIN_NUM, \ + }, \ + } + +static struct ast_gpio_bank ast_gpio_gp[] = { + AST_GPIO_BANK("GPIOA", IO_ADDRESS(AST_GPIO_BASE), 0, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOB", IO_ADDRESS(AST_GPIO_BASE), 1, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOC", IO_ADDRESS(AST_GPIO_BASE), 2, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOD", IO_ADDRESS(AST_GPIO_BASE), 3, 0x000, 0x004, 0x008, 0x00c, 0x018, 0x01c, 0x040, 0x060), + AST_GPIO_BANK("GPIOE", IO_ADDRESS(AST_GPIO_BASE), 0, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOF", IO_ADDRESS(AST_GPIO_BASE), 1, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOG", IO_ADDRESS(AST_GPIO_BASE), 2, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), + AST_GPIO_BANK("GPIOH", IO_ADDRESS(AST_GPIO_BASE), 3, 0x020, 0x024, 0x028, 0x02c, 0x038, 0x03c, 0x048, 0x068), +#if defined(CONFIG_ARCH_AST2300) || defined(CONFIG_ARCH_AST2400) + AST_GPIO_BANK("GPIOI", IO_ADDRESS(AST_GPIO_BASE), 0, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOJ", IO_ADDRESS(AST_GPIO_BASE), 1, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOK", IO_ADDRESS(AST_GPIO_BASE), 2, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOL", IO_ADDRESS(AST_GPIO_BASE), 3, 0x070, 0x074, 0x098, 0x09c, 0x0a8, 0x0ac, 0x0b0, 0x090), + AST_GPIO_BANK("GPIOM", IO_ADDRESS(AST_GPIO_BASE), 0, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPION", IO_ADDRESS(AST_GPIO_BASE), 1, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOO", IO_ADDRESS(AST_GPIO_BASE), 2, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOP", IO_ADDRESS(AST_GPIO_BASE), 3, 0x078, 0x07c, 0x0e8, 0x0ec, 0x0f8, 0x0fc, 0x100, 0x0e0), + AST_GPIO_BANK("GPIOQ", IO_ADDRESS(AST_GPIO_BASE), 0, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOR", IO_ADDRESS(AST_GPIO_BASE), 1, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOS", IO_ADDRESS(AST_GPIO_BASE), 2, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), +#if defined(CONFIG_ARCH_AST2400) + AST_GPIO_BANK("GPIOT", IO_ADDRESS(AST_GPIO_BASE), 3, 0x080, 0x084, 0x118, 0x11c, 0x128, 0x12c, 0x130, 0x110), + AST_GPIO_BANK("GPIOU", IO_ADDRESS(AST_GPIO_BASE), 0, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOV", IO_ADDRESS(AST_GPIO_BASE), 1, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOW", IO_ADDRESS(AST_GPIO_BASE), 2, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOX", IO_ADDRESS(AST_GPIO_BASE), 3, 0x088, 0x08c, 0x148, 0x14c, 0x158, 0x15c, 0x160, 0x140), + AST_GPIO_BANK("GPIOY", IO_ADDRESS(AST_GPIO_BASE), 0, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOZ", IO_ADDRESS(AST_GPIO_BASE), 1, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOAA", IO_ADDRESS(AST_GPIO_BASE), 2, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), + AST_GPIO_BANK("GPIOAB", IO_ADDRESS(AST_GPIO_BASE), 3, 0x1e0, 0x1e4, 0x178, 0x17c, 0x188, 0x18c, 0x190, 0x170), +#endif +#endif +}; + + +/***************************************************************************************/ +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +int ast_set_gpio_value(unsigned gpio_pin, int value) +{ + u32 data; + u32 gp, pin; + gp = gpio_pin / 8; + pin = gpio_pin % 32; + data = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].data_offset); + if(value) + data |= (1 << pin); + else + data &= ~(1 << pin); + + GPIODBUG("gp : %d, pin %d, data = %x \n ", gp, pin, data); + ast_gpio_write(&ast_gpio_gp[gp], data, ast_gpio_gp[gp].data_offset); + + return 0; +} +EXPORT_SYMBOL(ast_set_gpio_value); + + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +int ast_get_gpio_value(unsigned gpio_pin) +{ + u32 data; + u32 gp, pin; + gp = gpio_pin / 8; + pin = gpio_pin % 32; + data = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].data_offset); + + GPIODBUG("gp : %d, pin %d, data = %x, value = %d \n ", gp, pin, data, (data >> pin) & 1); + + return ((data >> pin) & 1); +} +EXPORT_SYMBOL(ast_get_gpio_value); + +//timer 0/1/2 +//Debounce time = PCLK * (val+1) +void ast_set_gpio_debounce_timer(int timer, int val) +{ + switch(timer) { + case 0: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x50); + break; + case 1: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x54); + break; + case 2: + writel(val, IO_ADDRESS(AST_GPIO_BASE) + 0x58); + break; + } +} + +EXPORT_SYMBOL(ast_set_gpio_debounce_timer); + +//TODO ...... +//mode 0 : no debounce , 1: set 0x50, 2: 0x54, 3: 0x58 +void ast_set_gpio_debounce(int gpio_port, int mode) +{ +#if 0 + u32 set0, set1; + u16 gp, port; + gp = gpio_port / 4; + port = gpio_port % 4; + set0 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset); + set1 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset + 0x04); + + switch(port) { + case 0: //A , H , ...... + set0 = port + ast_gpio_write(ast_gpio, val, 0x50); + break; + case 1: + ast_gpio_write(ast_gpio, val, 0x54); + break; + case 2: + ast_gpio_write(ast_gpio, val, 0x58); + break; + case 3: + ast_gpio_write(ast_gpio, val, 0x58); + break; + default: + GPIODBUG("not support \n"); + return; + break; + + } + + ast_gpio_write(&ast_gpio_gp[gp], set0, ast_gpio_gp[gp].debounce_offset); + ast_gpio_write(&ast_gpio_gp[gp], set1, ast_gpio_gp[gp].debounce_offset + 0x04); +#endif +} + +EXPORT_SYMBOL(ast_set_gpio_debounce); + +//TODO ...... +// +void ast_set_gpio_tolerant(int gpio_port, int mode) +{ +#if 0 + u32 set0, set1; + u16 gp, port; + gp = gpio_port / 4; + port = gpio_port % 4; + set0 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset); + set1 = ast_gpio_read(&ast_gpio_gp[gp], ast_gpio_gp[gp].debounce_offset + 0x04); + + switch(port) { + case 0: //A , H , ...... + set0 = port + ast_gpio_write(ast_gpio, val, 0x50); + break; + case 1: + ast_gpio_write(ast_gpio, val, 0x54); + break; + case 2: + ast_gpio_write(ast_gpio, val, 0x58); + break; + case 3: + ast_gpio_write(ast_gpio, val, 0x58); + break; + default: + GPIODBUG("not support \n"); + return; + break; + + } + + ast_gpio_write(&ast_gpio_gp[gp], set0, ast_gpio_gp[gp].debounce_offset); + ast_gpio_write(&ast_gpio_gp[gp], set1, ast_gpio_gp[gp].debounce_offset + 0x04); +#endif +} + +EXPORT_SYMBOL(ast_set_gpio_tolerant); + +/* + * We need to unmask the GPIO bank interrupt as soon as possible to + * avoid missing GPIO interrupts for other lines in the bank. + * Then we need to mask-read-clear-unmask the triggered GPIO lines + * in the bank to avoid missing nested interrupts for a GPIO line. + * If we wait to unmask individual GPIO lines in the bank after the + * line's interrupt handler has been run, we may miss some nested + * interrupts. + */ +static void +ast_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 isr; + int i,j; + struct ast_gpio_bank *ast_gpio; + + if(irq != IRQ_GPIO) + BUG(); + + GPIODBUG("ast_gpio_irq_handler %d \n ", irq); + +// ast_gpio = get_irq_data(irq); + +// GPIODBUG("[%s] ------\n ",ast_gpio->chip.label ); + + desc->chip->ack(IRQ_GPIO); + + for (i = 0; i < GPIO_PORT_NUM; i++) { + ast_gpio = &ast_gpio_gp[i]; + isr = ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset); + GPIODBUG("isr %x \n", isr); + isr = (isr >> (8 * ast_gpio->index)) & 0xff; + GPIODBUG("[%s] isr %x \n", ast_gpio->chip.label, isr); + if(isr != 0) { + //get gpio isr and --> to IRQ number .... + for (j=0; j<8;j++) { + if((1<<j) & isr) { + // dispach interrupt +// GPIODBUG("[%s] pin %d -> irq [%d]\n",ast_gpio->chip.label, j, j + IRQ_GPIO_CHAIN_START + (8 * i)); + generic_handle_irq(j + IRQ_GPIO_CHAIN_START + (8 * i)); + } + } +// GPIODBUG("isr -- ? %x \n",ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset)); + } + } + +#if 0 + while(1) { + isr = ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset); + printk("isr %x \n", isr); + isr = isr >> (8 * ast_gpio->index); + //get gpio isr and --> to IRQ number .... + for (i=0; i<8;i++) { + if((1<<i) & isr) { + // dispach interrupt + printk("[%s] pin %d -> irq [%d]\n",ast_gpio->chip.label, i,i + IRQ_GPIO_CHAIN_START + (8 * ast_gpio->index)); + generic_handle_irq(i + IRQ_GPIO_CHAIN_START + (8 * ast_gpio->index)); + } + } + if(isr == 0) + break; + } +#endif + desc->chip->unmask(IRQ_GPIO); + /* now it may re-trigger */ + +} + +static void ast_gpio_ack_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + + gpio_irq = gpio_irq % 8; + + GPIODBUG("irq [%d] : ast_gpio_ack_irq [%s] pin %d\n ",irq, ast_gpio->chip.label, gpio_irq); + + GPIODBUG("write clr [%x] %x\n ",ast_gpio->int_sts_offset, 1<< (gpio_irq + (ast_gpio->index * 8))); + + ast_gpio_write(ast_gpio, 1<< (gpio_irq + (ast_gpio->index * 8)), ast_gpio->int_sts_offset); + + GPIODBUG("read sts %x\n ",ast_gpio_read(ast_gpio, ast_gpio->int_sts_offset)); + +} + +static void ast_gpio_mask_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%8; + + + GPIODBUG("irq [%d] : ast_gpio_mask_irq [%s] pin %d\n ",irq, ast_gpio->chip.label, gpio_irq); + + //disable irq + ast_gpio_write(ast_gpio, ast_gpio_read(ast_gpio, ast_gpio->int_en_offset) & + ~(1<< (gpio_irq + (ast_gpio->index * 8))), ast_gpio->int_en_offset); +} + +static void ast_gpio_unmask_irq(unsigned int irq) +{ + struct ast_gpio_bank *ast_gpio = get_irq_chip_data(irq); + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%8; + + + GPIODBUG("irq[%d], [%s] pin %d\n",irq, ast_gpio->chip.label, gpio_irq); + + //Enable IRQ .. + ast_gpio_write(ast_gpio, 1<< (gpio_irq + (ast_gpio->index * 8)), ast_gpio->int_sts_offset); + + ast_gpio_write(ast_gpio, ast_gpio_read(ast_gpio, ast_gpio->int_en_offset) | + (1<< (gpio_irq + (ast_gpio->index * 8))), ast_gpio->int_en_offset); + +} + +static int +ast_gpio_irq_type(unsigned int irq, unsigned int type) +{ + u32 type0, type1, type2; + struct ast_gpio_bank *ast_gpio; + int retval = 0; + unsigned int gpio_irq = irq - IRQ_GPIO_CHAIN_START; + gpio_irq = gpio_irq%32; + + + + GPIODBUG("ast_gpio_irq_type %d : %x \n",irq,type); + if (type & ~IRQ_TYPE_SENSE_MASK) + return -EINVAL; + + ast_gpio = get_irq_chip_data(irq); + + type0 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset); + type1 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset + 0x04); + type2 = ast_gpio_read(ast_gpio, ast_gpio->int_type_offset + 0x08); + + switch(type) { + /* Edge rising type */ + case IRQ_TYPE_EDGE_RISING: + type0 |=(1<<irq); + type1 &=~(1<<irq); + type2 &=~(1<<irq); + break; + /* Edge falling type */ + case IRQ_TYPE_EDGE_FALLING: + type2 |=(1<<irq); + break; + case IRQ_TYPE_EDGE_BOTH: + type0 &=~(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + case IRQ_TYPE_LEVEL_HIGH: + type0 |=(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + case IRQ_TYPE_LEVEL_LOW: + type0 &=~(1<<irq); + type1 |=(1<<irq); + type2 &=~(1<<irq); + break; + default: + GPIODBUG("not support trigger"); + return -EINVAL; + break; + } + + ast_gpio_write(ast_gpio, type0, ast_gpio->int_type_offset); + ast_gpio_write(ast_gpio, type1, ast_gpio->int_type_offset + 0x04); + ast_gpio_write(ast_gpio, type2, ast_gpio->int_type_offset + 0x08); + + return retval; + +} + +static struct irq_chip ast_gpio_irq_chip = { + .name = "GPIO", + .ack = ast_gpio_ack_irq, + .mask = ast_gpio_mask_irq, + .unmask = ast_gpio_unmask_irq, + .set_type = ast_gpio_irq_type, +}; + +/*---------------------------------------------------------------------*/ +static int __init ast_gpio_init(void) +{ + int i,j; + struct ast_gpio_bank *ast_gpio; + + GPIODBUG("gpio port num %d, total gpio pin : %d\n", + GPIO_PORT_NUM, ARCH_NR_GPIOS); + + GPIODBUG("gpio chain start %d \n",IRQ_GPIO_CHAIN_START); + for (i = 0; i < GPIO_PORT_NUM; i++) { + ast_gpio = &ast_gpio_gp[i]; + + GPIODBUG("add gpio_chip [%s] : %d\n",ast_gpio->chip.label, i); + +#if 0 + bank->chip.direction_input = ast_gpio_direction_input; + bank->chip.get = ast_gpio_get; + bank->chip.direction_output = ast_gpio_direction_output; + bank->chip.set = ast_gpio_set; + + bank->chip.label = "gpio"; +#endif + ast_gpio->chip.base = i*8; + ast_gpio->chip.ngpio = 8; + + gpiochip_add(&ast_gpio->chip); + +#if 1 + //Set Level Trigger + ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_type_offset); + ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_type_offset + 0x04); + ast_gpio_write(ast_gpio, 0, ast_gpio->int_type_offset + 0x08); + //remove clear direction for keep orignal state +// ast_gpio_write(ast_gpio, 0, ast_gpio->dir_offset); + //Enable IRQ +// ast_gpio_write(ast_gpio, 0xffffffff, ast_gpio->int_en_offset); + +#endif + + for(j=0;j<8;j++) { + GPIODBUG("inst chip data %d\n",i*8 + j + IRQ_GPIO_CHAIN_START); + set_irq_chip_data(i*8 + j + IRQ_GPIO_CHAIN_START, ast_gpio); + set_irq_chip(i*8 + j + IRQ_GPIO_CHAIN_START, &ast_gpio_irq_chip); + set_irq_handler(i*8 + j + IRQ_GPIO_CHAIN_START, handle_level_irq); + set_irq_flags(i*8 + j + IRQ_GPIO_CHAIN_START, IRQF_VALID); + } + set_irq_chained_handler(IRQ_GPIO, ast_gpio_irq_handler); +// set_irq_chip_data(IRQ_GPIO, ast_gpio); +// set_irq_data(IRQ_GPIO, ast_gpio_gp[]); + + + } + + return 0; + +} + +core_initcall(ast_gpio_init); + +//arch_initcall(ast_gpio_init); + diff --git a/arch/arm/mach-aspeed/include/mach/aspeed_serial.h b/arch/arm/mach-aspeed/include/mach/aspeed_serial.h new file mode 100644 index 0000000..33bf333 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/aspeed_serial.h @@ -0,0 +1,61 @@ +/* + * file : aspeed_serial.h + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef ASM_ARM_HARDWARE_AST_SERIAL_H +#define ASM_ARM_HARDWARE_AST_SERIAL_H + +#define UART_RBR 0x00 /* Receiver Buffer Register */ +#define UART_THR 0x00 /* Transmit Holding Register */ +#define UART_DLL 0x00 /* Divisor Latch Low Register */ +#define UART_DLH 0x04 /* Divisor Latch High Register */ +#define UART_IER 0x04 /* Interrupt Enable Register */ +#define UART_IIR 0x08 /* Interrupt Identity Register */ +#define UART_FCR 0x08 /* FIFO Control Register */ +#define UART_LCR 0x0C /* Line Control Register */ +#define UART_MCR 0x10 /* Modem Control Register */ +#define UART_LSR 0x14 /* Line Status Register */ +#define UART_MSR 0x18 /* Modem Status Register */ +#define UART_SCR 0x1C /* Scratch Register */ + +/* Interrupt Enable Register */ +#define UART_IER_EMSI 0x08 /* Enable Modem Status Interrupt */ +#define UART_IER_ELSI 0x04 /* Enable Line Status Interrupt */ +#define UART_IER_ETEI 0x02 /* Enable Transmit Holding Empty Interrupt */ +#define UART_IER_ERDI 0X01 /* Enable Received Data Interrupt */ + +/* FIFO Control Register */ +#define UART_FCR_XMITR 0x04 /* XMIT FIFO Reset */ +#define UART_FCR_RCVRR 0x02 /* RCVR FIFO Reset */ +#define UART_FCR_FIFOE 0x01 /* FIEO Enable */ + +/* Line Control Register */ +#define UART_LCR_DLAB 0x80 /* Divisor Latch Address Bit */ +#define UART_LCR_BRK 0x40 /* Break Control */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_PEN 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop Bit */ +#define UART_LCR_WLEN_MASK 0x03 /* bits per character mask */ +#define UART_LCR_WLEN_8 0x03 /* 8 bits per character */ +#define UART_LCR_WLEN_7 0x02 /* 7 bits per character */ +#define UART_LCR_WLEN_6 0x01 /* 6 bits per character */ +#define UART_LCR_WLEN_5 0x00 /* 5 bits per character */ + +/* Line Status Register */ +#define UART_LSR_TEMT 0x40 /* Transmitter Empty */ +#define UART_LSR_THRE 0x20 /* Transmitter Holding Register Empty */ +#define UART_LSR_BE 0x10 /* Break Error */ +#define UART_LSR_FE 0x08 /* Framing Error */ +#define UART_LSR_PE 0x04 /* Parity Error */ +#define UART_LSR_OE 0x02 /* Overrun Error */ +#define UART_LSR_DR 0x01 /* Data Ready */ +#define UART_LSR_ANY (UART_LSR_BE|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h b/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h new file mode 100644 index 0000000..2ac2b41 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast-uart-dma.h @@ -0,0 +1,86 @@ +/******************************************************************************** +* File Name : ast-uart-dma.h +* +* Copyright (C) 2012-2020 ASPEED Technology Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +********************************************************************************/ +#ifndef AST_UART_DMA_H_INCLUDED +#define AST_UART_DMA_H_INCLUDED + + +#define DMA_BUFF_SIZE 0x1000 //4096 + +struct ast_uart_dma_data { + u8 chip_no; //campain chip number + u8 dma_ch; //dma channel number +}; + + +/* enum ast_uart_chan_op + * + * operation codes passed to the DMA code by the user, and also used + * to inform the current channel owner of any changes to the system state +*/ + +enum ast_uart_chan_op { + AST_UART_DMAOP_TRIGGER, + AST_UART_DMAOP_STOP, +}; + +struct ast1070_dma_ch; + +/* ast_uart_dma_cbfn_t * * buffer callback routine type */ +typedef void (*ast_uart_dma_cbfn_t)(struct ast1070_dma_ch *,void *dev_id, u16 len); + +struct uart_dma_desc { + u32 desc0; + u32 desc1; + u32 desc2; + u32 desc3; +} __attribute__ ((aligned(16))); + +struct ast1070_dma_ch { + u8 ch_no; + u8 direction; + u8 enable; + u32 ctrl_offset; + u32 desc_offset; + void *priv; + struct uart_dma_desc *desc; + dma_addr_t desc_dma_addr; /* Mapped descr. table */ + /* cdriver callbacks */ + ast_uart_dma_cbfn_t callback_fn; /* buffer done callback */ +}; + +#define AST1070_UART_DMA_CH 4 + +struct ast1070_dma { + void __iomem *reg_base; + struct ast1070_dma_ch dma_tx_ch[AST1070_UART_DMA_CH]; + struct ast1070_dma_ch dma_rx_ch[AST1070_UART_DMA_CH]; +}; + + +/* ast_uart_dma_request * * request a dma channel exclusivley */ +extern int ast_uart_rx_dma_request(u8 node, u8 channel, ast_uart_dma_cbfn_t rtn, void *id); +extern int ast_uart_tx_dma_request(u8 node, u8 channel, ast_uart_dma_cbfn_t rtn, void *id); + +/* ast_uart_dma_ctrl * * change the state of the dma channel */ +extern int ast_uart_rx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op); +extern int ast_uart_tx_dma_ctrl(u8 node, u8 ch, enum ast_uart_chan_op op); + +extern int ast_uart_rx_dma_enqueue(u8 node, u8 ch, dma_addr_t rx_buff, u16 len); +extern int ast_uart_tx_dma_enqueue(u8 node, u8 ch, dma_addr_t tx_buff, u16 len); + + + +#endif + diff --git a/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h b/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h new file mode 100644 index 0000000..0774417 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1070_irqs.h @@ -0,0 +1,142 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1070_IRQS_H_ +#define _AST1070_IRQS_H_ 1 + +#define IRQ_C0_VIC_CHAIN IRQ_EXT0 +#define IRQ_C0_VIC_CHAIN_START (AST_VIC_NUM) + +#define IRQ_C1_VIC_CHAIN IRQ_EXT1 +#define IRQ_C1_VIC_CHAIN_START (IRQ_C0_VIC_CHAIN_START + AST_CVIC_NUM) + +#define IRQ_C2_VIC_CHAIN IRQ_EXT2 +#define IRQ_C2_VIC_CHAIN_START (IRQ_C1_VIC_CHAIN_START + AST_CVIC_NUM) + +#define IRQ_C3_VIC_CHAIN IRQ_EXT3 +#define IRQ_C3_VIC_CHAIN_START (IRQ_C2_VIC_CHAIN_START + AST_CVIC_NUM) + +#define AST_CVIC_NUM 25 + +#define IRQ_C0_N1_KCS (IRQ_C0_VIC_CHAIN_START + 0) +#define IRQ_C0_N1_UART (IRQ_C0_VIC_CHAIN_START + 1) +#define IRQ_C0_N1_MAILBOX (IRQ_C0_VIC_CHAIN_START + 2) +#define IRQ_C0_N1_PORT80 (IRQ_C0_VIC_CHAIN_START + 3) +#define IRQ_C0_N1_RESET (IRQ_C0_VIC_CHAIN_START + 4) +#define IRQ_C0_N2_KCS (IRQ_C0_VIC_CHAIN_START + 5) +#define IRQ_C0_N2_UART (IRQ_C0_VIC_CHAIN_START + 6) +#define IRQ_C0_N2_MAILBOX (IRQ_C0_VIC_CHAIN_START + 7) +#define IRQ_C0_N2_PORT80 (IRQ_C0_VIC_CHAIN_START + 8) +#define IRQ_C0_N2_RESET (IRQ_C0_VIC_CHAIN_START + 9) +#define IRQ_C0_N3_KCS (IRQ_C0_VIC_CHAIN_START + 10) +#define IRQ_C0_N3_UART (IRQ_C0_VIC_CHAIN_START + 11) +#define IRQ_C0_N3_MAILBOX (IRQ_C0_VIC_CHAIN_START + 12) +#define IRQ_C0_N3_PORT80 (IRQ_C0_VIC_CHAIN_START + 13) +#define IRQ_C0_N3_RESET (IRQ_C0_VIC_CHAIN_START + 14) +#define IRQ_C0_N4_KCS (IRQ_C0_VIC_CHAIN_START + 15) +#define IRQ_C0_N4_UART (IRQ_C0_VIC_CHAIN_START + 16) +#define IRQ_C0_N4_MAILBOX (IRQ_C0_VIC_CHAIN_START + 17) +#define IRQ_C0_N4_PORT80 (IRQ_C0_VIC_CHAIN_START + 18) +#define IRQ_C0_N4_RESET (IRQ_C0_VIC_CHAIN_START + 19) +#define IRQ_C0_N1_UART_DMA (IRQ_C0_VIC_CHAIN_START + 20) +#define IRQ_C0_N2_UART_DMA (IRQ_C0_VIC_CHAIN_START + 21) +#define IRQ_C0_N3_UART_DMA (IRQ_C0_VIC_CHAIN_START + 22) +#define IRQ_C0_N4_UART_DMA (IRQ_C0_VIC_CHAIN_START + 23) +#define IRQ_C0_I2C (IRQ_C0_VIC_CHAIN_START + 24) + +#define IRQ_C1_N1_KCS (IRQ_C1_VIC_CHAIN_START + 0) +#define IRQ_C1_N1_UART (IRQ_C1_VIC_CHAIN_START + 1) +#define IRQ_C1_N1_MAILBOX (IRQ_C1_VIC_CHAIN_START + 2) +#define IRQ_C1_N1_PORT80 (IRQ_C1_VIC_CHAIN_START + 3) +#define IRQ_C1_N1_RESET (IRQ_C1_VIC_CHAIN_START + 4) +#define IRQ_C1_N2_KCS (IRQ_C1_VIC_CHAIN_START + 5) +#define IRQ_C1_N2_UART (IRQ_C1_VIC_CHAIN_START + 6) +#define IRQ_C1_N2_MAILBOX (IRQ_C1_VIC_CHAIN_START + 7) +#define IRQ_C1_N2_PORT80 (IRQ_C1_VIC_CHAIN_START + 8) +#define IRQ_C1_N2_RESET (IRQ_C1_VIC_CHAIN_START + 9) +#define IRQ_C1_N3_KCS (IRQ_C1_VIC_CHAIN_START + 10) +#define IRQ_C1_N3_UART (IRQ_C1_VIC_CHAIN_START + 11) +#define IRQ_C1_N3_MAILBOX (IRQ_C1_VIC_CHAIN_START + 12) +#define IRQ_C1_N3_PORT80 (IRQ_C1_VIC_CHAIN_START + 13) +#define IRQ_C1_N3_RESET (IRQ_C1_VIC_CHAIN_START + 14) +#define IRQ_C1_N4_KCS (IRQ_C1_VIC_CHAIN_START + 15) +#define IRQ_C1_N4_UART (IRQ_C1_VIC_CHAIN_START + 16) +#define IRQ_C1_N4_MAILBOX (IRQ_C1_VIC_CHAIN_START + 17) +#define IRQ_C1_N4_PORT80 (IRQ_C1_VIC_CHAIN_START + 18) +#define IRQ_C1_N4_RESET (IRQ_C1_VIC_CHAIN_START + 19) +#define IRQ_C1_N1_UART_DMA (IRQ_C1_VIC_CHAIN_START + 20) +#define IRQ_C1_N2_UART_DMA (IRQ_C1_VIC_CHAIN_START + 21) +#define IRQ_C1_N3_UART_DMA (IRQ_C1_VIC_CHAIN_START + 22) +#define IRQ_C1_N4_UART_DMA (IRQ_C1_VIC_CHAIN_START + 23) +#define IRQ_C1_I2C (IRQ_C1_VIC_CHAIN_START + 24) + +#define IRQ_C2_N1_KCS (IRQ_C2_VIC_CHAIN_START + 0) +#define IRQ_C2_N1_UART (IRQ_C2_VIC_CHAIN_START + 1) +#define IRQ_C2_N1_MAILBOX (IRQ_C2_VIC_CHAIN_START + 2) +#define IRQ_C2_N1_PORT80 (IRQ_C2_VIC_CHAIN_START + 3) +#define IRQ_C2_N1_RESET (IRQ_C2_VIC_CHAIN_START + 4) +#define IRQ_C2_N2_KCS (IRQ_C2_VIC_CHAIN_START + 5) +#define IRQ_C2_N2_UART (IRQ_C2_VIC_CHAIN_START + 6) +#define IRQ_C2_N2_MAILBOX (IRQ_C2_VIC_CHAIN_START + 7) +#define IRQ_C2_N2_PORT80 (IRQ_C2_VIC_CHAIN_START + 8) +#define IRQ_C2_N2_RESET (IRQ_C2_VIC_CHAIN_START + 9) +#define IRQ_C2_N3_KCS (IRQ_C2_VIC_CHAIN_START + 10) +#define IRQ_C2_N3_UART (IRQ_C2_VIC_CHAIN_START + 11) +#define IRQ_C2_N3_MAILBOX (IRQ_C2_VIC_CHAIN_START + 12) +#define IRQ_C2_N3_PORT80 (IRQ_C2_VIC_CHAIN_START + 13) +#define IRQ_C2_N3_RESET (IRQ_C2_VIC_CHAIN_START + 14) +#define IRQ_C2_N4_KCS (IRQ_C2_VIC_CHAIN_START + 15) +#define IRQ_C2_N4_UART (IRQ_C2_VIC_CHAIN_START + 16) +#define IRQ_C2_N4_MAILBOX (IRQ_C2_VIC_CHAIN_START + 17) +#define IRQ_C2_N4_PORT80 (IRQ_C2_VIC_CHAIN_START + 18) +#define IRQ_C2_N4_RESET (IRQ_C2_VIC_CHAIN_START + 19) +#define IRQ_C2_N1_UART_DMA (IRQ_C2_VIC_CHAIN_START + 20) +#define IRQ_C2_N2_UART_DMA (IRQ_C2_VIC_CHAIN_START + 21) +#define IRQ_C2_N3_UART_DMA (IRQ_C2_VIC_CHAIN_START + 22) +#define IRQ_C2_N4_UART_DMA (IRQ_C2_VIC_CHAIN_START + 23) +#define IRQ_C2_I2C (IRQ_C2_VIC_CHAIN_START + 24) + +#define IRQ_C3_N1_KCS (IRQ_C3_VIC_CHAIN_START + 0) +#define IRQ_C3_N1_UART (IRQ_C3_VIC_CHAIN_START + 1) +#define IRQ_C3_N1_MAILBOX (IRQ_C3_VIC_CHAIN_START + 2) +#define IRQ_C3_N1_PORT80 (IRQ_C3_VIC_CHAIN_START + 3) +#define IRQ_C3_N1_RESET (IRQ_C3_VIC_CHAIN_START + 4) +#define IRQ_C3_N2_KCS (IRQ_C3_VIC_CHAIN_START + 5) +#define IRQ_C3_N2_UART (IRQ_C3_VIC_CHAIN_START + 6) +#define IRQ_C3_N2_MAILBOX (IRQ_C3_VIC_CHAIN_START + 7) +#define IRQ_C3_N2_PORT80 (IRQ_C3_VIC_CHAIN_START + 8) +#define IRQ_C3_N2_RESET (IRQ_C3_VIC_CHAIN_START + 9) +#define IRQ_C3_N3_KCS (IRQ_C3_VIC_CHAIN_START + 10) +#define IRQ_C3_N3_UART (IRQ_C3_VIC_CHAIN_START + 11) +#define IRQ_C3_N3_MAILBOX (IRQ_C3_VIC_CHAIN_START + 12) +#define IRQ_C3_N3_PORT80 (IRQ_C3_VIC_CHAIN_START + 13) +#define IRQ_C3_N3_RESET (IRQ_C3_VIC_CHAIN_START + 14) +#define IRQ_C3_N4_KCS (IRQ_C3_VIC_CHAIN_START + 15) +#define IRQ_C3_N4_UART (IRQ_C3_VIC_CHAIN_START + 16) +#define IRQ_C3_N4_MAILBOX (IRQ_C3_VIC_CHAIN_START + 17) +#define IRQ_C3_N4_PORT80 (IRQ_C3_VIC_CHAIN_START + 18) +#define IRQ_C3_N4_RESET (IRQ_C3_VIC_CHAIN_START + 19) +#define IRQ_C3_N1_UART_DMA (IRQ_C3_VIC_CHAIN_START + 20) +#define IRQ_C3_N2_UART_DMA (IRQ_C3_VIC_CHAIN_START + 21) +#define IRQ_C3_N3_UART_DMA (IRQ_C3_VIC_CHAIN_START + 22) +#define IRQ_C3_N4_UART_DMA (IRQ_C3_VIC_CHAIN_START + 23) +#define IRQ_C3_I2C (IRQ_C3_VIC_CHAIN_START + 24) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1070_platform.h b/arch/arm/mach-aspeed/include/mach/ast1070_platform.h new file mode 100644 index 0000000..feefd91 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1070_platform.h @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1070_PLATFORM_H_ +#define _AST1070_PLATFORM_H_ 1 + +#define AST_C0_BASE (AST_LPC_BRIDGE) + +#define AST_C0_UART0_BASE (AST_C0_BASE) /* Companion UART1 */ +#define AST_C0_UART1_BASE (AST_C0_BASE + 0x400) /* Companion UART2 */ +#define AST_C0_UART2_BASE (AST_C0_BASE + 0x800) /* Companion UART3 */ +#define AST_C0_UART3_BASE (AST_C0_BASE + 0xc00) /* Companion UART4 */ +#define AST_C0_LPC0_BASE (AST_C0_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C0_LPC1_BASE (AST_C0_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C0_LPC2_BASE (AST_C0_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C0_LPC3_BASE (AST_C0_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C0_SCU_BASE (AST_C0_BASE + 0x2000) /* Companion SCU */ +#define AST_C0_VIC_BASE (AST_C0_BASE + 0x2400) /* Companion VIC */ +#define AST_C0_LPC_SLAVE_BASE (AST_C0_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C0_I2C_BASE (AST_C0_BASE + 0x3000) /* Companion I2C */ +#define AST_C0_SPI_BASE (AST_C0_BASE + 0x4000) /* Companion SPI */ +#define AST_C0_LPC_SPI_BASE (AST_C0_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C0_UART_DMA_BASE (AST_C0_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C0_SPI_CONTROL_BASE (AST_C0_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C0_SPI_SHADOW_SRAM_BASE (AST_C0_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C1_BASE (AST_LPC_BRIDGE + 0x10000) + +#define AST_C1_UART0_BASE (AST_C1_BASE) /* Companion UART1 */ +#define AST_C1_UART1_BASE (AST_C1_BASE + 0x400) /* Companion UART2 */ +#define AST_C1_UART2_BASE (AST_C1_BASE + 0x800) /* Companion UART3 */ +#define AST_C1_UART3_BASE (AST_C1_BASE + 0xc00) /* Companion UART4 */ +#define AST_C1_LPC0_BASE (AST_C1_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C1_LPC1_BASE (AST_C1_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C1_LPC2_BASE (AST_C1_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C1_LPC3_BASE (AST_C1_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C1_SCU_BASE (AST_C1_BASE + 0x2000) /* Companion SCU */ +#define AST_C1_VIC_BASE (AST_C1_BASE + 0x2400) /* Companion VIC */ +#define AST_C1_LPC_SLAVE_BASE (AST_C1_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C1_I2C_BASE (AST_C1_BASE + 0x3000) /* Companion I2C */ +#define AST_C1_SPI_BASE (AST_C1_BASE + 0x4000) /* Companion SPI */ +#define AST_C1_LPC_SPI_BASE (AST_C1_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C1_UART_DMA_BASE (AST_C1_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C1_SPI_CONTROL_BASE (AST_C1_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C1_SPI_SHADOW_SRAM_BASE (AST_C1_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C2_BASE (AST_LPC_BRIDGE + 0x20000) + +#define AST_C2_UART0_BASE (AST_C2_BASE) /* Companion UART1 */ +#define AST_C2_UART1_BASE (AST_C2_BASE + 0x400) /* Companion UART2 */ +#define AST_C2_UART2_BASE (AST_C2_BASE + 0x800) /* Companion UART3 */ +#define AST_C2_UART3_BASE (AST_C2_BASE + 0xc00) /* Companion UART4 */ +#define AST_C2_LPC1_BASE (AST_C2_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C2_LPC2_BASE (AST_C2_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C2_LPC3_BASE (AST_C2_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C2_LPC4_BASE (AST_C2_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C2_SCU_BASE (AST_C2_BASE + 0x2000) /* Companion SCU */ +#define AST_C2_VIC_BASE (AST_C2_BASE + 0x2400) /* Companion VIC */ +#define AST_C2_LPC_SLAVE_BASE (AST_C2_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C2_I2C_BASE (AST_C2_BASE + 0x3000) /* Companion I2C */ +#define AST_C2_SPI_BASE (AST_C2_BASE + 0x4000) /* Companion SPI */ +#define AST_C2_LPC_SPI_BASE (AST_C2_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C2_UART_DMA_BASE (AST_C2_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C2_SPI_CONTROL_BASE (AST_C2_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C2_SPI_SHADOW_SRAM_BASE (AST_C2_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#define AST_C3_BASE (AST_LPC_BRIDGE + 0x30000) + +#define AST_C3_UART0_BASE (AST_C3_BASE) /* Companion UART1 */ +#define AST_C3_UART1_BASE (AST_C3_BASE + 0x400) /* Companion UART2 */ +#define AST_C3_UART2_BASE (AST_C3_BASE + 0x800) /* Companion UART3 */ +#define AST_C3_UART3_BASE (AST_C3_BASE + 0xc00) /* Companion UART4 */ +#define AST_C3_LPC0_BASE (AST_C3_BASE + 0x1000) /* Companion LPC1 */ +#define AST_C3_LPC1_BASE (AST_C3_BASE + 0x1400) /* Companion LPC2 */ +#define AST_C3_LPC2_BASE (AST_C3_BASE + 0x1800) /* Companion LPC3 */ +#define AST_C3_LPC3_BASE (AST_C3_BASE + 0x1c00) /* Companion LPC4 */ +#define AST_C3_SCU_BASE (AST_C3_BASE + 0x2000) /* Companion SCU */ +#define AST_C3_VIC_BASE (AST_C3_BASE + 0x2400) /* Companion VIC */ +#define AST_C3_LPC_SLAVE_BASE (AST_C3_BASE + 0x2c00) /* Companion LPC SlLAVE */ +#define AST_C3_I2C_BASE (AST_C3_BASE + 0x3000) /* Companion I2C */ +#define AST_C3_SPI_BASE (AST_C3_BASE + 0x4000) /* Companion SPI */ +#define AST_C3_LPC_SPI_BASE (AST_C3_BASE + 0x4400) /* Companion LPC SPI */ +#define AST_C3_UART_DMA_BASE (AST_C3_BASE + 0x4800) /* Companion UART DMA */ +#define AST_C3_SPI_CONTROL_BASE (AST_C3_BASE + 0x4c00) /* Companion SPI CONTROL */ +#define AST_C3_SPI_SHADOW_SRAM_BASE (AST_C3_BASE + 0x5000) /* Companion SPI SHADOW SRAM */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h b/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h new file mode 100644 index 0000000..3ebc91b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1520_irqs.h @@ -0,0 +1,107 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1520_IRQS_H_ +#define _AST1520_IRQS_H_ 1 + + +#ifdef CONFIG_PCIE +#define NR_IRQS (ARCH_NR_GPIOS +ARCH_NR_PCIE + AST_VIC_NUM) + +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM +//------------------- --------------------------------------------------------------- + +#define ARCH_NR_PCIE 5 +#define IRQ_PCIE_CHAIN IRQ_PCIE +#define IRQ_PCIE_CHAIN_START (ARCH_NR_GPIOS + AST_VIC_NUM) + +#define IRQ_PCIE_INTA (IRQ_PCIE_CHAIN_START) +#define IRQ_PCIE_INTB (IRQ_PCIE_CHAIN_START + 1) +#define IRQ_PCIE_INTC (IRQ_PCIE_CHAIN_START + 2) +#define IRQ_PCIE_INTD (IRQ_PCIE_CHAIN_START + 3) +#define IRQ_PCIE_MSI0 (IRQ_PCIE_INTD + 1) // support max 32 MSI + +#else +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM +//------------------- --------------------------------------------------------------- +#endif + +#define AST_VIC_NUM 51 + +//#define IRQ_SDRAM_ECC 0 +//#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +//#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +//#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 3 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +//#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +//#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +//#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +//#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +//#define IRQ_UART2 33 /* UART 3 interrupt */ +//#define IRQ_UART3 34 /* UART 4 interrupt */ +//#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +//#define IRQ_TIMER4 36 +//#define IRQ_TIMER5 37 +//#define IRQ_TIMER6 38 +//#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +//#define IRQ_SGPIO_MASTER 40 +//#define IRQ_SGPIO_SLAVE 41 +#define IRQ_PCIE 41 + +#define IRQ_MCTP 42 +//#define IRQ_JTAG 43 +#define IRQ_PS2 44 +#define IRQ_CPU1 45 +//#define IRQ_MAILBOX 46 +#define IRQ_EXT0_GPIOL1 47 +#define IRQ_EXT1_GPIOL3 48 +#define IRQ_EXT2_GPIOM3 49 +#define IRQ_EXT3_GPIOM3 50 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast1520_platform.h b/arch/arm/mach-aspeed/include/mach/ast1520_platform.h new file mode 100644 index 0000000..daded5d --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast1520_platform.h @@ -0,0 +1,61 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST1520_PLATFORM_H_ +#define _AST1520_PLATFORM_H_ 1 + +#define AST_SRAM_SIZE (SZ_8K) + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_SPI_BASE 0x1E620000 /* SPI CONTROLLER */ + +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC SDRAM*/ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_I2S_BASE 0x1E6E5000 /* I2S */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_PCIE_BASE 0x1E6ED000 /* PCIE */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SD */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~2*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART3 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ + +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ + +#define AST_SPI0_MEM 0x20000000 + +#define AST_PCIE_WIN_BASE 0x70000000 +#define AST_PCIE_WIN_SIZE 0x01000000 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h new file mode 100644 index 0000000..50aece9 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2000_irqs.h @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2000_IRQS_H_ +#define _AST2000_IRQS_H_ 1 + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 + +#define IRQ_SPI 0 +#define IRQ_UART0 1 +#define IRQ_UART1 2 +#define IRQ_TIMER0 3 +#define IRQ_TIMER1 4 +#define IRQ_TIMER2 5 +#define IRQ_RTC 6 +#define IRQ_MAC0 7 +#define IRQ_GPIO_B0 8 +#define IRQ_UDC 9 +#define IRQ_PCI 10 +#define IRQ_GPIO_B1 11 +#define IRQ_GPIO_B2 12 +#define IRQ_GPIO_B3 13 +#define IRQ_LPC 14 +#define IRQ_I2C 15 +#define IRQ_USB11 16 +#define IRQ_VIDEO 17 +#define IRQ_CRYPTO 18 +#define IRQ_SCU 19 +#define IRQ_GPIO_B4 20 +#define IRQ_GPIO_B5 21 +#define IRQ_GPIO_B6 22 +#define IRQ_GPIO_A0 23 +#define IRQ_GPIO_A1 24 +#define IRQ_GPIO_A2 25 +#define IRQ_GPIO_A3 26 +#define IRQ_HDMA 27 +#define IRQ_GPIO_A4 28 +#define IRQ_GPIO_A5 29 +#define IRQ_GPIO_A6 30 +#define IRQ_WDT 31 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2000_platform.h b/arch/arm/mach-aspeed/include/mach/ast2000_platform.h new file mode 100644 index 0000000..ff34f5b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2000_platform.h @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2000_PLATFORM_H_ +#define _AST2000_PLATFORM_H_ 1 + +#define AST_MAC0_BASE 0x19c80000 /* MAC1 */ +#define AST_CRYPTO_BASE 0x1E6E0040 /* Crypto */ +#define AST_UDC11_BASE 0x1E6E0080 /* USB11 */ +#define AST_SCU0_BASE 0x1E6E0100 /* SCU1 */ +#define AST_LPC_BASE 0x1E6E0400 /* LPC */ +#define AST_I2C_BASE 0x1E6E0800 /* I2C */ +//---// +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +//...// +#define AST_HDMA_BASE 0x1E7c0000 /* HDMA */ +#define AST_TIMER_BASE 0x1E800000 /* TIMER0/1/2 */ +#define AST_RTC_BASE 0x1E820000 /* RTC */ +#define AST_UART0_BASE 0x1E840000 /* UART0 */ +#define AST_UART1_BASE 0x1E860000 /* UART1 */ +#define AST_SPI_BASE 0x1E880000 /* SPI */ +#define AST_GPIO_BASE 0x1E8A0000 /* GPIO */ +#define AST_WDT_BASE 0x1E8C0000 /* WDT */ +#define AST_SCU0_BASE 0x1E8E000c /* SCU2 */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h new file mode 100644 index 0000000..8513909 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2100_irqs.h @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2100_IRQS_H_ +#define _AST2100_IRQS_H_ 1 + + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART0 9 /* UART 1 interrupt */ +#define IRQ_UART1 10 /* UART 2 interrupt */ +//11 reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +//14 reserved +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC_SEC 22 +#define IRQ_RTC_DAY 23 +#define IRQ_RTC_HOUR 24 +#define IRQ_RTC_MIN 25 +#define IRQ_RTC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_PCI 30 +#define IRQ_AHBC 31 +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2100_platform.h b/arch/arm/mach-aspeed/include/mach/ast2100_platform.h new file mode 100644 index 0000000..2d635f7 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2100_platform.h @@ -0,0 +1,57 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2100_PLATFORM_H_ +#define _AST2100_PLATFORM_H_ 1 + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +#define AST_MDMA_BASE 0x1E740000 /* MDMA */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART0_BASE 0x1E783000 /* UART1 */ +#define AST_UART1_BASE 0x1E784000 /* UART2 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ + +#define ASPEED_VIC_STATUS_OFFSET 0x00 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h new file mode 100644 index 0000000..f0b880f --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2200_irqs.h @@ -0,0 +1,65 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2200_IRQS_H_ +#define _AST2200_IRQS_H_ 1 + +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#define AST_VIC_NUM 32 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART0 9 /* UART 1 interrupt */ +#define IRQ_UART1 10 /* UART 2 interrupt */ +//11 reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +//14 reserved +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC_SEC 22 +#define IRQ_RTC_DAY 23 +#define IRQ_RTC_HOUR 24 +#define IRQ_RTC_MIN 25 +#define IRQ_RTC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_PCI 30 +#define IRQ_AHBC 31 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2200_platform.h b/arch/arm/mach-aspeed/include/mach/ast2200_platform.h new file mode 100644 index 0000000..324e15b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2200_platform.h @@ -0,0 +1,55 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2200_PLATFORM_H_ +#define _AST2200_PLATFORM_H_ 1 + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC1_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC2_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* MMC */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ + +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_AHB_TO_PBUS_BASE 0x1E720000 /* APB -> PBUS */ +#define AST_MDMA_BASE 0x1E740000 /* MDMA */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART0_BASE 0x1E783000 /* UART1 */ +#define AST_UART1_BASE 0x1E784000 /* UART2 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h new file mode 100644 index 0000000..2d7b0c8 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2300_irqs.h @@ -0,0 +1,92 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2300_IRQS_H_ +#define _AST2300_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1070) +//----------VIC + GPIO + CVIC chain-------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS + AST_CVIC_NUM) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM) +//---------------CVIC--------------------------------------------------------------- +#define IRQ_C0_VIC_CHAIN IRQ_GPIOL1 +#define IRQ_C0_VIC_CHAIN_START (AST_VIC_NUM + ARCH_NR_GPIOS) +//------------------- --------------------------------------------------------------- +#else +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START AST_VIC_NUM + +#endif + + +#define AST_VIC_NUM 46 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 5 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +#define IRQ_UART3 33 /* UART 3 interrupt */ +#define IRQ_UART4 34 /* UART 4 interrupt */ +#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +#define IRQ_TIMER4 36 +#define IRQ_TIMER5 37 +#define IRQ_TIMER6 38 +#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +#define IRQ_SGPIO_MASTER 40 +#define IRQ_SGPIO_SLAVE 41 +#define IRQ_MCTP 42 +#define IRQ_JTAG 43 +//#define IRQ_RESERVED 44 +#define IRQ_CPU1 45 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2300_platform.h b/arch/arm/mach-aspeed/include/mach/ast2300_platform.h new file mode 100644 index 0000000..4898856 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2300_platform.h @@ -0,0 +1,72 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2300_PLATFORM_H_ +#define _AST2300_PLATFORM_H_ 1 + +#define AST_DRAM_BASE 0x40000000 +#define AST_SRAM_SIZE (SZ_16K) + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_SPI_BASE 0x1E630000 /* SPI CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* SDRAM CTRL */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ Controller */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SDHC */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_MBX_BASE 0x1E789200 /* MailBox */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ + +#define AST_LPC_BRIDGE 0x60000000 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h b/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h new file mode 100644 index 0000000..17c59da --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2400_irqs.h @@ -0,0 +1,96 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2400_IRQS_H_ +#define _AST2400_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1070) +#include <mach/ast1070_irqs.h> +#define MAX_AST1070_NR 2 +//----------VIC + CVIC + GPIO chain-------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + (AST_CVIC_NUM * MAX_AST1070_NR) + ARCH_NR_GPIOS) +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM + (AST_CVIC_NUM * MAX_AST1070_NR)) +//------------------- --------------------------------------------------------------- +#else +//--------------GPIO --------------------------------------------------------------- +#define ARCH_NR_GPIOS (GPIO_PORT_NUM*8) +#define IRQ_GPIO_CHAIN_START (AST_VIC_NUM) +//------------------- --------------------------------------------------------------- +#define NR_IRQS (AST_VIC_NUM + ARCH_NR_GPIOS) + +#endif + +#define AST_VIC_NUM 51 + +#define IRQ_SDRAM_ECC 0 +#define IRQ_MIC 1 +#define IRQ_MAC0 2 /* MAC 1 interrupt */ +#define IRQ_MAC1 3 /* MAC 2 interrupt */ +#define IRQ_CRYPTO 4 +#define IRQ_USB20_HUB 5 +#define IRQ_EHCI 5 +#define IRQ_XDMA 6 +#define IRQ_VIDEO 7 +#define IRQ_LPC 8 +#define IRQ_UART1 9 /* UART 1 interrupt */ +#define IRQ_UART0 10 /* UART 5 interrupt */ +//11 Reserved +#define IRQ_I2C 12 +#define IRQ_UDC11 13 +#define IRQ_UHCI 14 +#define IRQ_PECI 15 +#define IRQ_TIMER0 16 /* TIMER 1 interrupt */ +#define IRQ_TIMER1 17 /* TIMER 2 interrupt */ +#define IRQ_TIMER2 18 /* TIMER 3 interrupt */ +#define IRQ_SMC 19 +#define IRQ_GPIO 20 +#define IRQ_SCU 21 +#define IRQ_RTC 22 +//23 , 24 reserverd +#define IRQ_CRT 25 +#define IRQ_SDHC 26 +#define IRQ_WDT 27 +#define IRQ_TACHO 28 +#define IRQ_2D 29 +#define IRQ_SYS_WAKEUP 30 +#define IRQ_ADC 31 +#define IRQ_UART2 32 /* UART 2 interrupt */ +#define IRQ_UART3 33 /* UART 3 interrupt */ +#define IRQ_UART4 34 /* UART 4 interrupt */ +#define IRQ_TIMER3 35 /* TIMER 4 interrupt */ +#define IRQ_TIMER4 36 +#define IRQ_TIMER5 37 +#define IRQ_TIMER6 38 +#define IRQ_TIMER7 39 /* TIMER 8 interrupt */ +#define IRQ_SGPIO_MASTER 40 +#define IRQ_SGPIO_SLAVE 41 +#define IRQ_MCTP 42 +#define IRQ_JTAG 43 +//#define IRQ_RESERVED 44 +#define IRQ_CPU1 45 +#define IRQ_MAILBOX 46 +#define IRQ_EXT0 47 +#define IRQ_EXT1 48 +#define IRQ_EXT2 49 +#define IRQ_EXT3 50 + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast2400_platform.h b/arch/arm/mach-aspeed/include/mach/ast2400_platform.h new file mode 100644 index 0000000..e507953 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast2400_platform.h @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST2400_PLATFORM_H_ +#define _AST2400_PLATFORM_H_ 1 + +#define AST_DRAM_BASE 0x40000000 + +#define AST_SRAM_SIZE (SZ_16K*2) + +#define AST_OLD_SMC_BASE 0x10000000 /*Legacy BMC Static Memory */ +#define AST_OLD_SMC_CTRL_BASE 0x16000000 /*Legacy BMC Static Memory Ctrl*/ + +#define AST_AHB_CTRL_BASE 0x1E600000 /* AHB CONTROLLER */ + +#define AST_FMC_BASE 0x1E620000 /* NEW SMC CONTROLLER */ +#define AST_SPI_BASE 0x1E630000 /* SPI CONTROLLER */ +#define AST_MIC_BASE 0x1E640000 /* MIC CONTROLLER */ +#define AST_MAC0_BASE 0x1E660000 /* MAC1 */ +#define AST_MAC1_BASE 0x1E680000 /* MAC2 */ + +#define AST_USB20_BASE 0x1E6A0000 /* USB 2.0 VIRTUAL HUB CONTROLLER */ +#define AST_EHCI_BASE 0x1E6A1000 /* USB 2.0 HOST CONTROLLER */ +#define AST_UHCI_BASE 0x1E6B0000 /* USB 1.1 HOST CONTROLLER */ +#define AST_VIC_BASE 0x1E6C0000 /* VIC */ +#define AST_SDMC_BASE 0x1E6E0000 /* SDRAM CTRL */ +#define AST_UDC11_BASE 0x1E6E1000 /* USB11 */ +#define AST_SCU_BASE 0x1E6E2000 /* SCU */ +#define AST_CRYPTO_BASE 0x1E6E3000 /* Crypto */ +#define AST_JTAG_BASE 0x1E6E4000 /* JTAG */ +#define AST_GRAPHIC_BASE 0x1E6E6000 /* Graphics */ +#define AST_XDMA_BASE 0x1E6E7000 /* XDMA */ +#define AST_MCTP_BASE 0x1E6E8000 /* MCTP */ +#define AST_ADC_BASE 0x1E6E9000 /* ADC */ + +#define AST_LPC_PLUS_BASE 0x1E6EC000 /* LPC+ Controller */ + +#define AST_VIDEO_BASE 0x1E700000 /* VIDEO ENGINE */ +#define AST_SRAM_BASE 0x1E720000 /* SRAM */ +#define AST_SDHC_BASE 0x1E740000 /* SDHC */ +#define AST_2D_BASE 0x1E760000 /* 2D */ +#define AST_GPIO_BASE 0x1E780000 /* GPIO */ +#define AST_RTC_BASE 0x1E781000 /* RTC */ +#define AST_TIMER_BASE 0x1E782000 /* TIMER #0~7*/ +#define AST_UART1_BASE 0x1E783000 /* UART1 */ +#define AST_UART0_BASE 0x1E784000 /* UART5 */ +#define AST_WDT_BASE 0x1E785000 /* WDT */ +#define AST_PWM_BASE 0x1E786000 /* PWM */ +#define AST_VUART0_BASE 0x1E787000 /* VUART1 */ +#define AST_PUART_BASE 0x1E788000 /* PUART */ +#define AST_LPC_BASE 0x1E789000 /* LPC */ +#define AST_MBX_BASE 0x1E789200 /* MailBox */ +#define AST_I2C_BASE 0x1E78A000 /* I2C */ +#define AST_PECI_BASE 0x1E78B000 /* PECI */ +#define AST_PCIARBITER_BASE 0x1E78C000 /* PCI ARBITER */ +#define AST_UART2_BASE 0x1E78D000 /* UART2 */ +#define AST_UART3_BASE 0x1E78E000 /* UART3 */ +#define AST_UART4_BASE 0x1E78F000 /* UART4 */ +#define AST_SPI0_MEM 0x30000000 + +#define AST_LPC_PLUS_BRIDGE 0x70000000 + +#define AST_LPC_BRIDGE 0x60000000 + + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h b/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h new file mode 100644 index 0000000..48d5ef6 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_gpio_irqs.h @@ -0,0 +1,276 @@ +/* + * file : gpio_irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _GPIO_IRQS_H_ +#define _GPIO_IRQS_H_ 1 + +#if defined(CONFIG_ARCH_AST1010) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2000) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2100) +#define GPIO_PORT_NUM 8 +#elif defined(CONFIG_ARCH_AST2200) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2300) +#define GPIO_PORT_NUM 19 +#elif defined(CONFIG_ARCH_AST2400) +#define GPIO_PORT_NUM 28 +#elif defined(CONFIG_ARCH_AST1520) +#define GPIO_PORT_NUM 28 +#else +#err "no define for gpio irqs.h" +#endif + + +#define IRQ_GPIOA0 (IRQ_GPIO_CHAIN_START + 0) +#define IRQ_GPIOA1 (IRQ_GPIO_CHAIN_START + 1) +#define IRQ_GPIOA2 (IRQ_GPIO_CHAIN_START + 2) +#define IRQ_GPIOA3 (IRQ_GPIO_CHAIN_START + 3) +#define IRQ_GPIOA4 (IRQ_GPIO_CHAIN_START + 4) +#define IRQ_GPIOA5 (IRQ_GPIO_CHAIN_START + 5) +#define IRQ_GPIOA6 (IRQ_GPIO_CHAIN_START + 6) +#define IRQ_GPIOA7 (IRQ_GPIO_CHAIN_START + 7) +#define IRQ_GPIOB0 (IRQ_GPIO_CHAIN_START + 8) +#define IRQ_GPIOB1 (IRQ_GPIO_CHAIN_START + 9) +#define IRQ_GPIOB2 (IRQ_GPIO_CHAIN_START + 10) +#define IRQ_GPIOB3 (IRQ_GPIO_CHAIN_START + 11) +#define IRQ_GPIOB4 (IRQ_GPIO_CHAIN_START + 12) +#define IRQ_GPIOB5 (IRQ_GPIO_CHAIN_START + 13) +#define IRQ_GPIOB6 (IRQ_GPIO_CHAIN_START + 14) +#define IRQ_GPIOB7 (IRQ_GPIO_CHAIN_START + 15) +#define IRQ_GPIOC0 (IRQ_GPIO_CHAIN_START + 16) +#define IRQ_GPIOC1 (IRQ_GPIO_CHAIN_START + 17) +#define IRQ_GPIOC2 (IRQ_GPIO_CHAIN_START + 18) +#define IRQ_GPIOC3 (IRQ_GPIO_CHAIN_START + 19) +#define IRQ_GPIOC4 (IRQ_GPIO_CHAIN_START + 20) +#define IRQ_GPIOC5 (IRQ_GPIO_CHAIN_START + 21) +#define IRQ_GPIOC6 (IRQ_GPIO_CHAIN_START + 22) +#define IRQ_GPIOC7 (IRQ_GPIO_CHAIN_START + 23) +#define IRQ_GPIOD0 (IRQ_GPIO_CHAIN_START + 24) +#define IRQ_GPIOD1 (IRQ_GPIO_CHAIN_START + 25) +#define IRQ_GPIOD2 (IRQ_GPIO_CHAIN_START + 26) +#define IRQ_GPIOD3 (IRQ_GPIO_CHAIN_START + 27) +#define IRQ_GPIOD4 (IRQ_GPIO_CHAIN_START + 28) +#define IRQ_GPIOD5 (IRQ_GPIO_CHAIN_START + 29) +#define IRQ_GPIOD6 (IRQ_GPIO_CHAIN_START + 30) +#define IRQ_GPIOD7 (IRQ_GPIO_CHAIN_START + 31) +#define IRQ_GPIOE0 (IRQ_GPIO_CHAIN_START + 32) +#define IRQ_GPIOE1 (IRQ_GPIO_CHAIN_START + 33) +#define IRQ_GPIOE2 (IRQ_GPIO_CHAIN_START + 34) +#define IRQ_GPIOE3 (IRQ_GPIO_CHAIN_START + 35) +#define IRQ_GPIOE4 (IRQ_GPIO_CHAIN_START + 36) +#define IRQ_GPIOE5 (IRQ_GPIO_CHAIN_START + 37) +#define IRQ_GPIOE6 (IRQ_GPIO_CHAIN_START + 38) +#define IRQ_GPIOE7 (IRQ_GPIO_CHAIN_START + 39) +#define IRQ_GPIOF0 (IRQ_GPIO_CHAIN_START + 40) +#define IRQ_GPIOF1 (IRQ_GPIO_CHAIN_START + 41) +#define IRQ_GPIOF2 (IRQ_GPIO_CHAIN_START + 42) +#define IRQ_GPIOF3 (IRQ_GPIO_CHAIN_START + 43) +#define IRQ_GPIOF4 (IRQ_GPIO_CHAIN_START + 44) +#define IRQ_GPIOF5 (IRQ_GPIO_CHAIN_START + 45) +#define IRQ_GPIOF6 (IRQ_GPIO_CHAIN_START + 46) +#define IRQ_GPIOF7 (IRQ_GPIO_CHAIN_START + 47) +#define IRQ_GPIOG0 (IRQ_GPIO_CHAIN_START + 48) +#define IRQ_GPIOG1 (IRQ_GPIO_CHAIN_START + 49) +#define IRQ_GPIOG2 (IRQ_GPIO_CHAIN_START + 50) +#define IRQ_GPIOG3 (IRQ_GPIO_CHAIN_START + 51) +#define IRQ_GPIOG4 (IRQ_GPIO_CHAIN_START + 52) +#define IRQ_GPIOG5 (IRQ_GPIO_CHAIN_START + 53) +#define IRQ_GPIOG6 (IRQ_GPIO_CHAIN_START + 54) +#define IRQ_GPIOG7 (IRQ_GPIO_CHAIN_START + 55) +#define IRQ_GPIOH0 (IRQ_GPIO_CHAIN_START + 56) +#define IRQ_GPIOH1 (IRQ_GPIO_CHAIN_START + 57) +#define IRQ_GPIOH2 (IRQ_GPIO_CHAIN_START + 58) +#define IRQ_GPIOH3 (IRQ_GPIO_CHAIN_START + 59) +#define IRQ_GPIOH4 (IRQ_GPIO_CHAIN_START + 60) +#define IRQ_GPIOH5 (IRQ_GPIO_CHAIN_START + 61) +#define IRQ_GPIOH6 (IRQ_GPIO_CHAIN_START + 62) +#define IRQ_GPIOH7 (IRQ_GPIO_CHAIN_START + 63) + +#if defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST2300) || defined(CONFIG_ARCH_AST1520) + +#define IRQ_GPIOI0 (IRQ_GPIO_CHAIN_START + 64) +#define IRQ_GPIOI1 (IRQ_GPIO_CHAIN_START + 65) +#define IRQ_GPIOI2 (IRQ_GPIO_CHAIN_START + 66) +#define IRQ_GPIOI3 (IRQ_GPIO_CHAIN_START + 67) +#define IRQ_GPIOI4 (IRQ_GPIO_CHAIN_START + 68) +#define IRQ_GPIOI5 (IRQ_GPIO_CHAIN_START + 69) +#define IRQ_GPIOI6 (IRQ_GPIO_CHAIN_START + 70) +#define IRQ_GPIOI7 (IRQ_GPIO_CHAIN_START + 71) +#define IRQ_GPIOJ0 (IRQ_GPIO_CHAIN_START + 72) +#define IRQ_GPIOJ1 (IRQ_GPIO_CHAIN_START + 73) +#define IRQ_GPIOJ2 (IRQ_GPIO_CHAIN_START + 74) +#define IRQ_GPIOJ3 (IRQ_GPIO_CHAIN_START + 75) +#define IRQ_GPIOJ4 (IRQ_GPIO_CHAIN_START + 76) +#define IRQ_GPIOJ5 (IRQ_GPIO_CHAIN_START + 77) +#define IRQ_GPIOJ6 (IRQ_GPIO_CHAIN_START + 78) +#define IRQ_GPIOJ7 (IRQ_GPIO_CHAIN_START + 79) +#define IRQ_GPIOK0 (IRQ_GPIO_CHAIN_START + 80) +#define IRQ_GPIOK1 (IRQ_GPIO_CHAIN_START + 81) +#define IRQ_GPIOK2 (IRQ_GPIO_CHAIN_START + 82) +#define IRQ_GPIOK3 (IRQ_GPIO_CHAIN_START + 83) +#define IRQ_GPIOK4 (IRQ_GPIO_CHAIN_START + 84) +#define IRQ_GPIOK5 (IRQ_GPIO_CHAIN_START + 85) +#define IRQ_GPIOK6 (IRQ_GPIO_CHAIN_START + 86) +#define IRQ_GPIOK7 (IRQ_GPIO_CHAIN_START + 87) +#define IRQ_GPIOL0 (IRQ_GPIO_CHAIN_START + 88) +#define IRQ_GPIOL1 (IRQ_GPIO_CHAIN_START + 89) +#define IRQ_GPIOL2 (IRQ_GPIO_CHAIN_START + 90) +#define IRQ_GPIOL3 (IRQ_GPIO_CHAIN_START + 91) +#define IRQ_GPIOL4 (IRQ_GPIO_CHAIN_START + 92) +#define IRQ_GPIOL5 (IRQ_GPIO_CHAIN_START + 93) +#define IRQ_GPIOL6 (IRQ_GPIO_CHAIN_START + 94) +#define IRQ_GPIOL7 (IRQ_GPIO_CHAIN_START + 95) +#define IRQ_GPIOM0 (IRQ_GPIO_CHAIN_START + 96) +#define IRQ_GPIOM1 (IRQ_GPIO_CHAIN_START + 97) +#define IRQ_GPIOM2 (IRQ_GPIO_CHAIN_START + 98) +#define IRQ_GPIOM3 (IRQ_GPIO_CHAIN_START + 99) +#define IRQ_GPIOM4 (IRQ_GPIO_CHAIN_START + 100) +#define IRQ_GPIOM5 (IRQ_GPIO_CHAIN_START + 101) +#define IRQ_GPIOM6 (IRQ_GPIO_CHAIN_START + 102) +#define IRQ_GPIOM7 (IRQ_GPIO_CHAIN_START + 103) +#define IRQ_GPION0 (IRQ_GPIO_CHAIN_START + 104) +#define IRQ_GPION1 (IRQ_GPIO_CHAIN_START + 105) +#define IRQ_GPION2 (IRQ_GPIO_CHAIN_START + 106) +#define IRQ_GPION3 (IRQ_GPIO_CHAIN_START + 107) +#define IRQ_GPION4 (IRQ_GPIO_CHAIN_START + 108) +#define IRQ_GPION5 (IRQ_GPIO_CHAIN_START + 109) +#define IRQ_GPION6 (IRQ_GPIO_CHAIN_START + 110) +#define IRQ_GPION7 (IRQ_GPIO_CHAIN_START + 111) +#define IRQ_GPIOO0 (IRQ_GPIO_CHAIN_START + 112) +#define IRQ_GPIOO1 (IRQ_GPIO_CHAIN_START + 113) +#define IRQ_GPIOO2 (IRQ_GPIO_CHAIN_START + 114) +#define IRQ_GPIOO3 (IRQ_GPIO_CHAIN_START + 115) +#define IRQ_GPIOO4 (IRQ_GPIO_CHAIN_START + 116) +#define IRQ_GPIOO5 (IRQ_GPIO_CHAIN_START + 117) +#define IRQ_GPIOO6 (IRQ_GPIO_CHAIN_START + 118) +#define IRQ_GPIOO7 (IRQ_GPIO_CHAIN_START + 119) +#define IRQ_GPIOP0 (IRQ_GPIO_CHAIN_START + 120) +#define IRQ_GPIOP1 (IRQ_GPIO_CHAIN_START + 121) +#define IRQ_GPIOP2 (IRQ_GPIO_CHAIN_START + 122) +#define IRQ_GPIOP3 (IRQ_GPIO_CHAIN_START + 123) +#define IRQ_GPIOP4 (IRQ_GPIO_CHAIN_START + 124) +#define IRQ_GPIOP5 (IRQ_GPIO_CHAIN_START + 125) +#define IRQ_GPIOP6 (IRQ_GPIO_CHAIN_START + 126) +#define IRQ_GPIOP7 (IRQ_GPIO_CHAIN_START + 127) +#define IRQ_GPIOQ0 (IRQ_GPIO_CHAIN_START + 128) +#define IRQ_GPIOQ1 (IRQ_GPIO_CHAIN_START + 129) +#define IRQ_GPIOQ2 (IRQ_GPIO_CHAIN_START + 130) +#define IRQ_GPIOQ3 (IRQ_GPIO_CHAIN_START + 131) +#define IRQ_GPIOQ4 (IRQ_GPIO_CHAIN_START + 132) +#define IRQ_GPIOQ5 (IRQ_GPIO_CHAIN_START + 133) +#define IRQ_GPIOQ6 (IRQ_GPIO_CHAIN_START + 134) +#define IRQ_GPIOQ7 (IRQ_GPIO_CHAIN_START + 135) +#define IRQ_GPIOR0 (IRQ_GPIO_CHAIN_START + 136) +#define IRQ_GPIOR1 (IRQ_GPIO_CHAIN_START + 137) +#define IRQ_GPIOR2 (IRQ_GPIO_CHAIN_START + 138) +#define IRQ_GPIOR3 (IRQ_GPIO_CHAIN_START + 139) +#define IRQ_GPIOR4 (IRQ_GPIO_CHAIN_START + 140) +#define IRQ_GPIOR5 (IRQ_GPIO_CHAIN_START + 141) +#define IRQ_GPIOR6 (IRQ_GPIO_CHAIN_START + 142) +#define IRQ_GPIOR7 (IRQ_GPIO_CHAIN_START + 143) +#define IRQ_GPIOS0 (IRQ_GPIO_CHAIN_START + 144) +#define IRQ_GPIOS1 (IRQ_GPIO_CHAIN_START + 145) +#define IRQ_GPIOS2 (IRQ_GPIO_CHAIN_START + 146) +#define IRQ_GPIOS3 (IRQ_GPIO_CHAIN_START + 147) +#define IRQ_GPIOS4 (IRQ_GPIO_CHAIN_START + 148) +#define IRQ_GPIOS5 (IRQ_GPIO_CHAIN_START + 149) +#define IRQ_GPIOS6 (IRQ_GPIO_CHAIN_START + 150) +#define IRQ_GPIOS7 (IRQ_GPIO_CHAIN_START + 151) + +#if defined(CONFIG_ARCH_AST2400) || defined(CONFIG_ARCH_AST1520) + +#define IRQ_GPIOT0 (IRQ_GPIO_CHAIN_START + 152) +#define IRQ_GPIOT1 (IRQ_GPIO_CHAIN_START + 153) +#define IRQ_GPIOT2 (IRQ_GPIO_CHAIN_START + 154) +#define IRQ_GPIOT3 (IRQ_GPIO_CHAIN_START + 155) +#define IRQ_GPIOT4 (IRQ_GPIO_CHAIN_START + 156) +#define IRQ_GPIOT5 (IRQ_GPIO_CHAIN_START + 157) +#define IRQ_GPIOT6 (IRQ_GPIO_CHAIN_START + 158) +#define IRQ_GPIOT7 (IRQ_GPIO_CHAIN_START + 159) +#define IRQ_GPIOU0 (IRQ_GPIO_CHAIN_START + 161) +#define IRQ_GPIOU1 (IRQ_GPIO_CHAIN_START + 162) +#define IRQ_GPIOU2 (IRQ_GPIO_CHAIN_START + 163) +#define IRQ_GPIOU3 (IRQ_GPIO_CHAIN_START + 164) +#define IRQ_GPIOU4 (IRQ_GPIO_CHAIN_START + 165) +#define IRQ_GPIOU5 (IRQ_GPIO_CHAIN_START + 166) +#define IRQ_GPIOU6 (IRQ_GPIO_CHAIN_START + 167) +#define IRQ_GPIOU7 (IRQ_GPIO_CHAIN_START + 168) +#define IRQ_GPIOV0 (IRQ_GPIO_CHAIN_START + 169) +#define IRQ_GPIOV1 (IRQ_GPIO_CHAIN_START + 170) +#define IRQ_GPIOV2 (IRQ_GPIO_CHAIN_START + 171) +#define IRQ_GPIOV3 (IRQ_GPIO_CHAIN_START + 172) +#define IRQ_GPIOV4 (IRQ_GPIO_CHAIN_START + 173) +#define IRQ_GPIOV5 (IRQ_GPIO_CHAIN_START + 174) +#define IRQ_GPIOV6 (IRQ_GPIO_CHAIN_START + 175) +#define IRQ_GPIOV7 (IRQ_GPIO_CHAIN_START + 176) +#define IRQ_GPIOW0 (IRQ_GPIO_CHAIN_START + 177) +#define IRQ_GPIOW1 (IRQ_GPIO_CHAIN_START + 178) +#define IRQ_GPIOW2 (IRQ_GPIO_CHAIN_START + 179) +#define IRQ_GPIOW3 (IRQ_GPIO_CHAIN_START + 181) +#define IRQ_GPIOW4 (IRQ_GPIO_CHAIN_START + 182) +#define IRQ_GPIOW5 (IRQ_GPIO_CHAIN_START + 183) +#define IRQ_GPIOW6 (IRQ_GPIO_CHAIN_START + 184) +#define IRQ_GPIOW7 (IRQ_GPIO_CHAIN_START + 185) +#define IRQ_GPIOX0 (IRQ_GPIO_CHAIN_START + 186) +#define IRQ_GPIOX1 (IRQ_GPIO_CHAIN_START + 187) +#define IRQ_GPIOX2 (IRQ_GPIO_CHAIN_START + 188) +#define IRQ_GPIOX3 (IRQ_GPIO_CHAIN_START + 189) +#define IRQ_GPIOX4 (IRQ_GPIO_CHAIN_START + 190) +#define IRQ_GPIOX5 (IRQ_GPIO_CHAIN_START + 191) +#define IRQ_GPIOX6 (IRQ_GPIO_CHAIN_START + 192) +#define IRQ_GPIOX7 (IRQ_GPIO_CHAIN_START + 193) +#define IRQ_GPIOY0 (IRQ_GPIO_CHAIN_START + 194) +#define IRQ_GPIOY1 (IRQ_GPIO_CHAIN_START + 195) +#define IRQ_GPIOY2 (IRQ_GPIO_CHAIN_START + 196) +#define IRQ_GPIOY3 (IRQ_GPIO_CHAIN_START + 197) +#define IRQ_GPIOY4 (IRQ_GPIO_CHAIN_START + 198) +#define IRQ_GPIOY5 (IRQ_GPIO_CHAIN_START + 199) +#define IRQ_GPIOY6 (IRQ_GPIO_CHAIN_START + 200) +#define IRQ_GPIOY7 (IRQ_GPIO_CHAIN_START + 201) +#define IRQ_GPIOZ0 (IRQ_GPIO_CHAIN_START + 202) +#define IRQ_GPIOZ1 (IRQ_GPIO_CHAIN_START + 203) +#define IRQ_GPIOZ2 (IRQ_GPIO_CHAIN_START + 204) +#define IRQ_GPIOZ3 (IRQ_GPIO_CHAIN_START + 205) +#define IRQ_GPIOZ4 (IRQ_GPIO_CHAIN_START + 206) +#define IRQ_GPIOZ5 (IRQ_GPIO_CHAIN_START + 207) +#define IRQ_GPIOZ6 (IRQ_GPIO_CHAIN_START + 208) +#define IRQ_GPIOZ7 (IRQ_GPIO_CHAIN_START + 209) +#define IRQ_GPIOAA0 (IRQ_GPIO_CHAIN_START + 210) +#define IRQ_GPIOAA1 (IRQ_GPIO_CHAIN_START + 211) +#define IRQ_GPIOAA2 (IRQ_GPIO_CHAIN_START + 212) +#define IRQ_GPIOAA3 (IRQ_GPIO_CHAIN_START + 213) +#define IRQ_GPIOAA4 (IRQ_GPIO_CHAIN_START + 214) +#define IRQ_GPIOAA5 (IRQ_GPIO_CHAIN_START + 215) +#define IRQ_GPIOAA6 (IRQ_GPIO_CHAIN_START + 216) +#define IRQ_GPIOAA7 (IRQ_GPIO_CHAIN_START + 217) +#define IRQ_GPIOBB0 (IRQ_GPIO_CHAIN_START + 218) +#define IRQ_GPIOBB1 (IRQ_GPIO_CHAIN_START + 219) +#define IRQ_GPIOBB2 (IRQ_GPIO_CHAIN_START + 220) +#define IRQ_GPIOBB3 (IRQ_GPIO_CHAIN_START + 221) +#define IRQ_GPIOBB4 (IRQ_GPIO_CHAIN_START + 222) +#define IRQ_GPIOBB5 (IRQ_GPIO_CHAIN_START + 223) +#define IRQ_GPIOBB6 (IRQ_GPIO_CHAIN_START + 224) +#define IRQ_GPIOBB7 (IRQ_GPIO_CHAIN_START + 225) +#endif + +#endif +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_kcs.h b/arch/arm/mach-aspeed/include/mach/ast_kcs.h new file mode 100644 index 0000000..9bcd6fc --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_kcs.h @@ -0,0 +1,147 @@ +/**************************************************************** + ** ** + ** (C)Copyright 2006-2009, American Megatrends Inc. ** + ** ** + ** All Rights Reserved. ** + ** ** + ** 5555 Oakbrook Pkwy Suite 200, Norcross ** + ** ** + ** Georgia - 30093, USA. Phone-(770)-246-8600. ** + ** ** + ****************************************************************/ + +/**************************************************************** + * + * ast_kcs.h + * ASPEED AST2100/2050/2200/2150/2300 LPC controller KCS-related + * definitions, macros, prototypes + * +*****************************************************************/ + +#ifndef __AST_KCS_H__ +#define __AST_KCS_H__ + +#define AST_KCS_REG_BASE 0x1E789000 +#define AST_KCS_REG_SIZE SZ_4K +#define AST_KCS_IRQ 8 + +#if defined SOC_AST2300 +#define AST_KCS_CHANNEL_NUM 4 +#else +#define AST_KCS_CHANNEL_NUM 3 +#endif + +#define ERROR_STATE 0xC0 + +/* channel 1 I/O port address : 0xCA0 0xCA4*/ +#define AST_KCS_ADR1_HI 0x0C +#define AST_KCS_ADR1_LO 0xA0 + +/* channel 2 I/O port address : 0xCA8 0xCAC*/ +#define AST_KCS_ADR2_HI 0x0C +#define AST_KCS_ADR2_LO 0xA8 + +/* channel 3 I/O port address : 0xCA2 0xCA3*/ +#define AST_KCS_ADR3_HI 0x0C +#define AST_KCS_ADR3_LO 0xA2 + +/* channel 4 I/O port address : 0xCA6 0xCA7 */ +#define AST_KCS_ADR4 0x0CA70CA6 + +/* KCS-related registers of AST LPC controller */ +#define AST_LPC_HICR0 0x00 +#define AST_LPC_HICR1 0x04 +#define AST_LPC_HICR2 0x08 +#define AST_LPC_HICR3 0x0C +#define AST_LPC_HICR4 0x10 +#define AST_LPC_LADR3H 0x14 +#define AST_LPC_LADR3L 0x18 +#define AST_LPC_LADR12H 0x1C +#define AST_LPC_LADR12L 0x20 +#define AST_LPC_IDR1 0x24 +#define AST_LPC_IDR2 0x28 +#define AST_LPC_IDR3 0x2C +#define AST_LPC_ODR1 0x30 +#define AST_LPC_ODR2 0x34 +#define AST_LPC_ODR3 0x38 +#define AST_LPC_STR1 0x3C +#define AST_LPC_STR2 0x40 +#define AST_LPC_STR3 0x44 +#define AST_LPC_SIRQCR0 0x70 +#define AST_LPC_SIRQCR1 0x74 +#define AST_LPC_SIRQCR2 0x78 +#define AST_LPC_SIRQCR3 0x7C +#define AST_LPC_HICR5 0x80 +#define AST_LPC_HICR6 0x84 + +#if defined SOC_AST2300 +#define AST_LPC_HICRB 0x100 +#define AST_LPC_IDR4 0x114 +#define AST_LPC_ODR4 0x118 +#define AST_LPC_STR4 0x11C +#define AST_LPC_LADR4 0x110 +#endif + +#define AST_LPC_IDR_CH(ch) (AST_LPC_IDR1 + (ch * 0x04)) +#define AST_LPC_ODR_CH(ch) (AST_LPC_ODR1 + (ch * 0x04)) +#define AST_LPC_STR_CH(ch) (AST_LPC_STR1 + (ch * 0x04)) + +//#define AST_LPC_STR_CH(ch) (ch==3)?AST_LPC_STR4:(AST_LPC_STR1 + (ch * 0x04)) + +/* bits of HICR0 */ +#define AST_LPC_HICR0_LPC3E 0x80 +#define AST_LPC_HICR0_LPC2E 0x40 +#define AST_LPC_HICR0_LPC1E 0x20 +#define AST_LPC_HICR0_SDWNE 0x08 +#define AST_LPC_HICR0_PMEE 0x04 + +/* bits of HICR1 */ +#define AST_LPC_HICR1_LPCBSY 0x80 +#define AST_LPC_HICR1_CLKREQ 0x40 +#define AST_LPC_HICR1_IRQBSY 0x20 +#define AST_LPC_HICR1_LRSTB 0x10 +#define AST_LPC_HICR1_SDWNB 0x08 +#define AST_LPC_HICR1_PMEB 0x04 + +/* bits of HICR2, interrupt control register */ +#define AST_LPC_HICR2_LRST 0x40 +#define AST_LPC_HICR2_SDWN 0x20 +#define AST_LPC_HICR2_ABRT 0x10 +#define AST_LPC_HICR2_IBFIE3 0x08 +#define AST_LPC_HICR2_IBFIE2 0x04 +#define AST_LPC_HICR2_IBFIE1 0x02 +#define AST_LPC_HICR2_ERRIE 0x01 + +/* bits of HICR3, pin states regsiter */ +#define AST_LPC_HICR3_LFRAME 0x80 +#define AST_LPC_HICR3_CLKRUN 0x40 +#define AST_LPC_HICR3_SERIRQ 0x20 +#define AST_LPC_HICR3_LRESET 0x10 +#define AST_LPC_HICR3_LPCPD 0x08 +#define AST_LPC_HICR3_PME 0x04 + +/* bits of HICR4, selection register */ +#define AST_LPC_HICR4_LADR12SEL 0x80 +#define AST_LPC_HICR4_KCSENBL 0x04 +#define AST_LPC_HICR4_BTENBL 0x01 + +/* bits of STR[1:3], data full register */ +#define AST_LPC_STR_CD 0x08 +#define AST_LPC_STR_SMS_ATN 0x04 +#define AST_LPC_STR_IBFA 0x02 +#define AST_LPC_STR_OBFA 0x01 + +/* bits of HICR6 */ +#define AST_LPC_HICR6_SNP1_STR 0x02 +#define AST_LPC_HICR6_SNP0_STR 0x01 + +#if defined SOC_AST2300 +/* bits of HICRB */ +#define AST_LPC_HICRB0_KCS4E 0x01 +#define AST_LPC_HICRB0_KCS4INTE 0x02 + + +#endif + +#endif /* ! __AST_KCS_H__ */ + diff --git a/arch/arm/mach-aspeed/include/mach/ast_lcd.h b/arch/arm/mach-aspeed/include/mach/ast_lcd.h new file mode 100644 index 0000000..20963eb --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_lcd.h @@ -0,0 +1,61 @@ + /******************************************************************************** +* File Name : drivers/video/ast_lcd.h +* Author : Ryan Chen +* Description : ASPEED LCD Panel Timing +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/12/27 Ryan Chen create this file +* +* +********************************************************************************/ +#include <linux/fb.h> + +//# Define IO __ for control +#define YUV_MODE 0x4630 +#define CHANGE_YUV_ADDR 0x4631 +#define CHANGE_ADDR 0x4632 +#define OVERSCAN 0x4634 + + +enum astfb_color_format { + ASTFB_COLOR_RGB565 = 0, + ASTFB_COLOR_RGB888, + ASTFB_COLOR_YUV444, + ASTFB_COLOR_YUV420, +}; + +struct aspeed_lcd_panel { + struct fb_videomode mode; + signed short width; /* width in mm */ + signed short height; /* height in mm */ +}; + +struct ast_monitor_info { + int status; //0: no data 1:get data + int type; //0:dvi 1:hdmi + struct fb_monspecs specs; + char edid[256]; +}; + +struct ast_fb_plat_data { + u32 (*get_clk)(void); +}; + +int ast_vga_get_info(struct fb_info *fb_info); +int ast_hdmi_get_info(struct fb_info *fb_info); +void ast_hdmi_enable(int en); +int vga_read_edid(void); + diff --git a/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h b/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h new file mode 100644 index 0000000..bbb3878 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_lpc_irqs.h @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-aspeed/include/plat/gpio_irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _LPC_IRQS_H_ +#define _LPC_IRQS_H_ 1 + +#define AST_LPC_IRQ_NUM 7 + +#define IRQ_KCS0 (IRQ_LPC_CHAIN_START + 0) +#define IRQ_KCS1 (IRQ_LPC_CHAIN_START + 1) +#define IRQ_KCS2 (IRQ_LPC_CHAIN_START + 2) +#define IRQ_KCS3 (IRQ_LPC_CHAIN_START + 3) +#define IRQ_KCS4 (IRQ_LPC_CHAIN_START + 4) +#define IRQ_SNOOP0 (IRQ_LPC_CHAIN_START + 5) +#define IRQ_SNOOP1 (IRQ_LPC_CHAIN_START + 6) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h b/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h new file mode 100644 index 0000000..51d4ae3 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_pwm_techo.h @@ -0,0 +1,13 @@ +/*
+ * ast_pwm_techo_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+struct ast_pwm_driver_data {
+ u32 (*get_pwm_clock)(void);
+};
+
diff --git a/arch/arm/mach-aspeed/include/mach/ast_spi.h b/arch/arm/mach-aspeed/include/mach/ast_spi.h new file mode 100644 index 0000000..d612967 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_spi.h @@ -0,0 +1,14 @@ +/*
+ * ast_spi_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+struct ast_spi_driver_data {
+ u32 (*get_div)(u32 max_speed_hz);
+ u16 num_chipselect;
+};
diff --git a/arch/arm/mach-aspeed/include/mach/ast_video.h b/arch/arm/mach-aspeed/include/mach/ast_video.h new file mode 100644 index 0000000..18f9189 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_video.h @@ -0,0 +1,89 @@ + /******************************************************************************** +* File Name : drivers/video/ast_video.h +* Author : Ryan Chen +* Description : ASPEED Video Engine +* +* Copyright (C) ASPEED Tech. Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by the Free Software Foundation; +* either version 2 of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +* History : +* 1. 2012/12/27 Ryan Chen create this file +* +* +********************************************************************************/ +typedef enum ast_video_mode { + VIDEO_SINGLE_MODE = 0, + VIDEO_FRAME_MODE, + VIDEO_STREAM_MODE, +} video_mode; + +//VR08[2] +typedef enum ast_video_source { + VIDEO_SOURCE_UNKNOW = 0, //maybe memory .. TODO ... + VIDEO_SOURCE_INTERNAL, + VIDEO_SOURCE_EXTERNAL, +} video_source; + +//VR08[5] +typedef enum ast_vga_mode { + VIDEO_VGA_DIRECT_MODE = 0, + VIDEO_VGA_CAPTURE_MODE, +} vga_mode; + +//VR08[4] +typedef enum ast_video_dis_en { + VIDEO_EXT_DE_SIGNAL = 0, + VIDEO_INT_DE_SIGNAL, +} display_enable; + +typedef enum video_compress_format { + VIDEO_YUV444 = 0, + VIDEO_YUV420, +} compress_formate; + +typedef enum video_color_format { + VIDEO_COLOR_RGB565 = 0, + VIDEO_COLOR_RGB888, + VIDEO_COLOR_YUV444, + VIDEO_COLOR_YUV420, +} color_formate; + +typedef enum vga_color_mode { + VGA_NO_SIGNAL = 0, + EGA_MODE, + VGA_MODE, + VGA_15BPP_MODE, + VGA_16BPP_MODE, + VGA_32BPP_MODE, +} color_mode; + +typedef enum video_stage { + NONE, + POLARITY, + RESOLUTION, + INIT, + RUN, +} stage; + +struct ast_video_plat_data { + u32 (*get_clk)(void); + void (*ctrl_reset)(void); + void (*vga_display)(u8 enable); + u32 (*get_vga_base)(void); + video_source input_source; + video_mode mode; + u8 rc4_enable; + u8 scaling; + compress_formate compress; +}; + diff --git a/arch/arm/mach-aspeed/include/mach/ast_wdt.h b/arch/arm/mach-aspeed/include/mach/ast_wdt.h new file mode 100644 index 0000000..f9125a1 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ast_wdt.h @@ -0,0 +1,11 @@ +/*
+ * ast_wdt_h
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+ extern void ast_wdt_reset_full(void); diff --git a/arch/arm/mach-aspeed/include/mach/debug-macro.S b/arch/arm/mach-aspeed/include/mach/debug-macro.S new file mode 100644 index 0000000..33fc879 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/debug-macro.S @@ -0,0 +1,21 @@ +/* debug-macro.S + * + * Debugging macro include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ +#include <mach/platform.h> +#include <mach/hardware.h> + + .macro addruart, rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =AST_UART_BASE + ldrne \rx, =IO_ADDRESS(AST_UART_BASE) + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-aspeed/include/mach/dma.h b/arch/arm/mach-aspeed/include/mach/dma.h new file mode 100644 index 0000000..36c141d --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/dma.h @@ -0,0 +1,25 @@ +/* + * dma.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-aspeed/include/mach/entry-macro.S b/arch/arm/mach-aspeed/include/mach/entry-macro.S new file mode 100644 index 0000000..88b4417 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/entry-macro.S @@ -0,0 +1,191 @@ +/* + * entry-macro.S + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/platform.h> +#include <plat/regs-intr.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(AST_VIC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm +#if 1 + +#if defined(NEW_VIC) + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \tmp, =IO_ADDRESS(AST_SCU_BASE) + ldr \irqnr, [\tmp, #0x44] + + cmp \irqnr, #0 + beq 2000f + +1000: /* pass1 */ + cmp \irqnr, #32 + ble 1001f + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x84] + sub \irqnr, \irqnr, #32 + mov \tmp, #32 + sub \tmp, \tmp, \irqnr + mov \irqstat, \irqstat, lsl \tmp /* mask uncompare parts */ + mov \irqstat, \irqstat, lsr \tmp + mov \irqnr, #63 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f + mov \irqnr, #32 +1001: + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x00] + mov \tmp, #32 + sub \tmp, \tmp, \irqnr + mov \irqstat, \irqstat, lsl \tmp /* mask uncompare parts */ + mov \irqstat, \irqstat, lsr \tmp + mov \irqnr, #31 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f + +2000: /* pass 2 */ + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x84] + mov \irqnr, #63 + clz \tmp, \irqstat + cmp \tmp, #32 + bne 3000f +2001: + ldr \tmp, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\tmp, #0x00] + mov \irqnr, #31 + clz \tmp, \irqstat + cmp \tmp, #32 + beq 4000f /* not find */ + +3000: /* find */ + sub \irqnr, \irqnr, \tmp + ldr \tmp, =IO_ADDRESS(AST_SCU_BASE) + str \irqnr, [\tmp, #0x44] + cmp \irqnr, #64 +4000: /* done */ + .endm +#else + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +/* FIXME: should not be using soo many LDRs here */ + ldr \irqnr, =IO_ADDRESS(AST_VIC_BASE) + ldr \irqstat, [\irqnr, #ASPEED_VIC_STATUS_OFFSET] @ get masked status + + mov \irqnr, #0 +1001: tst \irqstat, #1 + bne 1002f + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + cmp \irqnr, #31 + bcc 1001b +1002: /* EQ will be set if we reach 31 */ + .endm + +#endif +#else + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + /*********************************************/ + /* load VIC (VIC1) status value into irqstat */ + /*********************************************/ + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] + + + /**********************************************/ + /* check each status bit and start from bit 0 */ + /**********************************************/ + mov \irqnr, #0 +1000: tst \irqstat, #1 /* Check irqstat[irqnr] is 1 or not. */ + bne 1100f /* If irqstat[irqnr] is 1, service */ + /* this interrupt. */ +1001: + /* check next bit */ + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + + cmp \irqnr, #32 /* If irqnr is number 32, all bits on VIC1 */ + beq 1300f /* have been checked and leave this macro. */ + /* Note that the Zero bit should be 1. */ + + bne 1000b /* continue to check next bit */ + + + +1100: ldr \irqstat, =INT_VIC2IRQ /* interrupt from VIC2? */ + cmp \irqnr, \irqstat + + bne 1300f /* Interupt isn't from VIC2 (i.e. irqnr != INT_VIC2IRQ). */ + /* Leave this macro with irqnr isn't changed and keep Zero */ + /* flag not set */ + + + /***************************************/ + /* load VIC2 status value into irqstat */ + /***************************************/ +#if 0 + ldr \irqnr, =IO_ADDRESS(MVP2_VIC2_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] +#else + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, =0x1000 + add \irqnr, \irqnr, \irqstat + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] +#endif + + /***********************************************/ + /* Check each status bit and start from bit 0. */ + /* Note that bit 0 in VIC2 is IRQ number 32. */ + /***********************************************/ + mov \irqnr, #32 +1200: tst \irqstat, #1 + bne 1300f + + + /* check next bit */ + add \irqnr, \irqnr, #1 + mov \irqstat, \irqstat, lsr #1 + + cmp \irqnr, #64 /* If irqnr isn't reach 64 */ + bne 1200b /* continue check irqstat. */ + + + + /*************************************************************************/ + /* Examine all the other interrupt bits larger than INT_VIC2IRQ on VIC1. */ + /*************************************************************************/ + ldr \irqnr, =IO_ADDRESS(MVP2_VIC_BASE) + ldr \irqstat, [\irqnr, #MVP2_VIC_STATUS_OFFSET] + mov \irqnr, #INT_VIC2IRQ + mov \irqstat, \irqstat, lsr #INT_VIC2IRQ + b 1001b + + /* TODO : if needed */ + /* All interrupt bits on VIC2 have been checked and no bit with value */ + /* 1 is found. Write 1 to EdgeClearReg[INT_VIC2IRQ] to clear interrupt. */ + +1300: + .endm + +#endif + + + + .macro irq_prio_table + .endm + diff --git a/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h b/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h new file mode 100644 index 0000000..40a59e3 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/ftgmac100_drv.h @@ -0,0 +1,18 @@ +/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+/* store this information for the driver.. */
+
+struct ftgmac100_eth_data
+{
+ unsigned char dev_addr[6]; //MAC address
+ unsigned char phy_addr; //Phy Address
+ unsigned char phy_id; //Phy ID
+ unsigned char DF_support; //Defragment support
+ unsigned long NCSI_support;
+ unsigned long INTEL_NCSI_EVA_support;
+};
diff --git a/arch/arm/mach-aspeed/include/mach/gpio.h b/arch/arm/mach-aspeed/include/mach/gpio.h new file mode 100644 index 0000000..9ff3863 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/gpio.h @@ -0,0 +1,352 @@ +/* + * arch/arm/mach-aspeed/include/mach/gpio.h + * + * Support functions for ASPEED GPIO + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Written by Ryan Chen <ryan_chen@aspeedtech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_ASPEED_GPIO_H +#define __ASM_ARCH_ASPEED_GPIO_H + +#include <linux/kernel.h> +#include <mach/irqs.h> +#include <plat/aspeed.h> + +/*************************************************************/ +#define GPIO_PORTA 0x0 +#define GPIO_PORTB 0x1 +#define GPIO_PORTC 0x2 +#define GPIO_PORTD 0x3 +#define GPIO_PORTE 0x4 +#define GPIO_PORTF 0x5 +#define GPIO_PORTG 0x6 +#define GPIO_PORTH 0x7 +#define GPIO_PORTI 0x8 +#define GPIO_PORTJ 0x9 +#define GPIO_PORTK 0xa +#define GPIO_PORTL 0xb +#define GPIO_PORTM 0xc +#define GPIO_PORTN 0xd +#define GPIO_PORTO 0xe +#define GPIO_PORTP 0xf +#define GPIO_PORTQ 0x10 +#define GPIO_PORTR 0x11 +#define GPIO_PORTS 0x12 +//AST2300 didn't have PORT TT +#define GPIO_PORTT 0x13 +#if defined(AST_SOC_G4) || defined(CONFIG_AST2400_BMC) +#define GPIO_PORTU 0x14 +#define GPIO_PORTV 0x15 +#define GPIO_PORTW 0x16 +#define GPIO_PORTX 0x17 +#define GPIO_PORTY 0x18 +#define GPIO_PORTZ 0x19 +#define GPIO_PORTAA 0x1a +#define GPIO_PORTAB 0x1b +#endif + +#define GPIO_PER_PORT_PIN_NUM 8 + +#define GPIO_INPUT_MODE 0 +#define GPIO_OUTPUT_MODE 1 + +#define GPIO_RISING_EDGE 1 +#define GPIO_FALLING_EDGE 0 + +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_LOW 1 + +#define GPIO_EDGE_MODE 0 +#define GPIO_LEVEL_MODE 1 + +#define GPIO_EDGE_LEVEL_MODE 0 +#define GPIO_DUAL_EDGE_MODE 1 + +#define GPIO_NO_DEBOUNCE 0 +#define GPIO_DEBOUNCE_TIMER0 2 //GPIO 50 as debounce timer +#define GPIO_DEBOUNCE_TIMER1 1 //GPIO 54 as debounce timer +#define GPIO_DEBOUNCE_TIMER2 3 //GPIO 58 as debounce timer + +#define GPIO_CMD_ARM 0 +#define GPIO_CMD_LPC 1 +#define GPIO_CMD_COPROCESSOR 2 + +#define PIN_GPIOA0 (0) +#define PIN_GPIOA1 (1) +#define PIN_GPIOA2 (2) +#define PIN_GPIOA3 (3) +#define PIN_GPIOA4 (4) +#define PIN_GPIOA5 (5) +#define PIN_GPIOA6 (6) +#define PIN_GPIOA7 (7) +#define PIN_GPIOB0 (8) +#define PIN_GPIOB1 (9) +#define PIN_GPIOB2 (10) +#define PIN_GPIOB3 (11) +#define PIN_GPIOB4 (12) +#define PIN_GPIOB5 (13) +#define PIN_GPIOB6 (14) +#define PIN_GPIOB7 (15) +#define PIN_GPIOC0 (16) +#define PIN_GPIOC1 (17) +#define PIN_GPIOC2 (18) +#define PIN_GPIOC3 (19) +#define PIN_GPIOC4 (20) +#define PIN_GPIOC5 (21) +#define PIN_GPIOC6 (22) +#define PIN_GPIOC7 (23) +#define PIN_GPIOD0 (24) +#define PIN_GPIOD1 (25) +#define PIN_GPIOD2 (26) +#define PIN_GPIOD3 (27) +#define PIN_GPIOD4 (28) +#define PIN_GPIOD5 (29) +#define PIN_GPIOD6 (30) +#define PIN_GPIOD7 (31) +#define PIN_GPIOE0 (32) +#define PIN_GPIOE1 (33) +#define PIN_GPIOE2 (34) +#define PIN_GPIOE3 (35) +#define PIN_GPIOE4 (36) +#define PIN_GPIOE5 (37) +#define PIN_GPIOE6 (38) +#define PIN_GPIOE7 (39) +#define PIN_GPIOF0 (40) +#define PIN_GPIOF1 (41) +#define PIN_GPIOF2 (42) +#define PIN_GPIOF3 (43) +#define PIN_GPIOF4 (44) +#define PIN_GPIOF5 (45) +#define PIN_GPIOF6 (46) +#define PIN_GPIOF7 (47) +#define PIN_GPIOG0 (48) +#define PIN_GPIOG1 (49) +#define PIN_GPIOG2 (50) +#define PIN_GPIOG3 (51) +#define PIN_GPIOG4 (52) +#define PIN_GPIOG5 (53) +#define PIN_GPIOG6 (54) +#define PIN_GPIOG7 (55) +#define PIN_GPIOH0 (56) +#define PIN_GPIOH1 (57) +#define PIN_GPIOH2 (58) +#define PIN_GPIOH3 (59) +#define PIN_GPIOH4 (60) +#define PIN_GPIOH5 (61) +#define PIN_GPIOH6 (62) +#define PIN_GPIOH7 (63) +#define PIN_GPIOI0 (64) +#define PIN_GPIOI1 (65) +#define PIN_GPIOI2 (66) +#define PIN_GPIOI3 (67) +#define PIN_GPIOI4 (68) +#define PIN_GPIOI5 (69) +#define PIN_GPIOI6 (70) +#define PIN_GPIOI7 (71) +#define PIN_GPIOJ0 (72) +#define PIN_GPIOJ1 (73) +#define PIN_GPIOJ2 (74) +#define PIN_GPIOJ3 (75) +#define PIN_GPIOJ4 (76) +#define PIN_GPIOJ5 (77) +#define PIN_GPIOJ6 (78) +#define PIN_GPIOJ7 (79) +#define PIN_GPIOK0 (80) +#define PIN_GPIOK1 (81) +#define PIN_GPIOK2 (82) +#define PIN_GPIOK3 (83) +#define PIN_GPIOK4 (84) +#define PIN_GPIOK5 (85) +#define PIN_GPIOK6 (86) +#define PIN_GPIOK7 (87) +#define PIN_GPIOL0 (88) +#define PIN_GPIOL1 (89) +#define PIN_GPIOL2 (90) +#define PIN_GPIOL3 (91) +#define PIN_GPIOL4 (92) +#define PIN_GPIOL5 (93) +#define PIN_GPIOL6 (94) +#define PIN_GPIOL7 (95) +#define PIN_GPIOM0 (96) +#define PIN_GPIOM1 (97) +#define PIN_GPIOM2 (98) +#define PIN_GPIOM3 (99) +#define PIN_GPIOM4 (100) +#define PIN_GPIOM5 (101) +#define PIN_GPIOM6 (102) +#define PIN_GPIOM7 (103) +#define PIN_GPION0 (104) +#define PIN_GPION1 (105) +#define PIN_GPION2 (106) +#define PIN_GPION3 (107) +#define PIN_GPION4 (108) +#define PIN_GPION5 (109) +#define PIN_GPION6 (110) +#define PIN_GPION7 (111) +#define PIN_GPIOO0 (112) +#define PIN_GPIOO1 (113) +#define PIN_GPIOO2 (114) +#define PIN_GPIOO3 (115) +#define PIN_GPIOO4 (116) +#define PIN_GPIOO5 (117) +#define PIN_GPIOO6 (118) +#define PIN_GPIOO7 (119) +#define PIN_GPIOP0 (120) +#define PIN_GPIOP1 (121) +#define PIN_GPIOP2 (122) +#define PIN_GPIOP3 (123) +#define PIN_GPIOP4 (124) +#define PIN_GPIOP5 (125) +#define PIN_GPIOP6 (126) +#define PIN_GPIOP7 (127) +#define PIN_GPIOQ0 (128) +#define PIN_GPIOQ1 (129) +#define PIN_GPIOQ2 (130) +#define PIN_GPIOQ3 (131) +#define PIN_GPIOQ4 (132) +#define PIN_GPIOQ5 (133) +#define PIN_GPIOQ6 (134) +#define PIN_GPIOQ7 (135) +#define PIN_GPIOR0 (136) +#define PIN_GPIOR1 (137) +#define PIN_GPIOR2 (138) +#define PIN_GPIOR3 (139) +#define PIN_GPIOR4 (140) +#define PIN_GPIOR5 (141) +#define PIN_GPIOR6 (142) +#define PIN_GPIOR7 (143) +#define PIN_GPIOS0 (144) +#define PIN_GPIOS1 (145) +#define PIN_GPIOS2 (146) +#define PIN_GPIOS3 (147) +#define PIN_GPIOS4 (148) +#define PIN_GPIOS5 (149) +#define PIN_GPIOS6 (150) +#define PIN_GPIOS7 (151) +#if defined(AST_SOC_G4) || defined(CONFIG_AST2400_BMC) +#define PIN_GPIOT0 (152) +#define PIN_GPIOT1 (153) +#define PIN_GPIOT2 (154) +#define PIN_GPIOT3 (155) +#define PIN_GPIOT4 (156) +#define PIN_GPIOT5 (157) +#define PIN_GPIOT6 (158) +#define PIN_GPIOT7 (159) +#define PIN_GPIOU0 (161) +#define PIN_GPIOU1 (162) +#define PIN_GPIOU2 (163) +#define PIN_GPIOU3 (164) +#define PIN_GPIOU4 (165) +#define PIN_GPIOU5 (166) +#define PIN_GPIOU6 (167) +#define PIN_GPIOU7 (168) +#define PIN_GPIOV0 (169) +#define PIN_GPIOV1 (170) +#define PIN_GPIOV2 (171) +#define PIN_GPIOV3 (172) +#define PIN_GPIOV4 (173) +#define PIN_GPIOV5 (174) +#define PIN_GPIOV6 (175) +#define PIN_GPIOV7 (176) +#define PIN_GPIOW0 (177) +#define PIN_GPIOW1 (178) +#define PIN_GPIOW2 (179) +#define PIN_GPIOW3 (181) +#define PIN_GPIOW4 (182) +#define PIN_GPIOW5 (183) +#define PIN_GPIOW6 (184) +#define PIN_GPIOW7 (185) +#define PIN_GPIOX0 (186) +#define PIN_GPIOX1 (187) +#define PIN_GPIOX2 (188) +#define PIN_GPIOX3 (189) +#define PIN_GPIOX4 (190) +#define PIN_GPIOX5 (191) +#define PIN_GPIOX6 (192) +#define PIN_GPIOX7 (193) +#define PIN_GPIOY0 (194) +#define PIN_GPIOY1 (195) +#define PIN_GPIOY2 (196) +#define PIN_GPIOY3 (197) +#define PIN_GPIOY4 (198) +#define PIN_GPIOY5 (199) +#define PIN_GPIOY6 (200) +#define PIN_GPIOY7 (201) +#define PIN_GPIOZ0 (202) +#define PIN_GPIOZ1 (203) +#define PIN_GPIOZ2 (204) +#define PIN_GPIOZ3 (205) +#define PIN_GPIOZ4 (206) +#define PIN_GPIOZ5 (207) +#define PIN_GPIOZ6 (208) +#define PIN_GPIOZ7 (209) +#define PIN_GPIOAA0 (210) +#define PIN_GPIOAA1 (211) +#define PIN_GPIOAA2 (212) +#define PIN_GPIOAA3 (213) +#define PIN_GPIOAA4 (214) +#define PIN_GPIOAA5 (215) +#define PIN_GPIOAA6 (216) +#define PIN_GPIOAA7 (217) +#define PIN_GPIOBB0 (218) +#define PIN_GPIOBB1 (219) +#define PIN_GPIOBB2 (220) +#define PIN_GPIOBB3 (221) +#define PIN_GPIOBB4 (222) +#define PIN_GPIOBB5 (223) +#define PIN_GPIOBB6 (224) +#define PIN_GPIOBB7 (225) +#endif +/*************************************************************/ +#ifndef __ASSEMBLY__ + +/* callable at any time */ +extern int ast_set_gpio_value(unsigned gpio_pin, int value); +extern int ast_get_gpio_value(unsigned gpio_pin); + +/*-------------------------------------------------------------------------*/ + +/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should + * eventually be removed (along with this errno.h inclusion), and the + * gpio request/free calls should probably be implemented. + */ + +//extern int gpio_direction_input(unsigned gpio); +//extern int gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_get_value(unsigned gpio) +{ + return ast_get_gpio_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + ast_set_gpio_value(gpio, value); +} + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#define gpio_to_irq(gpio) (IRQ_GPIO_CHAIN_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_CHAIN_START) + +#endif /* __ASSEMBLY__ */ + + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/hardware.h b/arch/arm/mach-aspeed/include/mach/hardware.h new file mode 100644 index 0000000..be3f23d --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/hardware.h @@ -0,0 +1,51 @@ +/* + * hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <mach/platform.h> + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ + +#define IO_BASE 0xF8000000 // VA of IO +/*#define IO_BASE2 0xE0000000 // VA of IO2 (AST1070) */ + +#ifdef CONFIG_AST_PCIE_EXT +#define ASPEED_IO_START2 AST_PCIE_WIN_BASE +#else +#define ASPEED_IO_START2 AST_LPC_BRIDGE +#endif + +/* macro to get at IO space when running virtually */ +//#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) +/*#define IO_ADDRESS(x) (x - 0x10000000 + IO_BASE) */ +#define IO_ADDRESS(x) (x - 0x1e600000 + IO_BASE) +/*#define IO_ADDRESS2(x) (x - ASPEED_IO_START2 + IO_BASE2) */ + +//PCIE +#ifdef CONFIG_AST_PCIE +#define PCIBIOS_MIN_IO 0x0 +#define PCIBIOS_MIN_MEM 0x0 +#define pcibios_assign_all_busses() 1 +#endif + +#endif /* __ASM_ARCH_HARDWARE_H END */ + diff --git a/arch/arm/mach-aspeed/include/mach/io.h b/arch/arm/mach-aspeed/include/mach/io.h new file mode 100644 index 0000000..baf86d2 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/io.h @@ -0,0 +1,28 @@ +/* + * io.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include <mach/hardware.h> +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) +#endif + diff --git a/arch/arm/mach-aspeed/include/mach/irqs.h b/arch/arm/mach-aspeed/include/mach/irqs.h new file mode 100644 index 0000000..d133251 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/irqs.h @@ -0,0 +1,61 @@ +/* + * arch/arm/plat-aspeed/include/plat/irqs.h + * + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <plat/aspeed.h> + +#if defined(CONFIG_ARCH_AST1010) +#include <mach/ast1010_irqs.h> +#elif defined(CONFIG_ARCH_AST1510) +#include <mach/ast1510_irqs.h> +#elif defined(CONFIG_ARCH_AST1520) +#include <mach/ast1520_irqs.h> +#elif defined(CONFIG_ARCH_AST2000) +#include <mach/ast2000_irqs.h> +#elif defined(CONFIG_ARCH_AST2100) +#include <mach/ast2100_irqs.h> +#elif defined(CONFIG_ARCH_AST2200) +#include <mach/ast2200_irqs.h> +#elif defined(CONFIG_ARCH_AST2300) +#include <mach/ast2300_irqs.h> +#elif defined(CONFIG_ARCH_AST2400) +#include <mach/ast2400_irqs.h> +#elif defined(CONFIG_ARCH_AST2500) +#include <mach/ast2500_irqs.h> +#elif defined(CONFIG_ARCH_AST3100) +#include <mach/ast3100_irqs.h> +#elif defined(CONFIG_ARCH_AST3200) +#include <mach/ast3200_irqs.h> +#else +#err "no define for irqs.h" +#endif + +#include <mach/ast_gpio_irqs.h> +//#include <mach/ast_lpc_irqs.h> + +/*********************************************************************************/ +//CVIC +#if defined(CONFIG_ARCH_AST1070) +//Companion chip irq +#include <mach/ast1070_irqs.h> +#endif + +#if defined(CONFIG_AST2400_BMC) +#include <mach/ext_ast2400_irqs.h> +#endif diff --git a/arch/arm/mach-aspeed/include/mach/memory.h b/arch/arm/mach-aspeed/include/mach/memory.h new file mode 100644 index 0000000..d9927b2 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/memory.h @@ -0,0 +1,48 @@ +/* + * memory.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <mach/platform.h> +#include <plat/aspeed.h> + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#if defined(AST_SOC_G3) || defined(AST_SOC_G4) +#define PHYS_OFFSET UL(0x40000000) +#define BUS_OFFSET UL(0x40000000) +#elif defined(AST_SOC_G5) +#define PHYS_OFFSET UL(0x80000000) +#define BUS_OFFSET UL(0x80000000) +#else +#define PHYS_OFFSET UL(0x40000000) +#define BUS_OFFSET UL(0x40000000) +#endif + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET) +#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET) + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/platform.h b/arch/arm/mach-aspeed/include/mach/platform.h new file mode 100644 index 0000000..afce81b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/platform.h @@ -0,0 +1,89 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _AST_PLATFORM_H_ +#define _AST_PLATFORM_H_ 1 + +#define AST_PLL_25MHZ 25000000 +#define AST_PLL_24MHZ 24000000 +#define AST_PLL_12MHZ 12000000 + +#define AST_IO_START 0x1E600000 +#define AST_IO_SIZE 0x00200000 + +/*********************************************************************************/ +#if defined(CONFIG_ARCH_AST1520) +#include <mach/ast1520_platform.h> +#elif defined(CONFIG_ARCH_AST2000) +#include <mach/ast2000_platform.h> +#elif defined(CONFIG_ARCH_AST2100) +#include <mach/ast2100_platform.h> +#elif defined(CONFIG_ARCH_AST2200) +#include <mach/ast2200_platform.h> +#elif defined(CONFIG_ARCH_AST2300) +#include <mach/ast2300_platform.h> +#elif defined(CONFIG_ARCH_AST2400) +#include <mach/ast2400_platform.h> +#elif defined(CONFIG_ARCH_AST2500) +#include <mach/ast2500_platform.h> +#elif defined(CONFIG_ARCH_AST3200) +#include <mach/ast3200_platform.h> +#else +#err "No define for platform.h" +#endif +/*********************************************************************************/ +/* Companion Base Address */ +#if defined(CONFIG_ARCH_AST1070) +#include <mach/ast1070_platform.h> +#endif +/*********************************************************************************/ +#if defined(CONFIG_ARCH_AST2300) || defined(CONFIG_ARCH_AST2400) +#define AST_CS0_DEF_BASE 0x20000000 /* CS0 */ +#define AST_CS1_DEF_BASE 0x24000000 /* CS1 */ +#define AST_CS2_DEF_BASE 0x26000000 /* CS2 */ +#define AST_CS3_DEF_BASE 0x28000000 /* CS3 */ +#define AST_CS4_DEF_BASE 0x2a000000 /* CS4 */ + +#define AST_NOR_SIZE 0x01000000 /* AST2300 NOR size 16MB */ +#else +#define AST_CS0_DEF_BASE 0x10000000 /* CS0 */ +#define AST_CS1_DEF_BASE 0x12000000 /* CS1 */ +#define AST_CS2_DEF_BASE 0x14000000 /* CS2 */ +#endif + +/* + * Watchdog + */ +#define AST_WDT_VA_BASE (IO_ADDRESS(AST_WDT_BASE)) + +/* + * Console UART + */ +#ifdef CONFIG_WEDGE +#define AST_UART_BASE AST_UART3_BASE +#elif defined(CONFIG_WEDGE100) +#define AST_UART_BASE AST_UART3_BASE +#elif defined(CONFIG_YOSEMITE) +#define AST_UART_BASE AST_UART0_BASE +#elif defined(CONFIG_FBPLATFORM1) +#define AST_UART_BASE AST_UART0_BASE +#elif defined(CONFIG_ASUSPLATFORM) +#define AST_UART_BASE AST_UART1_BASE +#else +#define AST_UART_BASE AST_UART0_BASE +#endif + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/system.h b/arch/arm/mach-aspeed/include/mach/system.h new file mode 100644 index 0000000..926268b --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/system.h @@ -0,0 +1,44 @@ +/* + * system.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <mach/hardware.h> +#include <asm/io.h> +#include <mach/ast_wdt.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Use WDT to restart system + */ +#if defined(CONFIG_AST_WATCHDOG) || defined(CONFIG_AST_WATCHDOG_MODULE) + ast_wdt_reset_full(); +#endif +} + +#endif diff --git a/arch/arm/mach-aspeed/include/mach/time.h b/arch/arm/mach-aspeed/include/mach/time.h new file mode 100644 index 0000000..973a0b0 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/time.h @@ -0,0 +1,73 @@ +/* + * time.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <asm/system.h> +#include <asm/mach/time.h> +#include <asm/param.h> + +/* + * How long is the timer interval? + */ +#define TIMER_INTERVAL (ASPEED_TIMER_CLKRATE / HZ) +#define TIMER_RELOAD (TIMER_INTERVAL) +#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) + +/* + * Timer + */ +#define ASPEED_TIMER0_OFFSET 0x0000 /* Timer0 Offset */ +#define ASPEED_TIMER1_OFFSET 0x0010 /* Timer1 Offset */ +#define ASPEED_TIMER2_OFFSET 0x0020 /* Timer2 Offset */ +#define ASPEED_TIMERRC_OFFSET 0x0030 /* Timer RC Offset */ + +#define ASPEED_TIMER_CLKRATE (ASPEED_EXTCLK) +#define ASPEED_EXTCLK (1*1000*1000) /* 1M */ + +/* + * Ticks + */ +//#define TICKS_PER_uSEC 40 // IP Cam +//#define TICKS_PER_uSEC 24 // FPGA +#define TICKS_PER_uSEC 1 /* ASPEED_EXTCLK / 10 ^ 6 */ + +#define mSEC_1 1000 +#define mSEC_5 (mSEC_1 * 5) +#define mSEC_10 (mSEC_1 * 10) +#define mSEC_25 (mSEC_1 * 25) +#define SEC_1 (mSEC_1 * 1000) + +/* + * Timer Control + */ +#define TIMER0_ENABLE 0x0001 +#define TIMER1_ENABLE 0x0010 +#define TIMER2_ENABLE 0x0100 + +#define TIMER0_RefExt 0x0002 +#define TIMER1_RefExt 0x0020 +#define TIMER2_RefExt 0x0200 + +/* + * What does it look like? + */ +typedef struct TimerStruct { + unsigned long TimerValue; + unsigned long TimerLoad; + unsigned long TimerMatch1; + unsigned long TimerMatch2; +} TimerStruct_t; + diff --git a/arch/arm/mach-aspeed/include/mach/timex.h b/arch/arm/mach-aspeed/include/mach/timex.h new file mode 100644 index 0000000..e907a30 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/timex.h @@ -0,0 +1,21 @@ +/* + * timex.h + * + * Integrator architecture timex specifications + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-aspeed/include/mach/uncompress.h b/arch/arm/mach-aspeed/include/mach/uncompress.h new file mode 100644 index 0000000..3be04b0 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/uncompress.h @@ -0,0 +1,38 @@ +/* + * uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/platform.h> +#include <mach/aspeed_serial.h> + +#define UART_PUT_CHAR (*(volatile unsigned char *)(AST_UART_BASE + UART_THR)) +#define UART_GET_LSR (*(volatile unsigned char *)(AST_UART_BASE + UART_LSR)) + +static void putc(int c) +{ + + /* wait for space in the UART's transmitter */ + while (!(UART_GET_LSR & UART_LSR_THRE)) + barrier(); + + /* send the character out. */ + UART_PUT_CHAR = c; +} + +static inline void flush(void) +{ + while (UART_GET_LSR & (1 << 3)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-aspeed/include/mach/vmalloc.h b/arch/arm/mach-aspeed/include/mach/vmalloc.h new file mode 100644 index 0000000..bc1b471 --- /dev/null +++ b/arch/arm/mach-aspeed/include/mach/vmalloc.h @@ -0,0 +1,29 @@ +/* + * vmalloc.h + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#if 0 +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x20000000) +#else +#define VMALLOC_END 0xf8000000UL +#endif |
