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| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-08-25 13:23:21 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-08-25 13:23:21 -0500 |
| commit | 4d7aca1484d6363636410077635661e58c74969d (patch) | |
| tree | 9490f8ed60cc8fdfb7723162957f3915558134d3 /arch | |
| parent | 30bdf6fabf97b0d46c73093f4f25e933c70c7b5e (diff) | |
| download | ast2050-linux-kernel-4d7aca1484d6363636410077635661e58c74969d.zip ast2050-linux-kernel-4d7aca1484d6363636410077635661e58c74969d.tar.gz | |
Acknowledge LPC reset and related events in the KCS interface module
This resolves an IRQ storm / LPC hang on host boot when the BMC is active
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-aspeed/include/mach/ast_kcs.h | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/arch/arm/mach-aspeed/include/mach/ast_kcs.h b/arch/arm/mach-aspeed/include/mach/ast_kcs.h index 9bcd6fc..2417c25 100644 --- a/arch/arm/mach-aspeed/include/mach/ast_kcs.h +++ b/arch/arm/mach-aspeed/include/mach/ast_kcs.h @@ -96,9 +96,9 @@ #define AST_LPC_HICR0_PMEE 0x04 /* bits of HICR1 */ -#define AST_LPC_HICR1_LPCBSY 0x80 -#define AST_LPC_HICR1_CLKREQ 0x40 -#define AST_LPC_HICR1_IRQBSY 0x20 +#define AST_LPC_HICR1_LPCBSY 0x80 +#define AST_LPC_HICR1_CLKREQ 0x40 +#define AST_LPC_HICR1_IRQBSY 0x20 #define AST_LPC_HICR1_LRSTB 0x10 #define AST_LPC_HICR1_SDWNB 0x08 #define AST_LPC_HICR1_PMEB 0x04 @@ -107,23 +107,23 @@ #define AST_LPC_HICR2_LRST 0x40 #define AST_LPC_HICR2_SDWN 0x20 #define AST_LPC_HICR2_ABRT 0x10 -#define AST_LPC_HICR2_IBFIE3 0x08 -#define AST_LPC_HICR2_IBFIE2 0x04 -#define AST_LPC_HICR2_IBFIE1 0x02 +#define AST_LPC_HICR2_IBFIE3 0x08 +#define AST_LPC_HICR2_IBFIE2 0x04 +#define AST_LPC_HICR2_IBFIE1 0x02 #define AST_LPC_HICR2_ERRIE 0x01 /* bits of HICR3, pin states regsiter */ -#define AST_LPC_HICR3_LFRAME 0x80 -#define AST_LPC_HICR3_CLKRUN 0x40 -#define AST_LPC_HICR3_SERIRQ 0x20 -#define AST_LPC_HICR3_LRESET 0x10 +#define AST_LPC_HICR3_LFRAME 0x80 +#define AST_LPC_HICR3_CLKRUN 0x40 +#define AST_LPC_HICR3_SERIRQ 0x20 +#define AST_LPC_HICR3_LRESET 0x10 #define AST_LPC_HICR3_LPCPD 0x08 #define AST_LPC_HICR3_PME 0x04 /* bits of HICR4, selection register */ -#define AST_LPC_HICR4_LADR12SEL 0x80 -#define AST_LPC_HICR4_KCSENBL 0x04 -#define AST_LPC_HICR4_BTENBL 0x01 +#define AST_LPC_HICR4_LADR12SEL 0x80 +#define AST_LPC_HICR4_KCSENBL 0x04 +#define AST_LPC_HICR4_BTENBL 0x01 /* bits of STR[1:3], data full register */ #define AST_LPC_STR_CD 0x08 @@ -131,6 +131,12 @@ #define AST_LPC_STR_IBFA 0x02 #define AST_LPC_STR_OBFA 0x01 +/* bits of HICR5 */ +#define AST_LPC_HICR5_SNP1_ENINT 0x08 +#define AST_LPC_HICR5_SNP1_EN 0x04 +#define AST_LPC_HICR5_SNP0_ENINT 0x02 +#define AST_LPC_HICR5_SNP0_EN 0x01 + /* bits of HICR6 */ #define AST_LPC_HICR6_SNP1_STR 0x02 #define AST_LPC_HICR6_SNP0_STR 0x01 |
