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author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-08-23 14:45:25 -0500 |
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committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-08-23 14:45:25 -0500 |
commit | fcbb27b0ec6dcbc5a5108cb8fb19eae64593d204 (patch) | |
tree | 22962a4387943edc841c72a4e636a068c66d58fd /arch/mips/kernel/irq-msc01.c | |
download | ast2050-linux-kernel-fcbb27b0ec6dcbc5a5108cb8fb19eae64593d204.zip ast2050-linux-kernel-fcbb27b0ec6dcbc5a5108cb8fb19eae64593d204.tar.gz |
Initial import of modified Linux 2.6.28 tree
Original upstream URL:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git | branch linux-2.6.28.y
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c new file mode 100644 index 0000000..963c16d --- /dev/null +++ b/arch/mips/kernel/irq-msc01.c @@ -0,0 +1,162 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (c) 2004 MIPS Inc + * Author: chris@mips.com + * + * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org> + */ +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/kernel_stat.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/msc01_ic.h> +#include <asm/traps.h> + +static unsigned long _icctrl_msc; +#define MSC01_IC_REG_BASE _icctrl_msc + +#define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) +#define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) + +static unsigned int irq_base; + +/* mask off an interrupt */ +static inline void mask_msc_irq(unsigned int irq) +{ + if (irq < (irq_base + 32)) + MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); + else + MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); +} + +/* unmask an interrupt */ +static inline void unmask_msc_irq(unsigned int irq) +{ + if (irq < (irq_base + 32)) + MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); + else + MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); +} + +/* + * Masks and ACKs an IRQ + */ +static void level_mask_and_ack_msc_irq(unsigned int irq) +{ + mask_msc_irq(irq); + if (!cpu_has_veic) + MSCIC_WRITE(MSC01_IC_EOI, 0); + /* This actually needs to be a call into platform code */ + smtc_im_ack_irq(irq); +} + +/* + * Masks and ACKs an IRQ + */ +static void edge_mask_and_ack_msc_irq(unsigned int irq) +{ + mask_msc_irq(irq); + if (!cpu_has_veic) + MSCIC_WRITE(MSC01_IC_EOI, 0); + else { + u32 r; + MSCIC_READ(MSC01_IC_SUP+irq*8, r); + MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); + MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); + } + smtc_im_ack_irq(irq); +} + +/* + * End IRQ processing + */ +static void end_msc_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_msc_irq(irq); +} + +/* + * Interrupt handler for interrupts coming from SOC-it. + */ +void ll_msc_irq(void) +{ + unsigned int irq; + + /* read the interrupt vector register */ + MSCIC_READ(MSC01_IC_VEC, irq); + if (irq < 64) + do_IRQ(irq + irq_base); + else { + /* Ignore spurious interrupt */ + } +} + +static void msc_bind_eic_interrupt(int irq, int set) +{ + MSCIC_WRITE(MSC01_IC_RAMW, + (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); +} + +static struct irq_chip msc_levelirq_type = { + .name = "SOC-it-Level", + .ack = level_mask_and_ack_msc_irq, + .mask = mask_msc_irq, + .mask_ack = level_mask_and_ack_msc_irq, + .unmask = unmask_msc_irq, + .eoi = unmask_msc_irq, + .end = end_msc_irq, +}; + +static struct irq_chip msc_edgeirq_type = { + .name = "SOC-it-Edge", + .ack = edge_mask_and_ack_msc_irq, + .mask = mask_msc_irq, + .mask_ack = edge_mask_and_ack_msc_irq, + .unmask = unmask_msc_irq, + .eoi = unmask_msc_irq, + .end = end_msc_irq, +}; + + +void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) +{ + _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000); + + /* Reset interrupt controller - initialises all registers to 0 */ + MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); + + board_bind_eic_interrupt = &msc_bind_eic_interrupt; + + for (; nirq >= 0; nirq--, imp++) { + int n = imp->im_irq; + + switch (imp->im_type) { + case MSC01_IRQ_EDGE: + set_irq_chip(irqbase+n, &msc_edgeirq_type); + if (cpu_has_veic) + MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); + else + MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); + break; + case MSC01_IRQ_LEVEL: + set_irq_chip(irqbase+n, &msc_levelirq_type); + if (cpu_has_veic) + MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); + else + MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); + } + } + + irq_base = irqbase; + + MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ + +} |