diff options
| -rw-r--r-- | Makefile | 20 | ||||
| -rw-r--r-- | ast1100.c | 414 | ||||
| -rw-r--r-- | ast2400.c | 182 | ||||
| -rw-r--r-- | flashrom.c | 15 | ||||
| -rw-r--r-- | programmer.h | 16 |
5 files changed, 554 insertions, 93 deletions
@@ -214,6 +214,11 @@ UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes else override CONFIG_GFXNVIDIA = no endif +ifeq ($(CONFIG_AST1100), yes) +UNSUPPORTED_FEATURES += CONFIG_AST1100=yes +else +override CONFIG_AST1100 = no +endif ifeq ($(CONFIG_AST2400), yes) UNSUPPORTED_FEATURES += CONFIG_AST2400=yes else @@ -446,6 +451,11 @@ UNSUPPORTED_FEATURES += CONFIG_GFXNVIDIA=yes else override CONFIG_GFXNVIDIA = no endif +ifeq ($(CONFIG_AST1100), yes) +UNSUPPORTED_FEATURES += CONFIG_AST1100=yes +else +override CONFIG_AST1100 = no +endif ifeq ($(CONFIG_AST2400), yes) UNSUPPORTED_FEATURES += CONFIG_AST2400=yes else @@ -579,6 +589,9 @@ CONFIG_NIC3COM ?= yes # Enable NVIDIA graphics cards. Note: write and erase do not work properly. CONFIG_GFXNVIDIA ?= yes +# Enable AST1100 BMC SoCs. +CONFIG_AST1100 ?= yes + # Enable AST2400 BMC SoCs. CONFIG_AST2400 ?= yes @@ -681,6 +694,7 @@ ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no override CONFIG_NIC3COM = no override CONFIG_GFXNVIDIA = no +override CONFIG_AST1100 = no override CONFIG_AST2400 = no override CONFIG_SATASII = no override CONFIG_ATAHPT = no @@ -794,6 +808,12 @@ PROGRAMMER_OBJS += gfxnvidia.o NEED_LIBPCI += CONFIG_GFXNVIDIA endif +ifeq ($(CONFIG_AST1100), yes) +FEATURE_CFLAGS += -D'CONFIG_AST1100=1' +PROGRAMMER_OBJS += ast1100.o +NEED_LIBPCI += CONFIG_AST1100 +endif + ifeq ($(CONFIG_AST2400), yes) FEATURE_CFLAGS += -D'CONFIG_AST2400=1' PROGRAMMER_OBJS += ast2400.o diff --git a/ast1100.c b/ast1100.c new file mode 100644 index 0000000..56b4e14 --- /dev/null +++ b/ast1100.c @@ -0,0 +1,414 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_ASPEED 0x1a03 + +#define ASPEED_MEMMAP_SIZE (128 * 1024) +#define ASPEED_P2A_OFFSET 0x10000 + +#define AST1100_SCU_APB_ADDR 0x1e6e2000 +#define AST1100_SCU_APB_BRIDGE_OFFSET (AST1100_SCU_APB_ADDR & 0xffff) +#define AST1100_SCU_PROT_KEY 0x00 +#define AST1100_SCU_HW_STRAP 0x70 + +#define AST1100_SCU_PASSWORD 0x1688a8a8 +#define AST1100_SCU_BOOT_SRC_MASK 0x3 +#define AST1100_SCU_BOOT_SPI 0x2 +#define AST1100_SCU_BOOT_NONE 0x3 + +#define AST1100_SMC_APB_ADDR 0x16000000 +#define AST1100_SMC_SMC00 0x00 +#define AST1100_SMC_CE_CTL(N) (0x4 + (N * 4)) + +#define AST1100_SMC_SEGMENT_SIZE_MASK 0x3 +#define AST1100_SMC_SEGMENT_SIZE_32M 0x0 +#define AST1100_SMC_SEGMENT_SIZE_16M 0x1 +#define AST1100_SMC_SEGMENT_SIZE_8M 0x2 +#define AST1100_SMC_SEGMENT_SIZE_4M 0x3 + +#define AST1100_SMC_FLASH_MMIO_ADDR 0x10000000 + +#define AST1100_SPI_CMD_FAST_R_MODE 0x1 +#define AST1100_SPI_CMD_USER_MODE 0x3 +#define AST1100_SPI_CMD_MASK 0x3 +#define AST1100_SPI_STOP_CE_ACTIVE (0x1 << 2) +#define AST1100_SPI_SPEED_SHIFT 8 +#define AST1100_SPI_SPEED_MASK (0x7 << AST1100_SPI_SPEED_SHIFT) + +#define AST1100_SPI_FLASH_MMIO_ADDR 0x30000000 + +#define AST1100_WDT_APB_ADDR 0x1e785000 +#define AST1100_WDT_APB_BRIDGE_OFFSET (AST1100_WDT_APB_ADDR & 0xffff) + +#define AST1100_WDT1_CTR 0x00 +#define AST1100_WDT1_CTR_RELOAD 0x04 +#define AST1100_WDT1_CTL 0x0c + +#define AST1100_WDT_RESET_SYSTEM (0x1 << 1) +#define AST1100_WDT_ENABLE (0x1 << 0) + +uint8_t *ast1100_device_bar = 0; +uint8_t ast1100_device_spi_bus = 0; +uint8_t ast1100_device_spi_speed = 0; +uint8_t ast1100_device_halt_cpu = 0; +uint8_t ast1100_device_reset_cpu = 0; +uint8_t ast1100_device_resume_cpu = 0; +uint8_t ast1100_device_tickle_fw = 0; +uint32_t ast1100_device_flash_mmio_offset = 0; +uint32_t ast1100_original_wdt_conf = 0; + +const struct dev_entry bmc_aspeed_ast1100[] = { + {PCI_VENDOR_ID_ASPEED, 0x2000, OK, "ASPEED", "AST1100" }, + + {0}, +}; + +static int ast1100_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); + +static const struct spi_master spi_master_ast1100 = { + .type = SPI_CONTROLLER_AST1100, + .max_data_read = 256, + .max_data_write = 256, + .command = ast1100_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +static int ast1100_set_a2b_bridge_scu(void) +{ + pci_mmio_writel(0x0, ast1100_device_bar + 0xf000); + pci_mmio_writel(AST1100_SCU_APB_ADDR & 0xffff0000, ast1100_device_bar + 0xf004); + pci_mmio_writel(0x1, ast1100_device_bar + 0xf000); + + return 0; +} + +static int ast1100_set_a2b_bridge_wdt(void) +{ + pci_mmio_writel(0x0, ast1100_device_bar + 0xf000); + pci_mmio_writel(AST1100_WDT_APB_ADDR & 0xffff0000, ast1100_device_bar + 0xf004); + pci_mmio_writel(0x1, ast1100_device_bar + 0xf000); + + return 0; +} + +static int ast1100_set_a2b_bridge_smc(void) +{ + pci_mmio_writel(0x0, ast1100_device_bar + 0xf000); + pci_mmio_writel(AST1100_SMC_APB_ADDR, ast1100_device_bar + 0xf004); + pci_mmio_writel(0x1, ast1100_device_bar + 0xf000); + + return 0; +} + +static int ast1100_set_a2b_bridge_smc_flash(void) +{ + pci_mmio_writel(0x0, ast1100_device_bar + 0xf000); + pci_mmio_writel(AST1100_SMC_FLASH_MMIO_ADDR + ast1100_device_flash_mmio_offset, ast1100_device_bar + 0xf004); + pci_mmio_writel(0x1, ast1100_device_bar + 0xf000); + + return 0; +} + +static int ast1100_disable_cpu(void) { + uint32_t dword; + + if (ast1100_device_halt_cpu) { + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP); + if (((dword & AST1100_SCU_BOOT_SRC_MASK) != AST1100_SCU_BOOT_SPI) + && ((dword & AST1100_SCU_BOOT_SRC_MASK) != AST1100_SCU_BOOT_NONE)) { /* NONE permitted to allow for BMC recovery after Ctrl+C or crash */ + msg_perr("CPU halt requested but CPU firmware source is not SPI.\n"); + pci_mmio_writel(0x0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_PROT_KEY); + ast1100_device_halt_cpu = 0; + return 1; + } + + /* Disable CPU */ + ast1100_set_a2b_bridge_scu(); + pci_mmio_writel((dword & ~AST1100_SCU_BOOT_SRC_MASK) | AST1100_SCU_BOOT_NONE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP); + } + + return 0; +} + +static int ast1100_enable_cpu(void) { + uint32_t dword; + + if (ast1100_device_halt_cpu && ast1100_device_resume_cpu) { + /* Re-enable CPU */ + ast1100_set_a2b_bridge_scu(); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP); + pci_mmio_writel((dword & ~AST1100_SCU_BOOT_SRC_MASK) | AST1100_SCU_BOOT_SPI, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP); + } + + return 0; +} + +static int ast1100_reset_cpu(void) { + if (ast1100_device_reset_cpu) { + /* Disable WDT from issuing full SoC reset + * Without this, OpenPOWER systems will crash when the GPIO blocks are reset on WDT timeout + */ + msg_pinfo("Configuring P2A bridge for WDT access\n"); + ast1100_set_a2b_bridge_wdt(); + ast1100_original_wdt_conf = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL); + + /* Initiate reset */ + msg_pinfo("Setting WDT to reset CPU immediately\n"); + pci_mmio_writel(0x1, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR); + pci_mmio_writel(0xec08ce00, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR_RELOAD); + pci_mmio_writel(AST1100_WDT_RESET_SYSTEM | AST1100_WDT_ENABLE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL); + } + + return 0; +} + +static int ast1100_shutdown(void *data) { + /* Reactivate CPU if previously deactivated */ + ast1100_enable_cpu(); + + /* Reset CPU if requested */ + ast1100_reset_cpu(); + + /* Disable backdoor APB access */ + pci_mmio_writel(0x0, ast1100_device_bar + 0xf000); + + return 0; +} + +int ast1100_init(void) +{ + struct pci_dev *dev = NULL; + uint32_t dword; + + char *arg; + + ast1100_device_spi_bus = 0; + arg = extract_programmer_param("spibus"); + if (arg) + ast1100_device_spi_bus = strtol(arg, NULL, 0); + free(arg); + + ast1100_device_spi_speed = 0; + arg = extract_programmer_param("spispeed"); + if (arg) + ast1100_device_spi_speed = strtol(arg, NULL, 0); + free(arg); + + ast1100_device_halt_cpu = 0; + arg = extract_programmer_param("cpu"); + if (arg && !strcmp(arg,"pause")) { + ast1100_device_halt_cpu = 1; + ast1100_device_resume_cpu = 1; + ast1100_device_reset_cpu = 0; + } + else if (arg && !strcmp(arg,"halt")) { + ast1100_device_halt_cpu = 1; + ast1100_device_resume_cpu = 0; + ast1100_device_reset_cpu = 0; + } + else if (arg && !strcmp(arg,"reset")) { + ast1100_device_halt_cpu = 1; + ast1100_device_resume_cpu = 1; + ast1100_device_reset_cpu = 1; + } + else if (arg) { + msg_perr("Invalid CPU option! Valid values are: pause | halt | reset\n"); + return 1; + } + arg = extract_programmer_param("tickle"); + if (arg && !strcmp(arg,"true")) + ast1100_device_tickle_fw = 1; + free(arg); + + if ((ast1100_device_spi_bus < 0) || (ast1100_device_spi_bus > 2)) { + msg_perr("SPI bus number out of range! Valid values are 0 - 2.\n"); + return 1; + } + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(bmc_aspeed_ast1100, PCI_BASE_ADDRESS_1); + if (!dev) + return 1; + + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_1); + if (!io_base_addr) + return 1; + + msg_pinfo("Detected ASPEED MMIO base address: %p.\n", (void*)io_base_addr); + + ast1100_device_bar = rphysmap("ASPEED", io_base_addr, ASPEED_MEMMAP_SIZE); + if (ast1100_device_bar == ERROR_PTR) + return 1; + + if (register_shutdown(ast1100_shutdown, dev)) + return 1; + + io_base_addr += ASPEED_P2A_OFFSET; + msg_pinfo("ASPEED P2A base address: %p.\n", (void*)io_base_addr); + + msg_pinfo("Configuring P2A bridge for SCU access\n"); + ast1100_set_a2b_bridge_scu(); + pci_mmio_writel(AST1100_SCU_PASSWORD, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_PROT_KEY); + + /* Halt CPU if requested */ + if (ast1100_disable_cpu()) + return 1; + + msg_pinfo("Configuring P2A bridge for SMC access\n"); + ast1100_set_a2b_bridge_smc(); + + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00); + if (((dword >> ((ast1100_device_spi_bus * 2) + 4)) & 0x3) != 0x2) { + msg_perr("CE%01x Flash type is not SPI!\n", ast1100_device_spi_bus); + return 1; + } + + msg_pinfo("Setting CE%01x SPI relative clock speed to %d\n", ast1100_device_spi_bus, ast1100_device_spi_speed); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + dword &= ~AST1100_SPI_SPEED_MASK; + pci_mmio_writel(dword | ((ast1100_device_spi_speed << AST1100_SPI_SPEED_SHIFT) & AST1100_SPI_SPEED_MASK), ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + + msg_pinfo("Enabling CE%01x write\n", ast1100_device_spi_bus); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00); + pci_mmio_writel(dword | (0x1 << (10 + ast1100_device_spi_bus)), ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00); + + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_SMC00); + dword &= AST1100_SMC_SEGMENT_SIZE_MASK; + switch (dword & AST1100_SMC_SEGMENT_SIZE_MASK) { + case AST1100_SMC_SEGMENT_SIZE_32M: + ast1100_device_flash_mmio_offset = 0x2000000; + break; + case AST1100_SMC_SEGMENT_SIZE_16M: + ast1100_device_flash_mmio_offset = 0x1000000; + break; + case AST1100_SMC_SEGMENT_SIZE_8M: + ast1100_device_flash_mmio_offset = 0x800000; + break; + case AST1100_SMC_SEGMENT_SIZE_4M: + ast1100_device_flash_mmio_offset = 0x400000; + break; + default: + ast1100_device_flash_mmio_offset = 0x2000000; + } + msg_pinfo("Segment size: 0x%08x\n", ast1100_device_flash_mmio_offset); + + ast1100_device_flash_mmio_offset = ast1100_device_flash_mmio_offset * ast1100_device_spi_bus; + msg_pinfo("Using CE%01x offset 0x%08x\n", ast1100_device_spi_bus, ast1100_device_flash_mmio_offset); + + register_spi_master(&spi_master_ast1100); + + return 0; +} + +static void ast1100_spi_xfer_data(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int i; + uint32_t dword; + + for (i = 0; i < writecnt; i++) + msg_pspew("[%02x]", writearr[i]); + msg_pspew("\n"); + + for (i = 0; i < writecnt; i=i+4) { + if ((writecnt - i) < 4) + break; + dword = writearr[i]; + dword |= writearr[i + 1] << 8; + dword |= writearr[i + 2] << 16; + dword |= writearr[i + 3] << 24; + pci_mmio_writel(dword, ast1100_device_bar + ASPEED_P2A_OFFSET); + } + for (; i < writecnt; i++) + pci_mmio_writeb(writearr[i], ast1100_device_bar + ASPEED_P2A_OFFSET); + programmer_delay(1); + for (i = 0; i < readcnt;) { + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET); + if (i < readcnt) + readarr[i] = dword & 0xff; + i++; + if (i < readcnt) + readarr[i] = (dword >> 8) & 0xff; + i++; + if (i < readcnt) + readarr[i] = (dword >> 16) & 0xff; + i++; + if (i < readcnt) + readarr[i] = (dword >> 24) & 0xff; + i++; + } + + for (i = 0; i < readcnt; i++) + msg_pspew("[%02x]", readarr[i]); + msg_pspew("\n"); +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int ast1100_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + uint32_t dword; + + msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, *writearr, writecnt, readcnt); + + /* Set up user command mode */ + ast1100_set_a2b_bridge_smc(); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + pci_mmio_writel(dword | AST1100_SPI_CMD_USER_MODE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + pci_mmio_writel(dword & ~AST1100_SPI_STOP_CE_ACTIVE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + + /* Transfer data */ + ast1100_set_a2b_bridge_smc_flash(); + ast1100_spi_xfer_data(flash, writecnt, readcnt, writearr, readarr); + + /* Tear down user command mode */ + ast1100_set_a2b_bridge_smc(); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + pci_mmio_writel(dword | AST1100_SPI_STOP_CE_ACTIVE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + dword = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + pci_mmio_writel((dword & ~AST1100_SPI_CMD_MASK) | AST1100_SPI_CMD_FAST_R_MODE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SMC_CE_CTL(ast1100_device_spi_bus)); + + if (ast1100_device_tickle_fw) { + ast1100_enable_cpu(); + programmer_delay(100); + ast1100_disable_cpu(); + } + + return 0; +} @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2016 Raptor Engineering, LLC + * Copyright (C) 2016 - 2017 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -71,16 +71,16 @@ #define AST2400_WDT_RESET_MODE_MASK (0x3 << 5) #define AST2400_WDT_RESET_CPU_ONLY (0x2 << 5) -uint8_t *aspeed_bar = 0; -uint8_t aspeed_spi_bus = 0; -uint8_t aspeed_halt_cpu = 0; -uint8_t aspeed_resume_cpu = 0; -uint8_t aspeed_tickle_fw = 0; -uint32_t aspeed_flash_mmio_offset = 0; -uint32_t aspeed_host_mode = 0; -uint32_t original_wdt_conf = 0; +uint8_t *ast2400_device_bar = 0; +uint8_t ast2400_device_spi_bus = 0; +uint8_t ast2400_device_halt_cpu = 0; +uint8_t ast2400_device_resume_cpu = 0; +uint8_t ast2400_device_tickle_fw = 0; +uint32_t ast2400_device_flash_mmio_offset = 0; +uint32_t ast2400_device_host_mode = 0; +uint32_t ast2400_original_wdt_conf = 0; -const struct dev_entry bmc_aspeed[] = { +const struct dev_entry bmc_aspeed_ast2400[] = { {PCI_VENDOR_ID_ASPEED, 0x2000, OK, "ASPEED", "AST2400" }, {0}, @@ -104,54 +104,54 @@ static const struct spi_master spi_master_ast2400 = { static int ast2400_set_a2b_bridge_scu(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_SCU_APB_ADDR & 0xffff0000, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_SCU_APB_ADDR & 0xffff0000, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } static int ast2400_set_a2b_bridge_wdt(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_WDT_APB_ADDR & 0xffff0000, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_WDT_APB_ADDR & 0xffff0000, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } static int ast2400_set_a2b_bridge_smc(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_SMC_APB_ADDR, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_SMC_APB_ADDR, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } static int ast2400_set_a2b_bridge_spi(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_SPI_APB_ADDR, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_SPI_APB_ADDR, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } static int ast2400_set_a2b_bridge_smc_flash(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_SMC_FLASH_MMIO_ADDR + aspeed_flash_mmio_offset, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_SMC_FLASH_MMIO_ADDR + ast2400_device_flash_mmio_offset, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } static int ast2400_set_a2b_bridge_spi_flash(void) { - pci_mmio_writel(0x0, aspeed_bar + 0xf000); - pci_mmio_writel(AST2400_SPI_FLASH_MMIO_ADDR, aspeed_bar + 0xf004); - pci_mmio_writel(0x1, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); + pci_mmio_writel(AST2400_SPI_FLASH_MMIO_ADDR, ast2400_device_bar + 0xf004); + pci_mmio_writel(0x1, ast2400_device_bar + 0xf000); return 0; } @@ -159,13 +159,13 @@ static int ast2400_set_a2b_bridge_spi_flash(void) static int ast2400_disable_cpu(void) { uint32_t dword; - if (aspeed_halt_cpu) { - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); + if (ast2400_device_halt_cpu) { + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); if (((dword & AST2400_SCU_BOOT_SRC_MASK) != AST2400_SCU_BOOT_SPI) && ((dword & AST2400_SCU_BOOT_SRC_MASK) != AST2400_SCU_BOOT_NONE)) { /* NONE permitted to allow for BMC recovery after Ctrl+C or crash */ msg_perr("CPU halt requested but CPU firmware source is not SPI.\n"); - pci_mmio_writel(0x0, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY); - aspeed_halt_cpu = 0; + pci_mmio_writel(0x0, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY); + ast2400_device_halt_cpu = 0; return 1; } @@ -174,12 +174,12 @@ static int ast2400_disable_cpu(void) { */ msg_pinfo("Configuring P2A bridge for WDT access\n"); ast2400_set_a2b_bridge_wdt(); - original_wdt_conf = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); - pci_mmio_writel((original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); + ast2400_original_wdt_conf = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); + pci_mmio_writel((ast2400_original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); /* Disable CPU */ ast2400_set_a2b_bridge_scu(); - pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_NONE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); + pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_NONE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); } return 0; @@ -188,15 +188,15 @@ static int ast2400_disable_cpu(void) { static int ast2400_enable_cpu(void) { uint32_t dword; - if (aspeed_halt_cpu && aspeed_resume_cpu) { + if (ast2400_device_halt_cpu && ast2400_device_resume_cpu) { /* Re-enable CPU */ ast2400_set_a2b_bridge_scu(); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); - pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_SPI, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); + pci_mmio_writel((dword & ~AST2400_SCU_BOOT_SRC_MASK) | AST2400_SCU_BOOT_SPI, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_HW_STRAP); /* Reset WDT configuration */ ast2400_set_a2b_bridge_wdt(); - pci_mmio_writel((original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); + pci_mmio_writel((ast2400_original_wdt_conf & ~AST2400_WDT_RESET_MODE_MASK) | AST2400_WDT_RESET_CPU_ONLY, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_WDT_APB_BRIDGE_OFFSET + AST2400_WDT1_CTL); } return 0; @@ -207,7 +207,7 @@ static int ast2400_shutdown(void *data) { ast2400_enable_cpu(); /* Disable backdoor APB access */ - pci_mmio_writel(0x0, aspeed_bar + 0xf000); + pci_mmio_writel(0x0, ast2400_device_bar + 0xf000); return 0; } @@ -220,32 +220,32 @@ int ast2400_init(void) char *arg; - aspeed_spi_bus = 0; + ast2400_device_spi_bus = 0; arg = extract_programmer_param("spibus"); if (arg) { if (!strcmp(arg,"host")) - aspeed_host_mode = 1; + ast2400_device_host_mode = 1; else - aspeed_spi_bus = strtol(arg, NULL, 0); + ast2400_device_spi_bus = strtol(arg, NULL, 0); } free(arg); - aspeed_halt_cpu = 0; + ast2400_device_halt_cpu = 0; arg = extract_programmer_param("cpu"); if (arg && !strcmp(arg,"pause")) { - aspeed_halt_cpu = 1; - aspeed_resume_cpu = 1; + ast2400_device_halt_cpu = 1; + ast2400_device_resume_cpu = 1; } if (arg && !strcmp(arg,"halt")) { - aspeed_halt_cpu = 1; - aspeed_resume_cpu = 0; + ast2400_device_halt_cpu = 1; + ast2400_device_resume_cpu = 0; } arg = extract_programmer_param("tickle"); if (arg && !strcmp(arg,"true")) - aspeed_tickle_fw = 1; + ast2400_device_tickle_fw = 1; free(arg); - if ((aspeed_host_mode == 0) && ((aspeed_spi_bus < 0) || (aspeed_spi_bus > 4))) { + if ((ast2400_device_host_mode == 0) && ((ast2400_device_spi_bus < 0) || (ast2400_device_spi_bus > 4))) { msg_perr("SPI bus number out of range! Valid values are 0 - 4.\n"); return 1; } @@ -253,7 +253,7 @@ int ast2400_init(void) if (rget_io_perms()) return 1; - dev = pcidev_init(bmc_aspeed, PCI_BASE_ADDRESS_1); + dev = pcidev_init(bmc_aspeed_ast2400, PCI_BASE_ADDRESS_1); if (!dev) return 1; @@ -261,24 +261,24 @@ int ast2400_init(void) if (!io_base_addr) return 1; - msg_pinfo("Detected ASPEED MMIO base address: 0x%p.\n", (void*)io_base_addr); + msg_pinfo("Detected ASPEED MMIO base address: %p.\n", (void*)io_base_addr); - aspeed_bar = rphysmap("ASPEED", io_base_addr, ASPEED_MEMMAP_SIZE); - if (aspeed_bar == ERROR_PTR) + ast2400_device_bar = rphysmap("ASPEED", io_base_addr, ASPEED_MEMMAP_SIZE); + if (ast2400_device_bar == ERROR_PTR) return 1; if (register_shutdown(ast2400_shutdown, dev)) return 1; io_base_addr += ASPEED_P2A_OFFSET; - msg_pinfo("ASPEED P2A base address: 0x%p.\n", (void*)io_base_addr); + msg_pinfo("ASPEED P2A base address: %p.\n", (void*)io_base_addr); msg_pinfo("Configuring P2A bridge for SCU access\n"); ast2400_set_a2b_bridge_scu(); - pci_mmio_writel(AST2400_SCU_PASSWORD, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY); + pci_mmio_writel(AST2400_SCU_PASSWORD, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_PROT_KEY); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL); - pci_mmio_writel(dword & ~((0x1 << 24) | (0x2 << 22)), aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL); + pci_mmio_writel(dword & ~((0x1 << 24) | (0x2 << 22)), ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SCU_APB_BRIDGE_OFFSET + AST2400_SCU_MISC_CTL); /* Halt CPU if requested */ if (ast2400_disable_cpu()) @@ -287,34 +287,34 @@ int ast2400_init(void) msg_pinfo("Configuring P2A bridge for SMC access\n"); ast2400_set_a2b_bridge_smc(); - if (aspeed_host_mode) { + if (ast2400_device_host_mode) { msg_pinfo("Configuring P2A bridge for SPI access\n"); ast2400_set_a2b_bridge_spi(); divisor = 0; /* Slowest speed for now */ - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); dword &= ~AST2400_SPI_SPEED_MASK; dword |= (divisor << 8); dword &= ~AST2400_SPI_CPOL_1; dword &= ~AST2400_SPI_LSB_FIRST_CTRL; /* MSB first */ dword &= ~AST2400_SPI_IO_MODE_MASK; /* Single bit I/O mode */ - pci_mmio_writel(dword, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + pci_mmio_writel(dword, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); } else { - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); - if (((dword >> (aspeed_spi_bus * 2)) & 0x3) != 0x2) { - msg_perr("CE%01x Flash type is not SPI!\n", aspeed_spi_bus); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); + if (((dword >> (ast2400_device_spi_bus * 2)) & 0x3) != 0x2) { + msg_perr("CE%01x Flash type is not SPI!\n", ast2400_device_spi_bus); return 1; } - msg_pinfo("Enabling CE%01x write\n", aspeed_spi_bus); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); - pci_mmio_writel(dword | (0x1 << (16 + aspeed_spi_bus)), aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); + msg_pinfo("Enabling CE%01x write\n", ast2400_device_spi_bus); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); + pci_mmio_writel(dword | (0x1 << (16 + ast2400_device_spi_bus)), ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_FMC00); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_SEG(aspeed_spi_bus)); - aspeed_flash_mmio_offset = ((dword >> 16) & 0x3f) * 0x800000; - msg_pinfo("Using CE%01x offset %08x\n", aspeed_spi_bus, aspeed_flash_mmio_offset); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_SEG(ast2400_device_spi_bus)); + ast2400_device_flash_mmio_offset = ((dword >> 16) & 0x3f) * 0x800000; + msg_pinfo("Using CE%01x offset 0x%08x\n", ast2400_device_spi_bus, ast2400_device_flash_mmio_offset); } register_spi_master(&spi_master_ast2400); @@ -341,13 +341,13 @@ static void ast2400_spi_xfer_data(struct flashctx *flash, dword |= writearr[i + 1] << 8; dword |= writearr[i + 2] << 16; dword |= writearr[i + 3] << 24; - pci_mmio_writel(dword, aspeed_bar + ASPEED_P2A_OFFSET); + pci_mmio_writel(dword, ast2400_device_bar + ASPEED_P2A_OFFSET); } for (; i < writecnt; i++) - pci_mmio_writeb(writearr[i], aspeed_bar + ASPEED_P2A_OFFSET); + pci_mmio_writeb(writearr[i], ast2400_device_bar + ASPEED_P2A_OFFSET); programmer_delay(1); for (i = 0; i < readcnt;) { - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET); if (i < readcnt) readarr[i] = dword & 0xff; i++; @@ -377,13 +377,13 @@ static int ast2400_spi_send_command(struct flashctx *flash, msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, *writearr, writecnt, readcnt); - if (aspeed_host_mode) { + if (ast2400_device_host_mode) { /* Set up user command mode */ ast2400_set_a2b_bridge_spi(); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); - pci_mmio_writel(dword | AST2400_SPI_CFG_WRITE_EN, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); - pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); + pci_mmio_writel(dword | AST2400_SPI_CFG_WRITE_EN, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); /* Transfer data */ ast2400_set_a2b_bridge_spi_flash(); @@ -391,18 +391,18 @@ static int ast2400_spi_send_command(struct flashctx *flash, /* Tear down user command mode */ ast2400_set_a2b_bridge_spi(); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); - pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); - pci_mmio_writel(dword & ~AST2400_SPI_CFG_WRITE_EN, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CTL); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); + pci_mmio_writel(dword & ~AST2400_SPI_CFG_WRITE_EN, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SPI_CFG); } else { /* Set up user command mode */ ast2400_set_a2b_bridge_smc(); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - pci_mmio_writel(dword & ~AST2400_SPI_STOP_CE_ACTIVE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + pci_mmio_writel(dword | AST2400_SPI_CMD_USER_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + pci_mmio_writel(dword & ~AST2400_SPI_STOP_CE_ACTIVE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); /* Transfer data */ ast2400_set_a2b_bridge_smc_flash(); @@ -410,13 +410,13 @@ static int ast2400_spi_send_command(struct flashctx *flash, /* Tear down user command mode */ ast2400_set_a2b_bridge_smc(); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - pci_mmio_writel(dword | AST2400_SPI_STOP_CE_ACTIVE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - dword = pci_mmio_readl(aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); - pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, aspeed_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(aspeed_spi_bus)); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + pci_mmio_writel(dword | AST2400_SPI_STOP_CE_ACTIVE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + dword = pci_mmio_readl(ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); + pci_mmio_writel((dword & ~AST2400_SPI_CMD_MASK) | AST2400_SPI_CMD_FAST_R_MODE, ast2400_device_bar + ASPEED_P2A_OFFSET + AST2400_SMC_CE_CTL(ast2400_device_spi_bus)); } - if (aspeed_tickle_fw) { + if (ast2400_device_tickle_fw) { ast2400_enable_cpu(); programmer_delay(100); ast2400_disable_cpu(); @@ -5,6 +5,7 @@ * Copyright (C) 2004 Tyan Corp <yhlu@tyan.com> * Copyright (C) 2005-2008 coresystems GmbH * Copyright (C) 2008,2009 Carl-Daniel Hailfinger + * Copyright (C) 2016-2017 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -134,11 +135,23 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_AST1100 == 1 + { + .name = "ast1100", + .type = PCI, + .devs.dev = bmc_aspeed_ast1100, + .init = ast1100_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_AST2400 == 1 { .name = "ast2400", .type = PCI, - .devs.dev = bmc_aspeed, + .devs.dev = bmc_aspeed_ast2400, .init = ast2400_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, diff --git a/programmer.h b/programmer.h index 25a8506..754f3cc 100644 --- a/programmer.h +++ b/programmer.h @@ -5,6 +5,7 @@ * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2006-2009 Carl-Daniel Hailfinger + * Copyright (C) 2016-2017 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,6 +46,9 @@ enum programmer { #if CONFIG_GFXNVIDIA == 1 PROGRAMMER_GFXNVIDIA, #endif +#if CONFIG_AST1100 == 1 + PROGRAMMER_AST1100, +#endif #if CONFIG_AST2400 == 1 PROGRAMMER_AST2400, #endif @@ -402,10 +406,16 @@ int gfxnvidia_init(void); extern const struct dev_entry gfx_nvidia[]; #endif +/* ast1100.c */ +#if CONFIG_AST1100 == 1 +int ast1100_init(void); +extern const struct dev_entry bmc_aspeed_ast1100[]; +#endif + /* ast2400.c */ #if CONFIG_AST2400 == 1 int ast2400_init(void); -extern const struct dev_entry bmc_aspeed[]; +extern const struct dev_entry bmc_aspeed_ast2400[]; #endif /* drkaiser.c */ @@ -610,6 +620,10 @@ enum spi_controller { SPI_CONTROLLER_CH341A_SPI, #endif +#if CONFIG_AST1100 == 1 + SPI_CONTROLLER_AST1100, +#endif + #if CONFIG_AST2400 == 1 SPI_CONTROLLER_AST2400, #endif |
