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-rw-r--r--cli_classic.c2
-rw-r--r--flashchips.c185
-rw-r--r--flashchips.h2
3 files changed, 185 insertions, 4 deletions
diff --git a/cli_classic.c b/cli_classic.c
index ee988a3..60b8b88 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -94,7 +94,7 @@ int main(int argc, char *argv[])
unsigned long size;
/* Probe for up to three flash chips. */
const struct flashchip *chip = NULL;
- struct flashctx flashes[3] = {{0}};
+ struct flashctx flashes[6] = {{0}};
struct flashctx *fill_flash;
const char *name;
int namelen, opt, i, j;
diff --git a/flashchips.c b/flashchips.c
index a1166e0..a973ddd 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -10389,7 +10389,69 @@ const struct flashchip flashchips[] = {
{
.vendor = "Spansion",
- .name = "S25FL128S......0", /* uniform 256kB sectors */
+ .name = "S25FL128P......0", /* uniform 64 kB sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128,
+ .total_size = 16384,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp3_srwd,
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Spansion",
+ .name = "S25FL128P......1", /* uniform 256kB sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128,
+ .total_size = 16384,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ .eraseblocks = { {256 * 1024, 64} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp2_srwd,
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Spansion",
+ .name = "S25FL128S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */
.bustype = BUS_SPI,
.manufacture_id = SPANSION_ID,
.model_id = SPANSION_S25FL128,
@@ -10403,9 +10465,48 @@ const struct flashchip flashchips[] = {
.probe_timing = TIMING_ZERO,
.block_erasers = {
{
- .eraseblocks = { {4 * 1024, 4096} },
+ /* This chip supports erasing of the 32 so-called "parameter sectors" with
+ * opcode 0x20. Trying to access an address outside these 4kB blocks does
+ * have no effect on the memory contents, but sets a flag in the SR.
+ .eraseblocks = {
+ {4 * 1024, 32},
+ {64 * 1024, 254} // inaccessible
+ },
.block_erase = spi_block_erase_20,
+ }, { */
+ .eraseblocks = { { 64 * 1024, 256} },
+ .block_erase = spi_block_erase_d8,
}, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */
+ .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */
+ .write = spi_chip_write_256, /* Multi I/O supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Spansion",
+ .name = "S25FL128S......1", /* uniform 256 kB sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128,
+ .total_size = 16384,
+ .page_size = 512,
+ /* supports 4B addressing */
+ /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
.eraseblocks = { {256 * 1024, 64} },
.block_erase = spi_block_erase_d8,
}, {
@@ -10424,6 +10525,86 @@ const struct flashchip flashchips[] = {
},
{
+ .vendor = "Spansion",
+ .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128,
+ .total_size = 16384,
+ .page_size = 256,
+ /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_OK_PREW,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ /* FIXME: This chip supports erasing of the 32 so-called "parameter sectors" with
+ * opcode 0x20. Trying to access an address outside these 4kB blocks does have no
+ * effect on the memory contents, but sets a flag in the SR.
+ .eraseblocks = {
+ {4 * 1024, 32},
+ {64 * 1024, 254} // inaccessible
+ },
+ .block_erase = spi_block_erase_20,
+ }, { */
+ /* FIXME: Additionally it also supports erase opcode 40h for the respective 2*4 kB pairs
+ .eraseblocks = {
+ {8 * 1024, 16},
+ {64 * 1024, 254} // inaccessible
+ },
+ .block_erase = spi_block_erase_40,
+ }, { */
+ .eraseblocks = { { 64 * 1024, 256} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256, /* Multi I/O supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Spansion",
+ .name = "S25FL129P......1", /* uniform 256 kB sectors */
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FL128,
+ .total_size = 16384,
+ .page_size = 512,
+ /* OTP: 506B total, 16B reserved; read 0x4B; write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ .eraseblocks = { {256 * 1024, 64} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { { 16384 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: Configuration register */
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256, /* Multi I/O supported */
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
.vendor = "SST",
.name = "SST25LF020A",
.bustype = BUS_SPI,
diff --git a/flashchips.h b/flashchips.h
index 029bae8..b2c1d4d 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -590,7 +590,7 @@
#define SPANSION_S25FL016A 0x0214
#define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */
#define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */
-#define SPANSION_S25FL128 0x2018
+#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */
#define SPANSION_S25FL256 0x0219
#define SPANSION_S25FL512 0x0220
#define SPANSION_S25FL204 0x4013
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