path: root/chipset_enable.c
diff options
authorStefan Tauner <>2012-09-21 12:52:50 +0000
committerStefan Tauner <>2012-09-21 12:52:50 +0000
commiteb58257b9650b9191d8b987e0b214fed1ad2b77a (patch)
tree8e37e169514dfba6083cc6f8c18943e69b81e9a4 /chipset_enable.c
parent3c0fcd0f30f2b3c0df57b66e645859d923e68d16 (diff)
Add a bunch of new/tested stuff and various small changes 14
Tested Mainboards: OK: - ASUS M3A78-EH - ASUS P2B-LS - Biostar TA790GX A3+ - ECS 848P-A7 - GIGABYTE GA-G41MT-S2PT Reported on IRC - GIGABYTE GA-H77-D3H Reported and tested by Alexander Gordeev on IRC. - Gigabyte GA-X79-UD5 - Shuttle FN78S - VIA EITX-3000 Reported on IRC by Tuju NOT OK: - Dell PowerEdge C6220 (0HYFFG) - Foxconn Q45M - MSI MS-7309 (K9N6SGM-V) - Supermicro X9QRi-F+ - ZOTAC H61-ITX WiFi (H61ITX-A-E) ASUS CUSL2-C has been tested to be working with the board enable once implemented for the TUSL2-C board. They seem to have the same PCI IDs as shown in the links below. Since only the CUSL2-C board enable has been tested yet, we distinguish the two by DMI strings. Tested flash chips: - Set EMST F25L008A to PREW (+PREW) - Set GigaDevice GD25Q64 to PREW (+PREW);a=commit;h=9e8ef49b1f626c2197e131fba6c5b65c8af4eeea - Set Macronix MX25L12805 to P (+P) - Set SST SST49LF003A/B to PREW (+EW) - Set Winbond W49V002FA to PREW (+EW) Tested chipsets: - Intel X79 (0x1d41) Board enables: - add ASUS P4P800-X Created by Idwer Vollering and tested by Mingsen Bao: - add DMI string to P4P800-VM Miscellaneous: - Add remaining Intel 7 series chipset (LPC) PCI IDs - Add generic SPI detection for chips from Winbond - Minor manpage changes - Minor other cleanups - Escape full stops after abbreviations in the manpage. - Add ICH9 and successors to spi_get_valid_read_addr Corresponding to flashrom svn r1601. Signed-off-by: Stefan Tauner <> Acked-by: Stefan Tauner <>
Diffstat (limited to 'chipset_enable.c')
1 files changed, 6 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index e1684f9..0873b4e 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1405,17 +1405,22 @@ const struct penable chipset_enables[] = {
{0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
{0x8086, 0x1c5c, OK, "Intel", "H61", enable_flash_pch6},
{0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_pch6},
- {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_pch6},
+ {0x8086, 0x1d41, OK, "Intel", "X79", enable_flash_pch6},
{0x8086, 0x1e44, NT, "Intel", "Z77", enable_flash_pch7},
{0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
+ {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7},
+ {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7},
{0x8086, 0x1e49, NT, "Intel", "B75", enable_flash_pch7},
{0x8086, 0x1e4a, NT, "Intel", "H77", enable_flash_pch7},
+ {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7},
{0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7},
+ {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7},
{0x8086, 0x1e57, NT, "Intel", "HM77", enable_flash_pch7},
{0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
{0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},
{0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7},
{0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7},
+ {0x8086, 0x1e5f, NT, "Intel", "NM70", enable_flash_pch7},
{0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7},
{0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
{0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
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