path: root/chipset_enable.c
diff options
authorUwe Hermann <>2010-08-08 17:01:18 +0000
committerUwe Hermann <>2010-08-08 17:01:18 +0000
commit48ec1b17d855ba0589487f6a5d5c6c0c61ed0b79 (patch)
tree2a69d7e58effcb8eaeea3240d80df42806c88d3a /chipset_enable.c
parent7507de451be109386668332e64ea1febe213d190 (diff)
Various cosmetic and coding-style fixes
- Fix incorrect whitespace, indentation, and coding style in some places. - Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use it, the comments are useless as we don't have any Doxygen markup in there. - Use consistent vendor name spelling as per current website (NVIDIA, abit, GIGABYTE). - Use consistent / common format for "Suited for:" lines in board_enable.c. - Add some missing 'void's in functions taking no arguments. - Add missing fullstops in sentences, remove them from non-sentences (lists). Corresponding to flashrom svn r1134. Signed-off-by: Uwe Hermann <> Acked-by: Uwe Hermann <>
Diffstat (limited to 'chipset_enable.c')
1 files changed, 3 insertions, 3 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 11f866b..05d8e09 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -609,7 +609,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
return 0;
* Geode systems write protect the BIOS via RCONFs (cache settings similar
* to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
@@ -868,7 +868,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
return 0;
* The MCP6x/MCP7x code is based on cleanroom reverse engineering.
* It is assumed that LPC chips need the MCP55 code and SPI chips need the
* code provided in enable_flash_mcp6x_7x_common.
@@ -945,7 +945,7 @@ static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
return 0;
* Usually on the x86 architectures (and on other PC-like platforms like some
* Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
* Elan SC520 only a small piece of the system flash is mapped there, but the
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