path: root/Documentation
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authorStefan Tauner <>2012-07-28 03:17:15 +0000
committerStefan Tauner <>2012-07-28 03:17:15 +0000
commitd94d25d75be771eec26578355dc5c70cfb3e9c73 (patch)
treed2cb1083a5fa9dd1274213c17bc4ede903913d3d /Documentation
parenta0fce5f459871840166348de1451fd8cd8bb9cb8 (diff)
Add a bunch of new/tested stuff and various small changes 13
Tested Mainboards: OK: - ASRock A780FullHD - ASRock 880G Pro3 - ASRock N61P-S - ASUS M2N68-VM - ASUS M3N78 PRO - ASUS M4N68T V2 - ASUS M5A78L-M LX reported by clavile on IRC - ASUS P8P67 PRO (rev. 3.0) - ASUS P8Z68-V reported by Kano on IRC - ASUS SABERTOOTH 990FX - Dell Inspiron 1420 - ECS GF8200A - GIGABYTE GA-H61M-D2H-USB3 - MSI MS-7250 (K9N SLI (rev 2.1)) - MSI MS-7676 (Z68MA-G45 (B3)) - Palit N61S NOT OK: - ASRock H61M-ITX - Dell Latitude E6520 - Dell Vostro 3700 - Intel DH61AG - Intel DQ965GF - HP/Compaq 8100 Elite CMT PC (304Bh) - HP Z400 Workstation (0AE4h) - Supermicro X9DR3-F Tested flash chips: - mark AMIC A25L032 as TEST_OK_PREW (+PREW) - mark Atmel AT25DF321A as TEST_OK_PREW (+REW) - mark Atmel AT26DF161 as TEST_OK_PR (+PR) - mark Eon EN25QH16 as TEST_OK_PR (+PR) - mark SST SST39VF010 as TEST_OK_PREW (+W) - mark ST M25P64 as TEST_OK_PREW (+PREW) Tested chipset enables: - Intel 3420 - Add board enable for ASUS P5GD2-X lspci: write: Miscellaneous - Reorder some boards in print.c. - Remove broken abit URLs. - Whitespace changes. - Fix the maximum number of southbridge straps in the ICH descriptor structs. - Refine documentation regarding ICH region lock bits. - Demote verbosity of ICH Opcode reprogramming to -VV. - Exclude Pony-SPI for DOS targets (missing serial support). Corresponding to flashrom svn r1554. Signed-off-by: Stefan Tauner <> Acked-by: Stefan Tauner <>
Diffstat (limited to 'Documentation')
1 files changed, 16 insertions, 3 deletions
diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt
index 55921cf..10cb37d 100644
--- a/Documentation/mysteries_intel.txt
+++ b/Documentation/mysteries_intel.txt
@@ -14,10 +14,18 @@
when trying to touch an address outside of any region.
See also
-= Unlocking the ME region =
+= (Un)locking the ME region =
If the ME region is locked by the FRAP register in descriptor mode, the host
- software is not allowed to read or write any address inside that region. There
- are different ways to unlock access:
+ software is not allowed to read or write any address inside that region.
+ Although the chipset datasheets specify that "[t]he contents of this register
+ are that of the Flash Descriptor" [PANTHER], this is not entirely true.
+ The firmware has to fill at least some of the registers involved. It is not
+ known when they become read-only or any other details, but there is at least
+ one HM67-based board, that provides an user-changeable setting in the firmware
+ user interface to enable ME region updates that lead to a FRAP content that is
+ not equal to the descriptor region bits [NC9B].
+ There are different ways to unlock access:
- A pin strap: Flash Descriptor Security Override Strap (as indicated by the
Flash Descriptor Override Pin Strap Status (FDOPSS) in HSFS. That pin is
@@ -81,6 +89,11 @@
vendor tools use it for updates. This needs to be investigated further before
drawing any conclusion.
+[PANTHER] Intel 7 Series Chipset Family Platform Controller Hub (PCH) Datasheet
+ Document Number: 326776, April 2012, page 857
+[NC9B] Jetway NC9B flashrom v0.9.5.2-r1517 log with ME region unlocked.
+ NB: "FRAP 0e0f" vs. "FLMSTR1 0a0b".
[MODE_CTRL] Client Platform Enabling Tour: Platform Software
Document Number: 439167, Revision 1.2, page 52
[MEBX] Intel Management Engine BIOS Extension (MEBX) User's Guide
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