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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2017-11-17 12:54:40 -0600
committerGitHub <noreply@github.com>2017-11-17 12:54:40 -0600
commitca651b75d78a26e959a8ec5e21c5cee2590c75e5 (patch)
tree37ee53a45a9cd26e9f201ae86c54497035be7658
parentcfb9cbdcf413e8bca58a895c224d2b15cd888f71 (diff)
parent5997c1635e38f31990a2eec95b9476f4bf38095a (diff)
downloadast2050-flashrom-ca651b75d78a26e959a8ec5e21c5cee2590c75e5.zip
ast2050-flashrom-ca651b75d78a26e959a8ec5e21c5cee2590c75e5.tar.gz
Merge pull request #2 from pkubaj/patch-1
Properly disable WDT
-rw-r--r--ast1100.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/ast1100.c b/ast1100.c
index 56b4e14..f661271 100644
--- a/ast1100.c
+++ b/ast1100.c
@@ -65,8 +65,10 @@
#define AST1100_WDT1_CTR 0x00
#define AST1100_WDT1_CTR_RELOAD 0x04
+#define AST1100_WDT1_CTR_RESTART 0x08
#define AST1100_WDT1_CTL 0x0c
+#define AST1100_WDT_SET_CLOCK (0x1 << 4)
#define AST1100_WDT_RESET_SYSTEM (0x1 << 1)
#define AST1100_WDT_ENABLE (0x1 << 0)
@@ -154,6 +156,8 @@ static int ast1100_disable_cpu(void) {
/* Disable CPU */
ast1100_set_a2b_bridge_scu();
pci_mmio_writel((dword & ~AST1100_SCU_BOOT_SRC_MASK) | AST1100_SCU_BOOT_NONE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_SCU_APB_BRIDGE_OFFSET + AST1100_SCU_HW_STRAP);
+ ast1100_original_wdt_conf = pci_mmio_readl(ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
+ pci_mmio_writel(ast1100_original_wdt_conf & 0xffff0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
}
return 0;
@@ -183,9 +187,12 @@ static int ast1100_reset_cpu(void) {
/* Initiate reset */
msg_pinfo("Setting WDT to reset CPU immediately\n");
- pci_mmio_writel(0x1, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR);
+ pci_mmio_writel(ast1100_original_wdt_conf & 0xffff0, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
pci_mmio_writel(0xec08ce00, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR_RELOAD);
+ pci_mmio_writel(0x4755, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTR_RESTART);
+ pci_mmio_writel(AST1100_WDT_SET_CLOCK, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
pci_mmio_writel(AST1100_WDT_RESET_SYSTEM | AST1100_WDT_ENABLE, ast1100_device_bar + ASPEED_P2A_OFFSET + AST1100_WDT_APB_BRIDGE_OFFSET + AST1100_WDT1_CTL);
+
}
return 0;
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