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| author | Stefan Reinauer <stepan@coresystems.de> | 2007-06-05 10:28:39 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2007-06-05 10:28:39 +0000 |
| commit | c868b9e68b735dc1ab0d075e4ff25065241860c5 (patch) | |
| tree | 18f66566101d1124744258035108f2e08377044c | |
| parent | a88088530e9ed523fef897a8a8dfeb4d4e431318 (diff) | |
| download | ast2050-flashrom-c868b9e68b735dc1ab0d075e4ff25065241860c5.zip ast2050-flashrom-c868b9e68b735dc1ab0d075e4ff25065241860c5.tar.gz | |
Add support for BCM HT1000 chipset
Tested on IBM x3455.
Corresponding to flashrom svn r117 and coreboot v2 svn r2711.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
| -rw-r--r-- | chipset_enable.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index bef55b1..b663295 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -387,6 +387,28 @@ static int enable_flash_mcp55(struct pci_dev *dev, char *name) } + +static int enable_flash_ht1000(struct pci_dev *dev, char *name) +{ + unsigned char byte; + + /* Set the 4MB enable bit */ + byte = pci_read_byte(dev, 0x41); + byte |= 0x0e; + pci_write_byte(dev, 0x41, byte); + + byte = pci_read_byte(dev, 0x43); + byte |= (1<<4); + pci_write_byte(dev, 0x43, byte); + + /* Some magic. Comment me if you can */ + outb(0x45, 0xcd6); + byte = inb(0xcd7); + outb(reg8|0x20, 0xcd7); + + return 0; +} + typedef struct penable { unsigned short vendor, device; char *name; @@ -444,6 +466,8 @@ static FLASH_ENABLE enables[] = { {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ + + {0x1166, 0x0205, "BCM HT1000", enable_flash_ht1000}, }; /* |
