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author | Peter Stuge <peter@stuge.se> | 2008-06-29 01:30:41 +0000 |
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committer | Peter Stuge <peter@stuge.se> | 2008-06-29 01:30:41 +0000 |
commit | 7e2c079367fb2b9eb298b51a102ab40a70e79332 (patch) | |
tree | f7110ea3a195ce2a65ec88944798b3ae6ed6a882 | |
parent | a0a791963b963b96b8017f52c8956878ea0e3f16 (diff) | |
download | ast2050-flashrom-7e2c079367fb2b9eb298b51a102ab40a70e79332.zip ast2050-flashrom-7e2c079367fb2b9eb298b51a102ab40a70e79332.tar.gz |
Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.
Also fixes a build error in ichspi.c with gcc 4.2.2.
Corresponding to flashrom svn r280 and coreboot v2 svn r3395.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
-rw-r--r-- | chipset_enable.c | 2 | ||||
-rw-r--r-- | ichspi.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index d1ab964..dc6d8bc 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -212,6 +212,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); + if (bbs >= 2) + ich7_detected = 0; buc = *(volatile uint8_t *)(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled"); @@ -229,7 +229,7 @@ static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32; + uint32_t temp32 = 0; uint16_t temp16; uint32_t a; |