1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
|
/*-
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: sio.c,v 1.95 1999/05/10 09:37:37 kato Exp $
* from: @(#)com.c 7.5 (Berkeley) 5/16/91
* from: i386/isa sio.c,v 1.234
*/
#include "opt_comconsole.h"
#include "opt_compat.h"
#include "opt_ddb.h"
#include "opt_devfs.h"
#include "opt_sio.h"
#include "sio.h"
/* #include "pnp.h" */
#define NPNP 0
/*
* Serial driver, based on 386BSD-0.1 com driver.
* Mostly rewritten to use pseudo-DMA.
* Works for National Semiconductor NS8250-NS16550AF UARTs.
* COM driver, based on HP dca driver.
*
* Changes for PC-Card integration:
* - Added PC-Card driver table and handlers
*/
/*===============================================================
* 386BSD(98),FreeBSD-1.1x(98) com driver.
* -----
* modified for PC9801 by M.Ishii
* Kyoto University Microcomputer Club (KMC)
* Chou "TEFUTEFU" Hirotomi
* Kyoto Univ. the faculty of medicine
*===============================================================
* FreeBSD-2.0.1(98) sio driver.
* -----
* modified for pc98 Internal i8251 and MICRO CORE MC16550II
* T.Koike(hfc01340@niftyserve.or.jp)
* implement kernel device configuration
* aizu@orient.center.nitech.ac.jp
*
* Notes.
* -----
* PC98 localization based on 386BSD(98) com driver. Using its PC98 local
* functions.
* This driver is under debugging,has bugs.
*
* 1) config
* options COM_MULTIPORT #if using MC16550II
* device sio0 at nec? port 0x30 tty irq 4 #internal
* device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
* device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
* # ~~~~~iobase ~~multi port flag
* # ~ master device is sio1
* 2) device
* cd /dev; MAKEDEV ttyd0 ttyd1 ..
* 3) /etc/rc.serial
* 57600bps is too fast for sio0(internal8251)
* my ex.
* #set default speed 9600
* modem()
* :
* stty </dev/ttyid$i crtscts 9600
* : # ~~~~ default speed(can change after init.)
* modem 0 1 2
* 4) COMCONSOLE
* not changed.
* 5) PC9861K,PIO9032B,B98_01
* not tested.
*/
/*
* modified for AIWA B98-01
* by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
*
* How to configure...
* # options COM_MULTIPORT # support for MICROCORE MC16550II
* ... comment-out this line, which will conflict with B98_01.
* options "B98_01" # support for AIWA B98-01
* device sio1 at nec? port 0x00d1 tty irq ?
* device sio2 at nec? port 0x00d5 tty irq ?
* ... you can leave these lines `irq ?', irq will be autodetected.
*/
/*
* Modified by Y.Takahashi of Kogakuin University.
*/
#ifdef PC98
#define COM_IF_INTERNAL 0x00
#define COM_IF_PC9861K_1 0x01
#define COM_IF_PC9861K_2 0x02
#define COM_IF_IND_SS_1 0x03
#define COM_IF_IND_SS_2 0x04
#define COM_IF_PIO9032B_1 0x05
#define COM_IF_PIO9032B_2 0x06
#define COM_IF_B98_01_1 0x07
#define COM_IF_B98_01_2 0x08
#define COM_IF_END1 COM_IF_B98_01_2
#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
#define COM_IF_NS16550 0x11
#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
#define COM_IF_MC16550II 0x13
#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
#define COM_IF_RSB3000 0x15
#define COM_IF_RSB384 0x16
#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
#define COM_IF_RSA98III 0x18
#define COM_IF_ESP98 0x19
#define COM_IF_END2 COM_IF_ESP98
#endif /* PC98 */
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/reboot.h>
#include <sys/malloc.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/module.h>
#include <sys/conf.h>
#include <sys/dkstat.h>
#include <sys/fcntl.h>
#include <sys/interrupt.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/sysctl.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#ifdef DEVFS
#include <sys/devfsext.h>
#endif
#include <sys/timepps.h>
#ifdef PC98
#include <pc98/pc98/pc98.h>
#include <pc98/pc98/pc98_machdep.h>
#include <i386/isa/ic/i8251.h>
#else
#include <isa/isareg.h>
#endif
#include <isa/isavar.h>
#include <machine/lock.h>
#include <machine/clock.h>
#include <machine/ipl.h>
#ifndef SMP
#include <machine/lock.h>
#endif
#include <machine/resource.h>
#include <isa/sioreg.h>
#ifdef COM_ESP
#include <i386/isa/ic/esp.h>
#endif
#include <i386/isa/ic/ns16550.h>
#ifdef PC98
#include <i386/isa/ic/rsa.h>
#endif
#if 0
#include "card.h"
#if NCARD > 0
#include <sys/module.h>
#include <pccard/cardinfo.h>
#include <pccard/slot.h>
#endif
#if NPNP > 0
#include <i386/isa/pnp.h>
#endif
#endif
#ifndef __i386__
#define disable_intr() 0
#define enable_intr() 0
#endif
#ifdef SMP
#define disable_intr() COM_DISABLE_INTR()
#define enable_intr() COM_ENABLE_INTR()
#endif /* SMP */
#ifndef EXTRA_SIO
#if NPNP > 0
#define EXTRA_SIO MAX_PNP_CARDS
#else
#define EXTRA_SIO 0
#endif
#endif
#define NSIOTOT (NSIO + EXTRA_SIO)
#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
#define CALLOUT_MASK 0x80
#define CONTROL_MASK 0x60
#define CONTROL_INIT_STATE 0x20
#define CONTROL_LOCK_STATE 0x40
#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
#ifdef COM_MULTIPORT
/* checks in flags for multiport and which is multiport "master chip"
* for a given card
*/
#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
#define COM_NOTAST4(flags) ((flags) & 0x04)
#endif /* COM_MULTIPORT */
#define COM_CONSOLE(flags) ((flags) & 0x10)
#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
#define COM_LLCONSOLE(flags) ((flags) & 0x40)
#define COM_DEBUGGER(flags) ((flags) & 0x80)
#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
#define COM_NOFIFO(flags) ((flags) & 0x02)
#define COM_ST16650A(flags) ((flags) & 0x20000)
#define COM_C_NOPROBE (0x40000)
#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
#define COM_C_IIR_TXRDYBUG (0x80000)
#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
#ifdef PC98
#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
#else
#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
#endif
/*
* com state bits.
* (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
* than the other bits so that they can be tested as a group without masking
* off the low bits.
*
* The following com and tty flags correspond closely:
* CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
* siostop())
* CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
* CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
* CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
* TS_FLUSH is not used.
* XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
* XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
*/
#define CS_BUSY 0x80 /* output in progress */
#define CS_TTGO 0x40 /* output not stopped by XOFF */
#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
#define CS_CHECKMSR 1 /* check of MSR scheduled */
#define CS_CTS_OFLOW 2 /* use CTS output flow control */
#define CS_DTR_OFF 0x10 /* DTR held off */
#define CS_ODONE 4 /* output completed */
#define CS_RTS_IFLOW 8 /* use RTS input flow control */
#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
static char const * const error_desc[] = {
#define CE_OVERRUN 0
"silo overflow",
#define CE_INTERRUPT_BUF_OVERFLOW 1
"interrupt-level buffer overflow",
#define CE_TTY_BUF_OVERFLOW 2
"tty-level buffer overflow",
};
#define CE_NTYPES 3
#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
/* types. XXX - should be elsewhere */
typedef u_int Port_t; /* hardware port */
typedef u_char bool_t; /* boolean */
/* queue of linear buffers */
struct lbq {
u_char *l_head; /* next char to process */
u_char *l_tail; /* one past the last char to process */
struct lbq *l_next; /* next in queue */
bool_t l_queued; /* nonzero if queued */
};
/* com device structure */
struct com_s {
u_int flags; /* Copy isa device flags */
u_char state; /* miscellaneous flag bits */
bool_t active_out; /* nonzero if the callout device is open */
u_char cfcr_image; /* copy of value written to CFCR */
#ifdef COM_ESP
bool_t esp; /* is this unit a hayes esp board? */
#endif
u_char extra_state; /* more flag bits, separate for order trick */
u_char fifo_image; /* copy of value written to FIFO */
bool_t hasfifo; /* nonzero for 16550 UARTs */
bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
bool_t loses_outints; /* nonzero if device loses output interrupts */
u_char mcr_image; /* copy of value written to MCR */
#ifdef COM_MULTIPORT
bool_t multiport; /* is this unit part of a multiport device? */
#endif /* COM_MULTIPORT */
bool_t no_irq; /* nonzero if irq is not attached */
bool_t gone; /* hardware disappeared */
bool_t poll; /* nonzero if polling is required */
bool_t poll_output; /* nonzero if polling for output is required */
int unit; /* unit number */
int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
u_int tx_fifo_size;
u_int wopeners; /* # processes waiting for DCD in open() */
/*
* The high level of the driver never reads status registers directly
* because there would be too many side effects to handle conveniently.
* Instead, it reads copies of the registers stored here by the
* interrupt handler.
*/
u_char last_modem_status; /* last MSR read by intr handler */
u_char prev_modem_status; /* last MSR handled by high level */
u_char hotchar; /* ldisc-specific char to be handled ASAP */
u_char *ibuf; /* start of input buffer */
u_char *ibufend; /* end of input buffer */
u_char *ibufold; /* old input buffer, to be freed */
u_char *ihighwater; /* threshold in input buffer */
u_char *iptr; /* next free spot in input buffer */
int ibufsize; /* size of ibuf (not include error bytes) */
int ierroff; /* offset of error bytes in ibuf */
struct lbq obufq; /* head of queue of output buffers */
struct lbq obufs[2]; /* output buffers */
#ifdef PC98
Port_t cmd_port;
Port_t sts_port;
Port_t in_modem_port;
Port_t intr_ctrl_port;
int intr_enable;
int pc98_prev_modem_status;
int pc98_modem_delta;
int modem_car_chg_timer;
int pc98_prev_siocmd;
int pc98_prev_siomod;
int modem_checking;
int pc98_if_type;
#endif /* PC98 */
Port_t data_port; /* i/o ports */
#ifdef COM_ESP
Port_t esp_port;
#endif
Port_t int_id_port;
Port_t iobase;
#ifdef PC98
Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
#endif
Port_t modem_ctl_port;
Port_t line_status_port;
Port_t modem_status_port;
Port_t intr_ctl_port; /* Ports of IIR register */
struct tty *tp; /* cross reference */
/* Initial state. */
struct termios it_in; /* should be in struct tty */
struct termios it_out;
/* Lock state. */
struct termios lt_in; /* should be in struct tty */
struct termios lt_out;
bool_t do_timestamp;
bool_t do_dcd_timestamp;
struct timeval timestamp;
struct timeval dcd_timestamp;
struct pps_state pps;
u_long bytes_in; /* statistics */
u_long bytes_out;
u_int delta_error_counts[CE_NTYPES];
u_long error_counts[CE_NTYPES];
/*
* Data area for output buffers. Someday we should build the output
* buffer queue without copying data.
*/
#ifdef PC98
int obufsize;
u_char *obuf1;
u_char *obuf2;
#else
u_char obuf1[256];
u_char obuf2[256];
#endif
#ifdef DEVFS
void *devfs_token_ttyd;
void *devfs_token_ttyl;
void *devfs_token_ttyi;
void *devfs_token_cuaa;
void *devfs_token_cual;
void *devfs_token_cuai;
#endif
};
#ifdef COM_ESP
static int espattach __P((struct com_s *com, Port_t esp_port));
#endif
static int sioattach __P((device_t dev));
static timeout_t siobusycheck;
static timeout_t siodtrwakeup;
static void comhardclose __P((struct com_s *com));
static void sioinput __P((struct com_s *com));
static void siointr1 __P((struct com_s *com));
static void siointr __P((void *arg));
static int commctl __P((struct com_s *com, int bits, int how));
static int comparam __P((struct tty *tp, struct termios *t));
static swihand_t siopoll;
static int sioprobe __P((device_t dev));
static void siosettimeout __P((void));
static int siosetwater __P((struct com_s *com, speed_t speed));
static void comstart __P((struct tty *tp));
static timeout_t comwakeup;
static void disc_optim __P((struct tty *tp, struct termios *t,
struct com_s *com));
static char driver_name[] = "sio";
/* table and macro for fast conversion from a unit number to its com struct */
static devclass_t sio_devclass;
#define com_addr(unit) ((struct com_s *) \
devclass_get_softc(sio_devclass, unit))
static device_method_t sio_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, sioprobe),
DEVMETHOD(device_attach, sioattach),
{ 0, 0 }
};
static driver_t sio_driver = {
driver_name,
sio_methods,
sizeof(struct com_s),
};
static d_open_t sioopen;
static d_close_t sioclose;
static d_read_t sioread;
static d_write_t siowrite;
static d_ioctl_t sioioctl;
static d_stop_t siostop;
static d_devtotty_t siodevtotty;
#define CDEV_MAJOR 28
static struct cdevsw sio_cdevsw = {
sioopen, sioclose, sioread, siowrite,
sioioctl, siostop, noreset, siodevtotty,
ttpoll, nommap, NULL, driver_name,
NULL, -1, nodump, nopsize,
D_TTY,
};
int comconsole = -1;
static volatile speed_t comdefaultrate = CONSPEED;
#ifdef __alpha__
static volatile speed_t gdbdefaultrate = CONSPEED;
#endif
static u_int com_events; /* input chars + weighted output completions */
static Port_t siocniobase;
static int siocnunit;
static Port_t siogdbiobase;
static int siogdbunit = -1;
static bool_t sio_registered;
static int sio_timeout;
static int sio_timeouts_until_log;
static struct callout_handle sio_timeout_handle
= CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
#if 0 /* XXX */
static struct tty *sio_tty[NSIOTOT];
#else
static struct tty sio_tty[NSIOTOT];
#endif
static const int nsio_tty = NSIOTOT;
#ifdef PC98
struct siodev {
short if_type;
short irq;
Port_t cmd, sts, ctrl, mod;
};
static int sysclock;
#define COM_INT_DISABLE {int previpri; previpri=spltty();
#define COM_INT_ENABLE splx(previpri);}
#define IEN_TxFLAG IEN_Tx
#define COM_CARRIER_DETECT_EMULATE 0
#define PC98_CHECK_MODEM_INTERVAL (hz/10)
#define DCD_OFF_TOLERANCE 2
#define DCD_ON_RECOGNITION 2
#define IS_8251(if_type) (!(if_type & 0x10))
#define COM1_EXT_CLOCK 0x40000
static void commint __P((dev_t dev));
static void com_tiocm_set __P((struct com_s *com, int msr));
static void com_tiocm_bis __P((struct com_s *com, int msr));
static void com_tiocm_bic __P((struct com_s *com, int msr));
static int com_tiocm_get __P((struct com_s *com));
static int com_tiocm_get_delta __P((struct com_s *com));
static void pc98_msrint_start __P((dev_t dev));
static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
static int pc98_ttspeedtab __P((struct com_s *com, int speed));
static int pc98_get_modem_status __P((struct com_s *com));
static timeout_t pc98_check_msr;
static void pc98_set_baud_rate __P((struct com_s *com, int count));
static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
static int pc98_check_i8251_interrupt __P((struct com_s *com));
static int pc98_i8251_get_cmd __P((struct com_s *com));
static int pc98_i8251_get_mod __P((struct com_s *com));
static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
static void pc98_check_sysclock __P((void));
static int pc98_set_ioport __P((struct com_s *com, int id_flags));
#define com_int_Tx_disable(com) \
pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
#define com_int_Tx_enable(com) \
pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
#define com_int_Rx_disable(com) \
pc98_disable_i8251_interrupt(com,IEN_Rx)
#define com_int_Rx_enable(com) \
pc98_enable_i8251_interrupt(com,IEN_Rx)
#define com_int_TxRx_disable(com) \
pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
#define com_int_TxRx_enable(com) \
pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
#define com_send_break_on(com) \
pc98_i8251_or_cmd(com,CMD8251_SBRK)
#define com_send_break_off(com) \
pc98_i8251_clear_cmd(com,CMD8251_SBRK)
static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
{ 0, 0, },
{ 50, 50, },
{ 75, 75, },
{ 150, 150, },
{ 200, 200, },
{ 300, 300, },
{ 600, 600, },
{ 1200, 1200, },
{ 2400, 2400, },
{ 4800, 4800, },
{ 9600, 9600, },
{ 19200, 19200, },
{ 38400, 38400, },
{ 51200, 51200, },
{ 76800, 76800, },
{ 20800, 20800, },
{ 31200, 31200, },
{ 41600, 41600, },
{ 62400, 62400, },
{ -1, -1 }
};
static struct speedtab pc98fast_speedtab[] = {
{ 9600, 0x80 | COMBRD(9600), },
{ 19200, 0x80 | COMBRD(19200), },
{ 38400, 0x80 | COMBRD(38400), },
{ 57600, 0x80 | COMBRD(57600), },
{ 115200, 0x80 | COMBRD(115200), },
{ -1, -1 }
};
static struct speedtab comspeedtab_pio9032b[] = {
{ 300, 6, },
{ 600, 5, },
{ 1200, 4, },
{ 2400, 3, },
{ 4800, 2, },
{ 9600, 1, },
{ 19200, 0, },
{ 38400, 7, },
{ -1, -1 }
};
static struct speedtab comspeedtab_b98_01[] = {
{ 75, 11, },
{ 150, 10, },
{ 300, 9, },
{ 600, 8, },
{ 1200, 7, },
{ 2400, 6, },
{ 4800, 5, },
{ 9600, 4, },
{ 19200, 3, },
{ 38400, 2, },
{ 76800, 1, },
{ 153600, 0, },
{ -1, -1 }
};
static struct speedtab comspeedtab_mc16550[] = {
{ 300, 1536, },
{ 600, 768, },
{ 1200, 384, },
{ 2400, 192, },
{ 4800, 96, },
{ 9600, 48, },
{ 19200, 24, },
{ 38400, 12, },
{ 57600, 8, },
{ 115200, 4, },
{ 153600, 3, },
{ 230400, 2, },
{ 460800, 1, },
{ -1, -1 }
};
static struct speedtab comspeedtab_rsb384[] = {
{ 300, 3840, },
{ 600, 1920, },
{ 1200, 960, },
{ 2400, 480, },
{ 4800, 240, },
{ 9600, 120, },
{ 19200, 60, },
{ 38400, 30, },
{ 57600, 20, },
{ 115200, 10, },
{ 128000, 9, },
{ 144000, 8, },
{ 192000, 6, },
{ 230400, 5, },
{ 288000, 4, },
{ 384000, 3, },
{ 576000, 2, },
{ 1152000, 1, },
{ -1, -1 }
};
static struct speedtab comspeedtab_rsa[] = {
{ 0, 0 },
{ 50, COMBRD_RSA(50) },
{ 75, COMBRD_RSA(75) },
{ 110, COMBRD_RSA(110) },
{ 134, COMBRD_RSA(134) },
{ 150, COMBRD_RSA(150) },
{ 200, COMBRD_RSA(200) },
{ 300, COMBRD_RSA(300) },
{ 600, COMBRD_RSA(600) },
{ 1200, COMBRD_RSA(1200) },
{ 1800, COMBRD_RSA(1800) },
{ 2400, COMBRD_RSA(2400) },
{ 4800, COMBRD_RSA(4800) },
{ 9600, COMBRD_RSA(9600) },
{ 19200, COMBRD_RSA(19200) },
{ 38400, COMBRD_RSA(38400) },
{ 57600, COMBRD_RSA(57600) },
{ 115200, COMBRD_RSA(115200) },
{ 230400, COMBRD_RSA(230400) },
{ 460800, COMBRD_RSA(460800) },
{ 921600, COMBRD_RSA(921600) },
{ -1, -1 }
};
#endif /* PC98 */
static struct speedtab comspeedtab[] = {
{ 0, 0 },
{ 50, COMBRD(50) },
{ 75, COMBRD(75) },
{ 110, COMBRD(110) },
{ 134, COMBRD(134) },
{ 150, COMBRD(150) },
{ 200, COMBRD(200) },
{ 300, COMBRD(300) },
{ 600, COMBRD(600) },
{ 1200, COMBRD(1200) },
{ 1800, COMBRD(1800) },
{ 2400, COMBRD(2400) },
{ 4800, COMBRD(4800) },
{ 9600, COMBRD(9600) },
{ 19200, COMBRD(19200) },
{ 38400, COMBRD(38400) },
{ 57600, COMBRD(57600) },
{ 115200, COMBRD(115200) },
{ -1, -1 }
};
#ifdef PC98
struct {
char *name;
short port_table[7];
short irr_mask;
struct speedtab *speedtab;
short check_irq;
} if_8251_type[] = {
/* COM_IF_INTERNAL */
{ " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
-1, pc98speedtab, 1 },
/* COM_IF_PC9861K_1 */
{ " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
3, NULL, 1 },
/* COM_IF_PC9861K_2 */
{ " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
3, NULL, 1 },
/* COM_IF_IND_SS_1 */
{ " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
3, comspeedtab_mc16550, 1 },
/* COM_IF_IND_SS_2 */
{ " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
3, comspeedtab_mc16550, 1 },
/* COM_IF_PIO9032B_1 */
{ " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
7, comspeedtab_pio9032b, 1 },
/* COM_IF_PIO9032B_2 */
{ " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
7, comspeedtab_pio9032b, 1 },
/* COM_IF_B98_01_1 */
{ " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
7, comspeedtab_b98_01, 0 },
/* COM_IF_B98_01_2 */
{ " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
7, comspeedtab_b98_01, 0 },
};
#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
struct {
char *name;
short irr_read;
short irr_write;
short port_shift;
short io_size;
struct speedtab *speedtab;
} if_16550a_type[] = {
/* COM_IF_RSA98 */
{ " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
/* COM_IF_NS16550 */
{ "", -1, -1, 0, IO_COMSIZE, comspeedtab },
/* COM_IF_SECOND_CCU */
{ "", -1, -1, 0, IO_COMSIZE, comspeedtab },
/* COM_IF_MC16550II */
{ " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
/* COM_IF_MCRS98 */
{ " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
/* COM_IF_RSB3000 */
{ " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
/* COM_IF_RSB384 */
{ " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
/* COM_IF_MODEM_CARD */
{ "", -1, -1, 0, IO_COMSIZE, comspeedtab },
/* COM_IF_RSA98III */
{ " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
/* COM_IF_ESP98 */
{ " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
};
#endif /* PC98 */
#ifdef COM_ESP
#ifdef PC98
/* XXX configure this properly. */
static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
#define ESP98_CMD1 (ESP_CMD1 * 0x100)
#define ESP98_CMD2 (ESP_CMD2 * 0x100)
#define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
#define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
#else /* PC98 */
/* XXX configure this properly. */
static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
#endif /* PC98 */
#endif
/*
* handle sysctl read/write requests for console speed
*
* In addition to setting comdefaultrate for I/O through /dev/console,
* also set the initial and lock values for the /dev/ttyXX device
* if there is one associated with the console. Finally, if the /dev/tty
* device has already been open, change the speed on the open running port
* itself.
*/
static int
sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
{
int error, s;
speed_t newspeed;
struct com_s *com;
struct tty *tp;
newspeed = comdefaultrate;
error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
if (error || !req->newptr)
return (error);
comdefaultrate = newspeed;
if (comconsole < 0) /* serial console not selected? */
return (0);
com = com_addr(comconsole);
if (!com)
return (ENXIO);
/*
* set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
* (note, the lock rates really are boolean -- if non-zero, disallow
* speed changes)
*/
com->it_in.c_ispeed = com->it_in.c_ospeed =
com->lt_in.c_ispeed = com->lt_in.c_ospeed =
com->it_out.c_ispeed = com->it_out.c_ospeed =
com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
/*
* if we're open, change the running rate too
*/
tp = com->tp;
if (tp && (tp->t_state & TS_ISOPEN)) {
tp->t_termios.c_ispeed =
tp->t_termios.c_ospeed = comdefaultrate;
s = spltty();
error = comparam(tp, &tp->t_termios);
splx(s);
}
return error;
}
SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
0, 0, sysctl_machdep_comdefaultrate, "I", "");
#if NCARD > 0
/*
* PC-Card (PCMCIA) specific code.
*/
static int sioinit __P((struct pccard_devinfo *));
static void siounload __P((struct pccard_devinfo *));
static int card_intr __P((struct pccard_devinfo *));
PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
/*
* Initialize the device - called from Slot manager.
*/
int
sioinit(struct pccard_devinfo *devi)
{
/* validate unit number. */
if (devi->isahd.id_unit >= (NSIOTOT))
return(ENODEV);
/* Make sure it isn't already probed. */
if (com_addr(devi->isahd.id_unit))
return(EBUSY);
/* It's already probed as serial by Upper */
devi->isahd.id_flags |= COM_C_NOPROBE;
/*
* Probe the device. If a value is returned, the
* device was found at the location.
*/
if (sioprobe(&devi->isahd) == 0)
return(ENXIO);
if (sioattach(&devi->isahd) == 0)
return(ENXIO);
return(0);
}
/*
* siounload - unload the driver and clear the table.
* XXX TODO:
* This is usually called when the card is ejected, but
* can be caused by a modunload of a controller driver.
* The idea is to reset the driver's view of the device
* and ensure that any driver entry points such as
* read and write do not hang.
*/
static void
siounload(struct pccard_devinfo *devi)
{
struct com_s *com;
if (!devi) {
printf("NULL devi in siounload\n");
return;
}
com = com_addr(devi->isahd.id_unit);
if (!com) {
printf("NULL com in siounload\n");
return;
}
if (!com->iobase) {
printf("sio%d already unloaded!\n",devi->isahd.id_unit);
return;
}
if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
com->gone = 1;
printf("sio%d: unload\n", devi->isahd.id_unit);
com->tp->t_gen++;
ttyclose(com->tp);
ttwakeup(com->tp);
ttwwakeup(com->tp);
} else {
if (com->ibuf != NULL)
free(com->ibuf, M_DEVBUF);
free(com, M_DEVBUF);
printf("sio%d: unload,gone\n", devi->isahd.id_unit);
}
}
/*
* card_intr - Shared interrupt called from
* front end of PC-Card handler.
*/
static int
card_intr(struct pccard_devinfo *devi)
{
struct com_s *com;
COM_LOCK();
com = com_addr(devi->isahd.id_unit);
if (com && !com->gone)
siointr1(com_addr(devi->isahd.id_unit));
COM_UNLOCK();
return(1);
}
#endif /* NCARD > 0 */
#define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
#define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
static int
sioprobe(dev)
device_t dev;
{
static bool_t already_init;
bool_t failures[10];
int fn;
device_t idev;
Port_t iobase;
intrmask_t irqmap[4];
intrmask_t irqs;
u_char mcr_image;
int result;
device_t xdev;
u_int flags = isa_get_flags(dev);
#ifdef PC98
int irqout=0;
int tmp;
int port_shift = 0;
struct siodev iod;
Port_t rsabase = NULL;
#endif
if (!already_init) {
/*
* Turn off MCR_IENABLE for all likely serial ports. An unused
* port with its MCR_IENABLE gate open will inhibit interrupts
* from any used port that shares the interrupt vector.
* XXX the gate enable is elsewhere for some multiports.
*/
device_t *devs;
int count, i;
devclass_get_devices(sio_devclass, &devs, &count);
#ifdef PC98
for (i = 0; i < count; i++) {
xdev = devs[i];
tmp = (flags >> 24) & 0xff;
if (IS_8251(tmp))
outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
else
if (tmp == COM_IF_RSA98III) {
rsabase = isa_get_port(xdev) & 0xfff0;
outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
} else
outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
}
#else
for (i = 0; i < count; i++) {
xdev = devs[i];
outb(isa_get_port(xdev) + com_mcr, 0);
}
#endif
free(devs, M_TEMP);
already_init = TRUE;
}
if (COM_LLCONSOLE(flags)) {
printf("sio%d: reserved for low-level i/o\n",
device_get_unit(dev));
return (ENXIO);
}
#ifdef PC98
DELAY(10);
/*
* If the port is i8251 UART (internal, B98_01)
*/
if (pc98_check_if_type(dev, &iod) == -1)
return ENXIO;
if (iod.irq > 0)
isa_set_irq(dev, iod.irq);
if (IS_8251(iod.if_type)) {
outb(iod.cmd, 0);
DELAY(10);
outb(iod.cmd, 0);
DELAY(10);
outb(iod.cmd, 0);
DELAY(10);
outb(iod.cmd, CMD8251_RESET);
DELAY(1000); /* for a while...*/
outb(iod.cmd, 0xf2); /* MODE (dummy) */
DELAY(10);
outb(iod.cmd, 0x01); /* CMD (dummy) */
DELAY(1000); /* for a while...*/
if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
result = ENXIO;
}
if (if_8251_type[iod.if_type & 0x0f].check_irq) {
COM_INT_DISABLE
tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
outb( iod.ctrl, tmp|IEN_TxEMP );
DELAY(10);
result = isa_irq_pending() ? 0 : ENXIO;
outb( iod.ctrl, tmp );
COM_INT_ENABLE
} else {
/*
* B98_01 doesn't activate TxEMP interrupt line
* when being reset, so we can't check irq pending.
*/
result = 0;
}
if (epson_machine_id==0x20) { /* XXX */
result = 0;
}
isa_set_portsize(dev, 4);
return result;
}
#endif /* PC98 */
/*
* If the device is on a multiport card and has an AST/4
* compatible interrupt control register, initialize this
* register and prepare to leave MCR_IENABLE clear in the mcr.
* Otherwise, prepare to set MCR_IENABLE in the mcr.
* Point idev to the device struct giving the correct id_irq.
* This is the struct for the master device if there is one.
*/
idev = dev;
mcr_image = MCR_IENABLE;
#ifdef PC98
if (iod.if_type == COM_IF_RSA98III) {
mcr_image = 0;
rsabase = isa_get_port(idev) & 0xfff0;
if (rsabase != isa_get_port(idev))
return(0);
outb(rsabase + rsa_msr, 0x04);
outb(rsabase + rsa_frr, 0x00);
if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
return (0);
outb(rsabase + rsa_ier, 0x00);
outb(rsabase + rsa_frr, 0x00);
outb(rsabase + rsa_tivsr, 0x00);
outb(rsabase + rsa_tcr, 0x00);
}
#endif /* PC98 */
#ifdef COM_MULTIPORT
if (COM_ISMULTIPORT(flags)) {
idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
if (idev == NULL) {
printf("sio%d: master device %d not configured\n",
device_get_unit(dev), COM_MPMASTER(flags));
isa_set_irq(dev, 0);
idev = dev;
}
#ifndef PC98
if (!COM_NOTAST4(flags)) {
outb(isa_get_port(idev) + com_scr,
isa_get_irq(idev) >= 0 ? 0x80 : 0);
mcr_image = 0;
}
#endif /* !PC98 */
}
#endif /* COM_MULTIPORT */
if (isa_get_irq(idev) < 0)
mcr_image = 0;
#ifdef PC98
tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
if (tmp != -1) {
/* MC16550II */
switch (isa_get_irq(idev)) {
case 3: irqout = 4; break;
case 5: irqout = 5; break;
case 6: irqout = 6; break;
case 12: irqout = 7; break;
default:
printf("sio%d: irq configuration error\n",
device_get_unit(dev));
return (0);
}
outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
}
port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
#endif
bzero(failures, sizeof failures);
iobase = isa_get_port(dev);
#ifdef PC98
if (iod.if_type == COM_IF_RSA98III)
iobase += 8;
#endif
/*
* We don't want to get actual interrupts, just masked ones.
* Interrupts from this line should already be masked in the ICU,
* but mask them in the processor as well in case there are some
* (misconfigured) shared interrupts.
*/
disable_intr();
/* EXTRA DELAY? */
/*
* Initialize the speed and the word size and wait long enough to
* drain the maximum of 16 bytes of junk in device output queues.
* The speed is undefined after a master reset and must be set
* before relying on anything related to output. There may be
* junk after a (very fast) soft reboot and (apparently) after
* master reset.
* XXX what about the UART bug avoided by waiting in comparam()?
* We don't want to to wait long enough to drain at 2 bps.
*/
if (iobase == siocniobase)
DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
else {
#ifdef PC98
tmp = ttspeedtab(SIO_TEST_SPEED,
if_16550a_type[iod.if_type & 0x0f].speedtab);
outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
#else
outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
outb(iobase + com_cfcr, CFCR_8BITS);
#endif
DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
}
/*
* Enable the interrupt gate and disable device interupts. This
* should leave the device driving the interrupt line low and
* guarantee an edge trigger if an interrupt can be generated.
*/
/* EXTRA DELAY? */
#ifdef PC98
outb(iobase + (com_mcr << port_shift), mcr_image);
outb(iobase + (com_ier << port_shift), 0);
#else
outb(iobase + com_mcr, mcr_image);
outb(iobase + com_ier, 0);
#endif
DELAY(1000); /* XXX */
irqmap[0] = isa_irq_pending();
/*
* Attempt to set loopback mode so that we can send a null byte
* without annoying any external device.
*/
/* EXTRA DELAY? */
#ifdef PC98
outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
#else
outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
#endif
/*
* Attempt to generate an output interrupt. On 8250's, setting
* IER_ETXRDY generates an interrupt independent of the current
* setting and independent of whether the THR is empty. On 16450's,
* setting IER_ETXRDY generates an interrupt independent of the
* current setting. On 16550A's, setting IER_ETXRDY only
* generates an interrupt when IER_ETXRDY is not already set.
*/
#ifdef PC98
outb(iobase + (com_ier << port_shift), IER_ETXRDY);
if (iod.if_type == COM_IF_RSA98III)
outb(rsabase + rsa_ier, 0x04);
#else
outb(iobase + com_ier, IER_ETXRDY);
#endif /* PC98 */
/*
* On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
* an interrupt. They'd better generate one for actually doing
* output. Loopback may be broken on the same incompatibles but
* it's unlikely to do more than allow the null byte out.
*/
#ifdef PC98
outb(iobase + (com_data << port_shift), 0);
#else
outb(iobase + com_data, 0);
#endif
DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
/*
* Turn off loopback mode so that the interrupt gate works again
* (MCR_IENABLE was hidden). This should leave the device driving
* an interrupt line high. It doesn't matter if the interrupt
* line oscillates while we are not looking at it, since interrupts
* are disabled.
*/
/* EXTRA DELAY? */
#ifdef PC98
outb(iobase + (com_mcr << port_shift), mcr_image);
#else
outb(iobase + com_mcr, mcr_image);
#endif /* PC98 */
/*
* It's a definitly Serial PCMCIA(16550A), but still be required
* for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
*/
if ( COM_NOPROBE(flags) ) {
/* Reading IIR register twice */
for ( fn = 0; fn < 2; fn ++ ) {
DELAY(10000);
#ifdef PC98
failures[6] = inb(iobase + (com_iir << port_shift));
#else
failures[6] = inb(iobase + com_iir);
#endif
}
/* Check IIR_TXRDY clear ? */
#ifdef PC98
isa_set_portsize(dev,
if_16550a_type[iod.if_type & 0x0f].io_size);
#else
isa_set_portsize(dev, IO_COMSIZE);
#endif
result = 0;
if ( failures[6] & IIR_TXRDY ) {
/* Nop, Double check with clearing IER */
#ifdef PC98
outb(iobase + (com_ier << port_shift), 0);
if (inb(iobase +
(com_iir << port_shift)) & IIR_NOPEND) {
#else
outb(iobase + com_ier, 0);
if ( inb(iobase + com_iir) & IIR_NOPEND ) {
#endif
/* Ok. we're familia this gang */
SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
} else {
/* Unknow, Just omit this chip.. XXX*/
result = ENXIO;
}
} else {
/* OK. this is well-known guys */
CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
}
#ifdef PC98
outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
#else
outb(iobase + com_cfcr, CFCR_8BITS);
#endif
enable_intr();
return (iobase == siocniobase ? 0 : result);
}
/*
* Check that
* o the CFCR, IER and MCR in UART hold the values written to them
* (the values happen to be all distinct - this is good for
* avoiding false positive tests from bus echoes).
* o an output interrupt is generated and its vector is correct.
* o the interrupt goes away when the IIR in the UART is read.
*/
/* EXTRA DELAY? */
#ifdef PC98
failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
#else
failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
failures[2] = inb(iobase + com_mcr) - mcr_image;
#endif
DELAY(10000); /* Some internal modems need this time */
irqmap[1] = isa_irq_pending();
#ifdef PC98
failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
- IIR_TXRDY;
if (iod.if_type == COM_IF_RSA98III)
inb(rsabase + rsa_srr);
#else
failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
#endif
DELAY(1000); /* XXX */
irqmap[2] = isa_irq_pending();
#ifdef PC98
failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
- IIR_NOPEND;
if (iod.if_type == COM_IF_RSA98III)
inb(rsabase + rsa_srr);
#else
failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
#endif
/*
* Turn off all device interrupts and check that they go off properly.
* Leave MCR_IENABLE alone. For ports without a master port, it gates
* the OUT2 output of the UART to
* the ICU input. Closing the gate would give a floating ICU input
* (unless there is another device driving it) and spurious interrupts.
* (On the system that this was first tested on, the input floats high
* and gives a (masked) interrupt as soon as the gate is closed.)
*/
#ifdef PC98
outb(iobase + (com_ier << port_shift), 0);
outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
failures[7] = inb(iobase + (com_ier << port_shift));
if (iod.if_type == COM_IF_RSA98III)
outb(rsabase + rsa_ier, 0x00);
#else
outb(iobase + com_ier, 0);
outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
failures[7] = inb(iobase + com_ier);
#endif
DELAY(1000); /* XXX */
irqmap[3] = isa_irq_pending();
#ifdef PC98
failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
- IIR_NOPEND;
if (iod.if_type == COM_IF_RSA98III) {
inb(rsabase + rsa_srr);
outb(rsabase + rsa_frr, 0x00);
}
#else
failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
#endif
enable_intr();
irqs = irqmap[1] & ~irqmap[0];
if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
printf(
"sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
device_get_unit(dev), isa_get_irq(idev), irqs);
if (bootverbose)
printf("sio%d: irq maps: %#x %#x %#x %#x\n",
device_get_unit(dev),
irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
#ifdef PC98
isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size);
#else
isa_set_portsize(dev, IO_COMSIZE);
#endif
result = 0;
for (fn = 0; fn < sizeof failures; ++fn)
if (failures[fn]) {
#ifdef PC98
outb(iobase + (com_mcr << port_shift), 0);
#else
outb(iobase + com_mcr, 0);
#endif
result = ENXIO;
if (bootverbose) {
printf("sio%d: probe failed test(s):",
device_get_unit(dev));
for (fn = 0; fn < sizeof failures; ++fn)
if (failures[fn])
printf(" %d", fn);
printf("\n");
}
break;
}
return (iobase == siocniobase ? 0 : result);
}
#ifdef COM_ESP
static int
espattach(com, esp_port)
struct com_s *com;
Port_t esp_port;
{
u_char dips;
u_char val;
/*
* Check the ESP-specific I/O port to see if we're an ESP
* card. If not, return failure immediately.
*/
if ((inb(esp_port) & 0xf3) == 0) {
printf(" port 0x%x is not an ESP board?\n", esp_port);
return (0);
}
/*
* We've got something that claims to be a Hayes ESP card.
* Let's hope so.
*/
/* Get the dip-switch configuration */
#ifdef PC98
outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
dips = inb(esp_port + ESP98_STATUS1);
#else
outb(esp_port + ESP_CMD1, ESP_GETDIPS);
dips = inb(esp_port + ESP_STATUS1);
#endif
/*
* Bits 0,1 of dips say which COM port we are.
*/
#ifdef PC98
if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
#else
if (com->iobase == likely_com_ports[dips & 0x03])
#endif
printf(" : ESP");
else {
printf(" esp_port has com %d\n", dips & 0x03);
return (0);
}
/*
* Check for ESP version 2.0 or later: bits 4,5,6 = 010.
*/
#ifdef PC98
outb(esp_port + ESP98_CMD1, ESP_GETTEST);
val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
val = inb(esp_port + ESP98_STATUS2);
#else
outb(esp_port + ESP_CMD1, ESP_GETTEST);
val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
val = inb(esp_port + ESP_STATUS2);
#endif
if ((val & 0x70) < 0x20) {
printf("-old (%o)", val & 0x70);
return (0);
}
/*
* Check for ability to emulate 16550: bit 7 == 1
*/
if ((dips & 0x80) == 0) {
printf(" slave");
return (0);
}
/*
* Okay, we seem to be a Hayes ESP card. Whee.
*/
com->esp = TRUE;
com->esp_port = esp_port;
return (1);
}
#endif /* COM_ESP */
static int
sioattach(dev)
device_t dev;
{
struct com_s *com;
#ifdef COM_ESP
Port_t *espp;
#endif
Port_t iobase;
int unit;
void *ih;
struct resource *res;
int zero = 0;
u_int flags = isa_get_flags(dev);
#ifdef PC98
int port_shift = 0;
u_char *obuf;
u_long obufsize;
#endif
iobase = isa_get_port(dev);
#ifdef PC98
if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
iobase += 8;
#endif
unit = device_get_unit(dev);
com = device_get_softc(dev);
#ifdef PC98
obufsize = 256;
if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
obufsize = 2048;
if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
return (0);
bzero(obuf, obufsize * 2);
#endif
/*
* sioprobe() has initialized the device registers as follows:
* o cfcr = CFCR_8BITS.
* It is most important that CFCR_DLAB is off, so that the
* data port is not hidden when we enable interrupts.
* o ier = 0.
* Interrupts are only enabled when the line is open.
* o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
* interrupt control register or the config specifies no irq.
* Keeping MCR_DTR and MCR_RTS off might stop the external
* device from sending before we are ready.
*/
bzero(com, sizeof *com);
#ifdef PC98
com->obufsize = obufsize;
com->obuf1 = obuf;
com->obuf2 = obuf + obufsize;
#endif
com->unit = unit;
com->cfcr_image = CFCR_8BITS;
com->dtr_wait = 3 * hz;
com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
com->no_irq = isa_get_irq(dev) < 0;
com->tx_fifo_size = 1;
com->obufs[0].l_head = com->obuf1;
com->obufs[1].l_head = com->obuf2;
com->iobase = iobase;
#ifdef PC98
if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) {
com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff;
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
com->data_port = iobase + (com_data << port_shift);
com->int_id_port = iobase + (com_iir << port_shift);
com->modem_ctl_port = iobase + (com_mcr << port_shift);
com->mcr_image = inb(com->modem_ctl_port);
com->line_status_port = iobase + (com_lsr << port_shift);
com->modem_status_port = iobase + (com_msr << port_shift);
com->intr_ctl_port = iobase + (com_ier << port_shift);
}
#else /* not PC98 */
com->data_port = iobase + com_data;
com->int_id_port = iobase + com_iir;
com->modem_ctl_port = iobase + com_mcr;
com->mcr_image = inb(com->modem_ctl_port);
com->line_status_port = iobase + com_lsr;
com->modem_status_port = iobase + com_msr;
com->intr_ctl_port = iobase + com_ier;
#endif
/*
* We don't use all the flags from <sys/ttydefaults.h> since they
* are only relevant for logins. It's important to have echo off
* initially so that the line doesn't start blathering before the
* echo flag can be turned off.
*/
com->it_in.c_iflag = 0;
com->it_in.c_oflag = 0;
com->it_in.c_cflag = TTYDEF_CFLAG;
com->it_in.c_lflag = 0;
if (unit == comconsole) {
#ifdef PC98
if (IS_8251(com->pc98_if_type))
DELAY(100000);
#endif
com->it_in.c_iflag = TTYDEF_IFLAG;
com->it_in.c_oflag = TTYDEF_OFLAG;
com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
com->it_in.c_lflag = TTYDEF_LFLAG;
com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
com->lt_out.c_ispeed = com->lt_out.c_ospeed =
com->lt_in.c_ispeed = com->lt_in.c_ospeed =
com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
} else
com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
if (siosetwater(com, com->it_in.c_ispeed) != 0) {
enable_intr();
free(com, M_DEVBUF);
return (0);
}
enable_intr();
termioschars(&com->it_in);
com->it_out = com->it_in;
/* attempt to determine UART type */
printf("sio%d: type", unit);
#ifndef PC98
#ifdef COM_MULTIPORT
if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
#else
if (!COM_IIR_TXRDYBUG(flags))
#endif
{
u_char scr;
u_char scr1;
u_char scr2;
scr = inb(iobase + com_scr);
outb(iobase + com_scr, 0xa5);
scr1 = inb(iobase + com_scr);
outb(iobase + com_scr, 0x5a);
scr2 = inb(iobase + com_scr);
outb(iobase + com_scr, scr);
if (scr1 != 0xa5 || scr2 != 0x5a) {
printf(" 8250");
goto determined_type;
}
}
#endif /* !PC98 */
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
com_int_TxRx_disable( com );
com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
com_send_break_off( com );
printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
} else {
outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
#else
outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
#endif /* PC98 */
DELAY(100);
com->st16650a = 0;
switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
case FIFO_RX_LOW:
printf(" 16450");
break;
case FIFO_RX_MEDL:
printf(" 16450?");
break;
case FIFO_RX_MEDH:
printf(" 16550?");
break;
case FIFO_RX_HIGH:
if (COM_NOFIFO(flags)) {
printf(" 16550A fifo disabled");
} else {
com->hasfifo = TRUE;
#ifdef PC98
com->tx_fifo_size = 0; /* XXX flag conflicts. */
printf(" 16550A");
#else
if (COM_ST16650A(flags)) {
com->st16650a = 1;
com->tx_fifo_size = 32;
printf(" ST16650A");
} else {
com->tx_fifo_size = COM_FIFOSIZE(flags);
printf(" 16550A");
}
#endif
}
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
com->tx_fifo_size = 2048;
com->rsabase = isa_get_port(dev);
outb(com->rsabase + rsa_ier, 0x00);
outb(com->rsabase + rsa_frr, 0x00);
}
#endif
#ifdef COM_ESP
#ifdef PC98
if (com->pc98_if_type == COM_IF_ESP98)
#endif
for (espp = likely_esp_ports; *espp != 0; espp++)
if (espattach(com, *espp)) {
com->tx_fifo_size = 1024;
break;
}
#endif
if (!com->st16650a) {
if (!com->tx_fifo_size)
com->tx_fifo_size = 16;
else
printf(" lookalike with %d bytes FIFO",
com->tx_fifo_size);
}
break;
}
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSB3000) {
/* Set RSB-2000/3000 Extended Buffer mode. */
u_char lcr;
lcr = inb(iobase + (com_cfcr << port_shift));
outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
outb(iobase + (com_cfcr << port_shift), lcr);
}
#endif
#ifdef COM_ESP
if (com->esp) {
/*
* Set 16550 compatibility mode.
* We don't use the ESP_MODE_SCALE bit to increase the
* fifo trigger levels because we can't handle large
* bursts of input.
* XXX flow control should be set in comparam(), not here.
*/
#ifdef PC98
outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
#else
outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
#endif
/* Set RTS/CTS flow control. */
#ifdef PC98
outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
#else
outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
#endif
/* Set flow-control levels. */
#ifdef PC98
outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
#else
outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
outb(com->esp_port + ESP_CMD2, HIBYTE(768));
outb(com->esp_port + ESP_CMD2, LOBYTE(768));
outb(com->esp_port + ESP_CMD2, HIBYTE(512));
outb(com->esp_port + ESP_CMD2, LOBYTE(512));
#endif
#ifdef PC98
/* Set UART clock prescaler. */
outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
#endif
}
#endif /* COM_ESP */
#ifdef PC98
printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
outb(iobase + (com_fifo << port_shift), 0);
#else
outb(iobase + com_fifo, 0);
determined_type: ;
#endif
#ifdef COM_MULTIPORT
if (COM_ISMULTIPORT(flags)) {
com->multiport = TRUE;
printf(" (multiport");
if (unit == COM_MPMASTER(flags))
printf(" master");
printf(")");
com->no_irq =
isa_get_irq(devclass_get_device
(sio_devclass, COM_MPMASTER(flags))) < 0;
}
#endif /* COM_MULTIPORT */
#ifdef PC98
}
#endif
if (unit == comconsole)
printf(", console");
if ( COM_IIR_TXRDYBUG(flags) )
printf(" with a bogus IIR_TXRDY register");
printf("\n");
if (!sio_registered) {
register_swi(SWI_TTY, siopoll);
sio_registered = TRUE;
}
#ifdef DEVFS
com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
unit, DV_CHR,
UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,
unit | CONTROL_INIT_STATE, DV_CHR,
UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw,
unit | CONTROL_LOCK_STATE, DV_CHR,
UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw,
unit | CALLOUT_MASK, DV_CHR,
UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
#endif
com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
pps_init(&com->pps);
res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
RF_SHAREABLE | RF_ACTIVE);
BUS_SETUP_INTR(device_get_parent(dev), dev, res,
INTR_TYPE_TTY | INTR_TYPE_FAST,
siointr, com, &ih);
return (0);
}
static int
sioopen(dev, flag, mode, p)
dev_t dev;
int flag;
int mode;
struct proc *p;
{
struct com_s *com;
int error;
Port_t iobase;
int mynor;
int s;
struct tty *tp;
int unit;
#ifdef PC98
int port_shift = 0;
#endif
mynor = minor(dev);
unit = MINOR_TO_UNIT(mynor);
if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
return (ENXIO);
if (com->gone)
return (ENXIO);
if (mynor & CONTROL_MASK)
return (0);
#if 0 /* XXX */
tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
#else
tp = com->tp = &sio_tty[unit];
#endif
s = spltty();
#ifdef PC98
if (!IS_8251(com->pc98_if_type))
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
#endif
/*
* We jump to this label after all non-interrupted sleeps to pick
* up any changes of the device state.
*/
open_top:
while (com->state & CS_DTR_OFF) {
error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
if (com_addr(unit) == NULL)
return (ENXIO);
if (error != 0 || com->gone)
goto out;
}
if (tp->t_state & TS_ISOPEN) {
/*
* The device is open, so everything has been initialized.
* Handle conflicts.
*/
if (mynor & CALLOUT_MASK) {
if (!com->active_out) {
error = EBUSY;
goto out;
}
} else {
if (com->active_out) {
if (flag & O_NONBLOCK) {
error = EBUSY;
goto out;
}
error = tsleep(&com->active_out,
TTIPRI | PCATCH, "siobi", 0);
if (com_addr(unit) == NULL)
return (ENXIO);
if (error != 0 || com->gone)
goto out;
goto open_top;
}
}
if (tp->t_state & TS_XCLUDE &&
suser(p)) {
error = EBUSY;
goto out;
}
} else {
/*
* The device isn't open, so there are no conflicts.
* Initialize it. Initialization is done twice in many
* cases: to preempt sleeping callin opens if we are
* callout, and to complete a callin open after DCD rises.
*/
tp->t_oproc = comstart;
tp->t_param = comparam;
tp->t_dev = dev;
tp->t_termios = mynor & CALLOUT_MASK
? com->it_out : com->it_in;
#ifdef PC98
if (!IS_8251(com->pc98_if_type))
#endif
(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
com->poll = com->no_irq;
com->poll_output = com->loses_outints;
++com->wopeners;
error = comparam(tp, &tp->t_termios);
--com->wopeners;
if (error != 0)
goto out;
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
pc98_msrint_start(dev);
}
#endif
/*
* XXX we should goto open_top if comparam() slept.
*/
iobase = com->iobase;
if (com->hasfifo) {
/*
* (Re)enable and drain fifos.
*
* Certain SMC chips cause problems if the fifos
* are enabled while input is ready. Turn off the
* fifo if necessary to clear the input. We test
* the input ready bit after enabling the fifos
* since we've already enabled them in comparam()
* and to handle races between enabling and fresh
* input.
*/
while (TRUE) {
#ifdef PC98
outb(iobase + (com_fifo << port_shift),
FIFO_RCV_RST | FIFO_XMT_RST
| com->fifo_image);
if (com->pc98_if_type == COM_IF_RSA98III)
outb(com->rsabase + rsa_frr , 0x00);
#else
outb(iobase + com_fifo,
FIFO_RCV_RST | FIFO_XMT_RST
| com->fifo_image);
#endif
/*
* XXX the delays are for superstitious
* historical reasons. It must be less than
* the character time at the maximum
* supported speed (87 usec at 115200 bps
* 8N1). Otherwise we might loop endlessly
* if data is streaming in. We used to use
* delays of 100. That usually worked
* because DELAY(100) used to usually delay
* for about 85 usec instead of 100.
*/
DELAY(50);
#ifndef PC98
if (!(inb(com->line_status_port) & LSR_RXRDY))
#else
if (com->pc98_if_type == COM_IF_RSA98III
? !(inb(com->rsabase + rsa_srr) & 0x08)
: !(inb(com->line_status_port) & LSR_RXRDY))
#endif
break;
#ifdef PC98
outb(iobase + (com_fifo << port_shift), 0);
#else
outb(iobase + com_fifo, 0);
#endif
DELAY(50);
(void) inb(com->data_port);
}
}
disable_intr();
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
com_tiocm_bis(com, TIOCM_LE);
com->pc98_prev_modem_status = pc98_get_modem_status(com);
com_int_Rx_enable(com);
} else {
#endif
(void) inb(com->line_status_port);
(void) inb(com->data_port);
com->prev_modem_status = com->last_modem_status
= inb(com->modem_status_port);
if (COM_IIR_TXRDYBUG(com->flags)) {
outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
| IER_EMSC);
} else {
outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
| IER_ERLS | IER_EMSC);
}
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
outb(com->rsabase + rsa_ier, 0x1d);
outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
}
#endif
#ifdef PC98
}
#endif
enable_intr();
/*
* Handle initial DCD. Callout devices get a fake initial
* DCD (trapdoor DCD). If we are callout, then any sleeping
* callin opens get woken up and resume sleeping on "siobi"
* instead of "siodcd".
*/
/*
* XXX `mynor & CALLOUT_MASK' should be
* `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
* TRAPDOOR_CARRIER is the default initial state for callout
* devices and SOFT_CARRIER is like CLOCAL except it hides
* the true carrier.
*/
#ifdef PC98
if ((IS_8251(com->pc98_if_type) &&
(pc98_get_modem_status(com) & TIOCM_CAR)) ||
(!IS_8251(com->pc98_if_type) &&
(com->prev_modem_status & MSR_DCD)) ||
mynor & CALLOUT_MASK)
#else
if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
#endif
(*linesw[tp->t_line].l_modem)(tp, 1);
}
/*
* Wait for DCD if necessary.
*/
if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
&& !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
++com->wopeners;
error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
if (com_addr(unit) == NULL)
return (ENXIO);
--com->wopeners;
if (error != 0 || com->gone)
goto out;
goto open_top;
}
error = (*linesw[tp->t_line].l_open)(dev, tp);
disc_optim(tp, &tp->t_termios, com);
if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
com->active_out = TRUE;
siosettimeout();
out:
splx(s);
if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
comhardclose(com);
return (error);
}
static int
sioclose(dev, flag, mode, p)
dev_t dev;
int flag;
int mode;
struct proc *p;
{
struct com_s *com;
int mynor;
int s;
struct tty *tp;
mynor = minor(dev);
if (mynor & CONTROL_MASK)
return (0);
com = com_addr(MINOR_TO_UNIT(mynor));
tp = com->tp;
s = spltty();
(*linesw[tp->t_line].l_close)(tp, flag);
#ifdef PC98
com->modem_checking = 0;
#endif
disc_optim(tp, &tp->t_termios, com);
siostop(tp, FREAD | FWRITE);
comhardclose(com);
ttyclose(tp);
siosettimeout();
splx(s);
if (com->gone) {
printf("sio%d: gone\n", com->unit);
s = spltty();
if (com->ibuf != NULL)
free(com->ibuf, M_DEVBUF);
bzero(tp, sizeof *tp);
free(com, M_DEVBUF);
splx(s);
}
return (0);
}
static void
comhardclose(com)
struct com_s *com;
{
Port_t iobase;
int s;
struct tty *tp;
int unit;
#ifdef PC98
int port_shift = 0;
#endif
unit = com->unit;
iobase = com->iobase;
s = spltty();
com->poll = FALSE;
com->poll_output = FALSE;
com->do_timestamp = FALSE;
com->do_dcd_timestamp = FALSE;
com->pps.ppsparam.mode = 0;
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_send_break_off(com);
else {
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
outb(iobase + (com_cfcr << port_shift),
com->cfcr_image &= ~CFCR_SBREAK);
}
#else
outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
#endif
{
#ifdef PC98
int tmp;
if (IS_8251(com->pc98_if_type))
com_int_TxRx_disable(com);
else
outb(iobase + (com_ier << port_shift), 0);
if (com->pc98_if_type == COM_IF_RSA98III) {
outb(com->rsabase + rsa_ier, 0x00);
}
#else
outb(iobase + com_ier, 0);
#endif
tp = com->tp;
#ifdef PC98
if (IS_8251(com->pc98_if_type))
tmp = pc98_get_modem_status(com) & TIOCM_CAR;
else
tmp = com->prev_modem_status & MSR_DCD;
#endif
if (tp->t_cflag & HUPCL
/*
* XXX we will miss any carrier drop between here and the
* next open. Perhaps we should watch DCD even when the
* port is closed; it is not sufficient to check it at
* the next open because it might go up and down while
* we're not watching.
*/
|| (!com->active_out
#ifdef PC98
&& !(tmp)
#else
&& !(com->prev_modem_status & MSR_DCD)
#endif
&& !(com->it_in.c_cflag & CLOCAL))
|| !(tp->t_state & TS_ISOPEN)) {
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
else
#endif
(void)commctl(com, TIOCM_DTR, DMBIC);
if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
timeout(siodtrwakeup, com, com->dtr_wait);
com->state |= CS_DTR_OFF;
}
}
#ifdef PC98
else {
if (IS_8251(com->pc98_if_type))
com_tiocm_bic(com, TIOCM_LE );
}
#endif
}
if (com->hasfifo) {
/*
* Disable fifos so that they are off after controlled
* reboots. Some BIOSes fail to detect 16550s when the
* fifos are enabled.
*/
#ifdef PC98
outb(iobase + (com_fifo << port_shift), 0);
#else
outb(iobase + com_fifo, 0);
#endif
}
com->active_out = FALSE;
wakeup(&com->active_out);
wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
splx(s);
}
static int
sioread(dev, uio, flag)
dev_t dev;
struct uio *uio;
int flag;
{
int mynor;
struct com_s *com;
mynor = minor(dev);
if (mynor & CONTROL_MASK)
return (ENODEV);
com = com_addr(MINOR_TO_UNIT(mynor));
if (com->gone)
return (ENODEV);
return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
}
static int
siowrite(dev, uio, flag)
dev_t dev;
struct uio *uio;
int flag;
{
int mynor;
struct com_s *com;
int unit;
mynor = minor(dev);
if (mynor & CONTROL_MASK)
return (ENODEV);
unit = MINOR_TO_UNIT(mynor);
com = com_addr(unit);
if (com->gone)
return (ENODEV);
/*
* (XXX) We disallow virtual consoles if the physical console is
* a serial port. This is in case there is a display attached that
* is not the console. In that situation we don't need/want the X
* server taking over the console.
*/
if (constty != NULL && unit == comconsole)
constty = NULL;
return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
}
static void
siobusycheck(chan)
void *chan;
{
struct com_s *com;
int s;
com = (struct com_s *)chan;
/*
* Clear TS_BUSY if low-level output is complete.
* spl locking is sufficient because siointr1() does not set CS_BUSY.
* If siointr1() clears CS_BUSY after we look at it, then we'll get
* called again. Reading the line status port outside of siointr1()
* is safe because CS_BUSY is clear so there are no output interrupts
* to lose.
*/
s = spltty();
if (com->state & CS_BUSY)
com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
#ifdef PC98
else if ((IS_8251(com->pc98_if_type) &&
(inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
== (STS8251_TxRDY | STS8251_TxEMP)) ||
(inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
== (LSR_TSRE | LSR_TXRDY)) {
#else
else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
== (LSR_TSRE | LSR_TXRDY)) {
#endif
com->tp->t_state &= ~TS_BUSY;
ttwwakeup(com->tp);
com->extra_state &= ~CSE_BUSYCHECK;
} else
timeout(siobusycheck, com, hz / 100);
splx(s);
}
static void
siodtrwakeup(chan)
void *chan;
{
struct com_s *com;
com = (struct com_s *)chan;
com->state &= ~CS_DTR_OFF;
wakeup(&com->dtr_wait);
}
static void
sioinput(com)
struct com_s *com;
{
u_char *buf;
int incc;
u_char line_status;
int recv_data;
struct tty *tp;
#ifdef PC98
u_char tmp;
#endif
buf = com->ibuf;
tp = com->tp;
if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
com_events -= (com->iptr - com->ibuf);
com->iptr = com->ibuf;
return;
}
if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
/*
* Avoid the grotesquely inefficient lineswitch routine
* (ttyinput) in "raw" mode. It usually takes about 450
* instructions (that's without canonical processing or echo!).
* slinput is reasonably fast (usually 40 instructions plus
* call overhead).
*/
do {
enable_intr();
incc = com->iptr - buf;
if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
&& (com->state & CS_RTS_IFLOW
|| tp->t_iflag & IXOFF)
&& !(tp->t_state & TS_TBLOCK))
ttyblock(tp);
com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
+= b_to_q((char *)buf, incc, &tp->t_rawq);
buf += incc;
tk_nin += incc;
tk_rawcc += incc;
tp->t_rawcc += incc;
ttwakeup(tp);
if (tp->t_state & TS_TTSTOP
&& (tp->t_iflag & IXANY
|| tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
tp->t_state &= ~TS_TTSTOP;
tp->t_lflag &= ~FLUSHO;
comstart(tp);
}
disable_intr();
} while (buf < com->iptr);
} else {
do {
enable_intr();
line_status = buf[com->ierroff];
recv_data = *buf++;
if (line_status
& (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
if (line_status & LSR_BI)
recv_data |= TTY_BI;
if (line_status & LSR_FE)
recv_data |= TTY_FE;
if (line_status & LSR_OE)
recv_data |= TTY_OE;
if (line_status & LSR_PE)
recv_data |= TTY_PE;
}
(*linesw[tp->t_line].l_rint)(recv_data, tp);
disable_intr();
} while (buf < com->iptr);
}
com_events -= (com->iptr - com->ibuf);
com->iptr = com->ibuf;
/*
* There is now room for another low-level buffer full of input,
* so enable RTS if it is now disabled and there is room in the
* high-level buffer.
*/
#ifdef PC98
if (IS_8251(com->pc98_if_type))
tmp = com_tiocm_get(com) & TIOCM_RTS;
else
tmp = com->mcr_image & MCR_RTS;
if ((com->state & CS_RTS_IFLOW) && !(tmp) &&
!(tp->t_state & TS_TBLOCK))
if (IS_8251(com->pc98_if_type))
com_tiocm_bis(com, TIOCM_RTS);
else
outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
#else
if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
!(tp->t_state & TS_TBLOCK))
outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
#endif
}
void
siointr(arg)
void *arg;
{
#ifndef COM_MULTIPORT
COM_LOCK();
siointr1((struct com_s *) arg);
COM_UNLOCK();
#else /* COM_MULTIPORT */
bool_t possibly_more_intrs;
int unit;
struct com_s *com;
#ifdef PC98
u_char rsa_buf_status;
#endif
/*
* Loop until there is no activity on any port. This is necessary
* to get an interrupt edge more than to avoid another interrupt.
* If the IRQ signal is just an OR of the IRQ signals from several
* devices, then the edge from one may be lost because another is
* on.
*/
COM_LOCK();
do {
possibly_more_intrs = FALSE;
for (unit = 0; unit < NSIOTOT; ++unit) {
com = com_addr(unit);
/*
* XXX COM_LOCK();
* would it work here, or be counter-productive?
*/
#ifdef PC98
if (com != NULL
&& !com->gone
&& IS_8251(com->pc98_if_type)){
siointr1(com);
} else
#endif /* PC98 */
#ifdef PC98
if (com != NULL
&& !com->gone
&& com->pc98_if_type == COM_IF_RSA98III) {
rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
if ((rsa_buf_status & 0xc8)
|| !(rsa_buf_status & 0x01)) {
siointr1(com);
if(rsa_buf_status
!= (inb(com->rsabase + rsa_srr) & 0xc9))
possibly_more_intrs = TRUE;
}
} else
#endif
if (com != NULL
&& !com->gone
&& (inb(com->int_id_port) & IIR_IMASK)
!= IIR_NOPEND) {
siointr1(com);
possibly_more_intrs = TRUE;
}
/* XXX COM_UNLOCK(); */
}
} while (possibly_more_intrs);
COM_UNLOCK();
#endif /* COM_MULTIPORT */
}
static void
siointr1(com)
struct com_s *com;
{
u_char line_status;
u_char modem_status;
u_char *ioptr;
u_char recv_data;
u_char int_ctl;
u_char int_ctl_new;
struct timecounter *tc;
u_int count;
#ifdef PC98
u_char tmp=0;
u_char rsa_buf_status = 0;
int rsa_tx_fifo_size=0;
recv_data=0;
#endif /* PC98 */
int_ctl = inb(com->intr_ctl_port);
int_ctl_new = int_ctl;
while (!com->gone) {
#ifdef PC98
status_read:;
if (IS_8251(com->pc98_if_type)) {
tmp = inb(com->sts_port);
more_intr:
line_status = 0;
if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
if (tmp & STS8251_PE) line_status |= LSR_PE;
if (tmp & STS8251_OE) line_status |= LSR_OE;
if (tmp & STS8251_FE) line_status |= LSR_FE;
if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
} else {
#endif /* PC98 */
if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
modem_status = inb(com->modem_status_port);
if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
tc = timecounter;
count = tc->tc_get_timecount(tc);
pps_event(&com->pps, tc, count,
(modem_status & MSR_DCD) ?
PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
}
}
line_status = inb(com->line_status_port);
#ifdef PC98
}
if (com->pc98_if_type == COM_IF_RSA98III)
rsa_buf_status = inb(com->rsabase + rsa_srr);
#endif /* PC98 */
/* input event? (check first to help avoid overruns) */
#ifndef PC98
while (line_status & LSR_RCV_MASK) {
#else
while ((line_status & LSR_RCV_MASK)
|| (com->pc98_if_type == COM_IF_RSA98III
&& (rsa_buf_status & 0x08))) {
#endif /* PC98 */
/* break/unnattached error bits or real input? */
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
recv_data = inb(com->data_port);
if (tmp & 0x78) {
pc98_i8251_or_cmd(com,CMD8251_ER);
recv_data = 0;
}
} else {
#endif /* PC98 */
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
if (!(rsa_buf_status & 0x08))
recv_data = 0;
else {
recv_data = inb(com->data_port);
}
} else
#endif
if (!(line_status & LSR_RXRDY))
recv_data = 0;
else
recv_data = inb(com->data_port);
#ifdef PC98
}
#endif
if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
/*
* Don't store BI if IGNBRK or FE/PE if IGNPAR.
* Otherwise, push the work to a higher level
* (to handle PARMRK) if we're bypassing.
* Otherwise, convert BI/FE and PE+INPCK to 0.
*
* This makes bypassing work right in the
* usual "raw" case (IGNBRK set, and IGNPAR
* and INPCK clear).
*
* Note: BI together with FE/PE means just BI.
*/
if (line_status & LSR_BI) {
#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
if (com->unit == comconsole) {
breakpoint();
goto cont;
}
#endif
if (com->tp == NULL
|| com->tp->t_iflag & IGNBRK)
goto cont;
} else {
if (com->tp == NULL
|| com->tp->t_iflag & IGNPAR)
goto cont;
}
if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
&& (line_status & (LSR_BI | LSR_FE)
|| com->tp->t_iflag & INPCK))
recv_data = 0;
}
++com->bytes_in;
if (com->hotchar != 0 && recv_data == com->hotchar)
setsofttty();
ioptr = com->iptr;
if (ioptr >= com->ibufend)
CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
else {
if (com->do_timestamp)
microtime(&com->timestamp);
++com_events;
schedsofttty();
#if 0 /* for testing input latency vs efficiency */
if (com->iptr - com->ibuf == 8)
setsofttty();
#endif
ioptr[0] = recv_data;
ioptr[com->ierroff] = line_status;
com->iptr = ++ioptr;
if (ioptr == com->ihighwater
&& com->state & CS_RTS_IFLOW)
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_tiocm_bic(com, TIOCM_RTS);
else
#endif
outb(com->modem_ctl_port,
com->mcr_image &= ~MCR_RTS);
if (line_status & LSR_OE)
CE_RECORD(com, CE_OVERRUN);
}
cont:
/*
* "& 0x7F" is to avoid the gcc-1.40 generating a slow
* jump from the top of the loop to here
*/
#ifdef PC98
if (IS_8251(com->pc98_if_type))
goto status_read;
else
#endif
line_status = inb(com->line_status_port) & 0x7F;
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III)
rsa_buf_status = inb(com->rsabase + rsa_srr);
#endif /* PC98 */
}
/* modem status change? (always check before doing output) */
#ifdef PC98
if (!IS_8251(com->pc98_if_type)) {
#endif
modem_status = inb(com->modem_status_port);
if (modem_status != com->last_modem_status) {
if (com->do_dcd_timestamp
&& !(com->last_modem_status & MSR_DCD)
&& modem_status & MSR_DCD)
microtime(&com->dcd_timestamp);
/*
* Schedule high level to handle DCD changes. Note
* that we don't use the delta bits anywhere. Some
* UARTs mess them up, and it's easy to remember the
* previous bits and calculate the delta.
*/
com->last_modem_status = modem_status;
if (!(com->state & CS_CHECKMSR)) {
com_events += LOTS_OF_EVENTS;
com->state |= CS_CHECKMSR;
setsofttty();
}
/* handle CTS change immediately for crisp flow ctl */
if (com->state & CS_CTS_OFLOW) {
if (modem_status & MSR_CTS)
com->state |= CS_ODEVREADY;
else
com->state &= ~CS_ODEVREADY;
}
}
#ifdef PC98
}
#endif
/* output queued and everything ready? */
#ifndef PC98
if (line_status & LSR_TXRDY
&& com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
#else
if (((com->pc98_if_type == COM_IF_RSA98III)
? (rsa_buf_status & 0x02)
: (line_status & LSR_TXRDY))
&& com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
#endif
ioptr = com->obufq.l_head;
if (com->tx_fifo_size > 1) {
u_int ocount;
ocount = com->obufq.l_tail - ioptr;
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
rsa_buf_status = inb(com->rsabase + rsa_srr);
rsa_tx_fifo_size = 1024;
if (!(rsa_buf_status & 0x01))
rsa_tx_fifo_size = 2048;
if (ocount > rsa_tx_fifo_size)
ocount = rsa_tx_fifo_size;
} else
#endif
if (ocount > com->tx_fifo_size)
ocount = com->tx_fifo_size;
com->bytes_out += ocount;
do
outb(com->data_port, *ioptr++);
while (--ocount != 0);
} else {
outb(com->data_port, *ioptr++);
++com->bytes_out;
}
#ifdef PC98
if (IS_8251(com->pc98_if_type))
if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
com_int_Tx_enable(com);
#endif
com->obufq.l_head = ioptr;
if (COM_IIR_TXRDYBUG(com->flags)) {
int_ctl_new = int_ctl | IER_ETXRDY;
}
if (ioptr >= com->obufq.l_tail) {
struct lbq *qp;
qp = com->obufq.l_next;
qp->l_queued = FALSE;
qp = qp->l_next;
if (qp != NULL) {
com->obufq.l_head = qp->l_head;
com->obufq.l_tail = qp->l_tail;
com->obufq.l_next = qp;
} else {
/* output just completed */
if ( COM_IIR_TXRDYBUG(com->flags) ) {
int_ctl_new = int_ctl & ~IER_ETXRDY;
}
com->state &= ~CS_BUSY;
#if defined(PC98)
if (IS_8251(com->pc98_if_type))
if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
com_int_Tx_disable(com);
#endif
}
if (!(com->state & CS_ODONE)) {
com_events += LOTS_OF_EVENTS;
com->state |= CS_ODONE;
setsofttty(); /* handle at high level ASAP */
}
}
if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
outb(com->intr_ctl_port, int_ctl_new);
outb(com->rsabase + rsa_ier, 0x1d);
} else
#endif
outb(com->intr_ctl_port, int_ctl_new);
}
}
#ifdef PC98
else if (line_status & LSR_TXRDY) {
if (IS_8251(com->pc98_if_type))
if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
com_int_Tx_disable(com);
}
if (IS_8251(com->pc98_if_type))
if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
goto more_intr;
#endif
/* finished? */
#ifndef COM_MULTIPORT
#ifdef PC98
if (IS_8251(com->pc98_if_type))
return;
#endif
if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
#endif /* COM_MULTIPORT */
return;
}
}
static int
sioioctl(dev, cmd, data, flag, p)
dev_t dev;
u_long cmd;
caddr_t data;
int flag;
struct proc *p;
{
struct com_s *com;
int error;
Port_t iobase;
int mynor;
int s;
struct tty *tp;
#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
u_long oldcmd;
struct termios term;
#endif
mynor = minor(dev);
com = com_addr(MINOR_TO_UNIT(mynor));
if (com->gone)
return (ENODEV);
iobase = com->iobase;
if (mynor & CONTROL_MASK) {
struct termios *ct;
switch (mynor & CONTROL_MASK) {
case CONTROL_INIT_STATE:
ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
break;
case CONTROL_LOCK_STATE:
ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
break;
default:
return (ENODEV); /* /dev/nodev */
}
switch (cmd) {
case TIOCSETA:
error = suser(p);
if (error != 0)
return (error);
*ct = *(struct termios *)data;
return (0);
case TIOCGETA:
*(struct termios *)data = *ct;
return (0);
case TIOCGETD:
*(int *)data = TTYDISC;
return (0);
case TIOCGWINSZ:
bzero(data, sizeof(struct winsize));
return (0);
default:
return (ENOTTY);
}
}
tp = com->tp;
#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
term = tp->t_termios;
oldcmd = cmd;
error = ttsetcompat(tp, &cmd, data, &term);
if (error != 0)
return (error);
if (cmd != oldcmd)
data = (caddr_t)&term;
#endif
if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
int cc;
struct termios *dt = (struct termios *)data;
struct termios *lt = mynor & CALLOUT_MASK
? &com->lt_out : &com->lt_in;
dt->c_iflag = (tp->t_iflag & lt->c_iflag)
| (dt->c_iflag & ~lt->c_iflag);
dt->c_oflag = (tp->t_oflag & lt->c_oflag)
| (dt->c_oflag & ~lt->c_oflag);
dt->c_cflag = (tp->t_cflag & lt->c_cflag)
| (dt->c_cflag & ~lt->c_cflag);
dt->c_lflag = (tp->t_lflag & lt->c_lflag)
| (dt->c_lflag & ~lt->c_lflag);
for (cc = 0; cc < NCCS; ++cc)
if (lt->c_cc[cc] != 0)
dt->c_cc[cc] = tp->t_cc[cc];
if (lt->c_ispeed != 0)
dt->c_ispeed = tp->t_ispeed;
if (lt->c_ospeed != 0)
dt->c_ospeed = tp->t_ospeed;
}
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
if (error != ENOIOCTL)
return (error);
s = spltty();
error = ttioctl(tp, cmd, data, flag);
disc_optim(tp, &tp->t_termios, com);
if (error != ENOIOCTL) {
splx(s);
return (error);
}
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
switch (cmd) {
case TIOCSBRK:
com_send_break_on( com );
break;
case TIOCCBRK:
com_send_break_off( com );
break;
case TIOCSDTR:
com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
break;
case TIOCCDTR:
com_tiocm_bic(com, TIOCM_DTR);
break;
/*
* XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
* changes get undone on the next call to comparam().
*/
case TIOCMSET:
com_tiocm_set( com, *(int *)data );
break;
case TIOCMBIS:
com_tiocm_bis( com, *(int *)data );
break;
case TIOCMBIC:
com_tiocm_bic( com, *(int *)data );
break;
case TIOCMGET:
*(int *)data = com_tiocm_get(com);
break;
case TIOCMSDTRWAIT:
/* must be root since the wait applies to following logins */
error = suser(p);
if (error != 0) {
splx(s);
return (error);
}
com->dtr_wait = *(int *)data * hz / 100;
break;
case TIOCMGDTRWAIT:
*(int *)data = com->dtr_wait * 100 / hz;
break;
case TIOCTIMESTAMP:
com->do_timestamp = TRUE;
*(struct timeval *)data = com->timestamp;
break;
case TIOCDCDTIMESTAMP:
com->do_dcd_timestamp = TRUE;
*(struct timeval *)data = com->dcd_timestamp;
break;
default:
splx(s);
return (ENOTTY);
}
} else {
int port_shift;
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
#endif
switch (cmd) {
case TIOCSBRK:
#ifdef PC98
outb(iobase + (com_cfcr << port_shift),
com->cfcr_image |= CFCR_SBREAK);
#else
outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
#endif
break;
case TIOCCBRK:
#ifdef PC98
outb(iobase + (com_cfcr << port_shift),
com->cfcr_image &= ~CFCR_SBREAK);
#else
outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
#endif
break;
case TIOCSDTR:
(void)commctl(com, TIOCM_DTR, DMBIS);
break;
case TIOCCDTR:
(void)commctl(com, TIOCM_DTR, DMBIC);
break;
/*
* XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
* changes get undone on the next call to comparam().
*/
case TIOCMSET:
(void)commctl(com, *(int *)data, DMSET);
break;
case TIOCMBIS:
(void)commctl(com, *(int *)data, DMBIS);
break;
case TIOCMBIC:
(void)commctl(com, *(int *)data, DMBIC);
break;
case TIOCMGET:
*(int *)data = commctl(com, 0, DMGET);
break;
case TIOCMSDTRWAIT:
/* must be root since the wait applies to following logins */
error = suser(p);
if (error != 0) {
splx(s);
return (error);
}
com->dtr_wait = *(int *)data * hz / 100;
break;
case TIOCMGDTRWAIT:
*(int *)data = com->dtr_wait * 100 / hz;
break;
case TIOCTIMESTAMP:
com->do_timestamp = TRUE;
*(struct timeval *)data = com->timestamp;
break;
case TIOCDCDTIMESTAMP:
com->do_dcd_timestamp = TRUE;
*(struct timeval *)data = com->dcd_timestamp;
break;
default:
splx(s);
error = pps_ioctl(cmd, data, &com->pps);
if (error == ENODEV)
error = ENOTTY;
return (error);
}
#ifdef PC98
}
#endif
splx(s);
return (0);
}
static void
siopoll()
{
int unit;
if (com_events == 0)
return;
repeat:
for (unit = 0; unit < NSIOTOT; ++unit) {
struct com_s *com;
int incc;
struct tty *tp;
com = com_addr(unit);
if (com == NULL)
continue;
tp = com->tp;
if (tp == NULL || com->gone) {
/*
* Discard any events related to never-opened or
* going-away devices.
*/
disable_intr();
incc = com->iptr - com->ibuf;
com->iptr = com->ibuf;
if (com->state & CS_CHECKMSR) {
incc += LOTS_OF_EVENTS;
com->state &= ~CS_CHECKMSR;
}
com_events -= incc;
enable_intr();
continue;
}
if (com->iptr != com->ibuf) {
disable_intr();
sioinput(com);
enable_intr();
}
if (com->state & CS_CHECKMSR) {
u_char delta_modem_status;
#ifdef PC98
if (!IS_8251(com->pc98_if_type)) {
#endif
disable_intr();
delta_modem_status = com->last_modem_status
^ com->prev_modem_status;
com->prev_modem_status = com->last_modem_status;
com_events -= LOTS_OF_EVENTS;
com->state &= ~CS_CHECKMSR;
enable_intr();
if (delta_modem_status & MSR_DCD)
(*linesw[tp->t_line].l_modem)
(tp, com->prev_modem_status & MSR_DCD);
#ifdef PC98
}
#endif
}
if (com->state & CS_ODONE) {
disable_intr();
com_events -= LOTS_OF_EVENTS;
com->state &= ~CS_ODONE;
enable_intr();
if (!(com->state & CS_BUSY)
&& !(com->extra_state & CSE_BUSYCHECK)) {
timeout(siobusycheck, com, hz / 100);
com->extra_state |= CSE_BUSYCHECK;
}
(*linesw[tp->t_line].l_start)(tp);
}
if (com_events == 0)
break;
}
if (com_events >= LOTS_OF_EVENTS)
goto repeat;
}
static int
comparam(tp, t)
struct tty *tp;
struct termios *t;
{
u_int cfcr;
int cflag;
struct com_s *com;
int divisor;
u_char dlbh;
u_char dlbl;
Port_t iobase;
int s;
int unit;
#ifdef PC98
int port_shift = 0;
u_char param = 0;
#endif
#ifdef PC98
cfcr = 0;
unit = DEV_TO_UNIT(tp->t_dev);
com = com_addr(unit);
iobase = com->iobase;
if (IS_8251(com->pc98_if_type)) {
divisor = pc98_ttspeedtab(com, t->c_ospeed);
} else {
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
/* do historical conversions */
if (t->c_ispeed == 0)
t->c_ispeed = t->c_ospeed;
/* check requested parameters */
divisor = ttspeedtab(t->c_ospeed,
if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
}
#else
/* do historical conversions */
if (t->c_ispeed == 0)
t->c_ispeed = t->c_ospeed;
/* check requested parameters */
divisor = ttspeedtab(t->c_ospeed, comspeedtab);
#endif
if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
return (EINVAL);
/* parameters are OK, convert them to the com struct and the device */
#ifndef PC98
unit = DEV_TO_UNIT(tp->t_dev);
com = com_addr(unit);
iobase = com->iobase;
#endif
s = spltty();
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
if (divisor == 0)
com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
else
com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
} else {
#endif
if (divisor == 0)
(void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
else
(void)commctl(com, TIOCM_DTR, DMBIS);
#ifdef PC98
}
#endif
cflag = t->c_cflag;
#ifdef PC98
if (!IS_8251(com->pc98_if_type)) {
#endif
switch (cflag & CSIZE) {
case CS5:
cfcr = CFCR_5BITS;
break;
case CS6:
cfcr = CFCR_6BITS;
break;
case CS7:
cfcr = CFCR_7BITS;
break;
default:
cfcr = CFCR_8BITS;
break;
}
if (cflag & PARENB) {
cfcr |= CFCR_PENAB;
if (!(cflag & PARODD))
cfcr |= CFCR_PEVEN;
}
if (cflag & CSTOPB)
cfcr |= CFCR_STOPB;
if (com->hasfifo && divisor != 0) {
/*
* Use a fifo trigger level low enough so that the input
* latency from the fifo is less than about 16 msec and
* the total latency is less than about 30 msec. These
* latencies are reasonable for humans. Serial comms
* protocols shouldn't expect anything better since modem
* latencies are larger.
*/
com->fifo_image = t->c_ospeed <= 4800
? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
#ifdef COM_ESP
/*
* The Hayes ESP card needs the fifo DMA mode bit set
* in compatibility mode. If not, it will interrupt
* for each character received.
*/
if (com->esp)
com->fifo_image |= FIFO_DMA_MODE;
#endif
#ifdef PC98
outb(iobase + (com_fifo << port_shift), com->fifo_image);
#else
outb(iobase + com_fifo, com->fifo_image);
#endif
}
#ifdef PC98
}
#endif
/*
* This returns with interrupts disabled so that we can complete
* the speed change atomically. Keeping interrupts disabled is
* especially important while com_data is hidden.
*/
(void) siosetwater(com, t->c_ispeed);
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_cflag_and_speed_set(com, cflag, t->c_ospeed);
else {
#endif
if (divisor != 0) {
#ifdef PC98
outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
#else
outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
#endif
/*
* Only set the divisor registers if they would change,
* since on some 16550 incompatibles (UMC8669F), setting
* them while input is arriving them loses sync until
* data stops arriving.
*/
dlbl = divisor & 0xFF;
#ifdef PC98
if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
outb(iobase + (com_dlbl << port_shift), dlbl);
dlbh = (u_int) divisor >> 8;
if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
outb(iobase + (com_dlbh << port_shift), dlbh);
#else
if (inb(iobase + com_dlbl) != dlbl)
outb(iobase + com_dlbl, dlbl);
dlbh = (u_int) divisor >> 8;
if (inb(iobase + com_dlbh) != dlbh)
outb(iobase + com_dlbh, dlbh);
#endif
}
#ifdef PC98
}
outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
#else
outb(iobase + com_cfcr, com->cfcr_image = cfcr);
#endif
if (!(tp->t_state & TS_TTSTOP))
com->state |= CS_TTGO;
if (cflag & CRTS_IFLOW) {
if (com->st16650a) {
outb(iobase + com_cfcr, 0xbf);
outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
}
com->state |= CS_RTS_IFLOW;
/*
* If CS_RTS_IFLOW just changed from off to on, the change
* needs to be propagated to MCR_RTS. This isn't urgent,
* so do it later by calling comstart() instead of repeating
* a lot of code from comstart() here.
*/
} else if (com->state & CS_RTS_IFLOW) {
com->state &= ~CS_RTS_IFLOW;
/*
* CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
* on here, since comstart() won't do it later.
*/
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_tiocm_bis(com, TIOCM_RTS);
else
#endif
outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
if (com->st16650a) {
outb(iobase + com_cfcr, 0xbf);
outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
}
}
/*
* Set up state to handle output flow control.
* XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
* Now has 10+ msec latency, while CTS flow has 50- usec latency.
*/
com->state |= CS_ODEVREADY;
com->state &= ~CS_CTS_OFLOW;
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
param = inb(com->rsabase + rsa_msr);
outb(com->rsabase + rsa_msr, param & 0x14);
}
#endif
if (cflag & CCTS_OFLOW) {
com->state |= CS_CTS_OFLOW;
#ifdef PC98
if (IS_8251(com->pc98_if_type)) {
if (!(pc98_get_modem_status(com) & TIOCM_CTS))
com->state &= ~CS_ODEVREADY;
} else {
#endif
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
/* Set automatic flow control mode */
outb(com->rsabase + rsa_msr, param | 0x08);
} else
#endif
if (!(com->last_modem_status & MSR_CTS))
com->state &= ~CS_ODEVREADY;
if (com->st16650a) {
outb(iobase + com_cfcr, 0xbf);
outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
}
#ifdef PC98
}
#endif
} else {
if (com->st16650a) {
outb(iobase + com_cfcr, 0xbf);
outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
}
}
#ifdef PC98
outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
#else
outb(iobase + com_cfcr, com->cfcr_image);
#endif
/* XXX shouldn't call functions while intrs are disabled. */
disc_optim(tp, t, com);
/*
* Recover from fiddling with CS_TTGO. We used to call siointr1()
* unconditionally, but that defeated the careful discarding of
* stale input in sioopen().
*/
if (com->state >= (CS_BUSY | CS_TTGO))
siointr1(com);
enable_intr();
splx(s);
comstart(tp);
if (com->ibufold != NULL) {
free(com->ibufold, M_DEVBUF);
com->ibufold = NULL;
}
return (0);
}
static int
siosetwater(com, speed)
struct com_s *com;
speed_t speed;
{
int cp4ticks;
u_char *ibuf;
int ibufsize;
struct tty *tp;
/*
* Make the buffer size large enough to handle a softtty interrupt
* latency of about 2 ticks without loss of throughput or data
* (about 3 ticks if input flow control is not used or not honoured,
* but a bit less for CS5-CS7 modes).
*/
cp4ticks = speed / 10 / hz * 4;
for (ibufsize = 128; ibufsize < cp4ticks;)
ibufsize <<= 1;
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III)
ibufsize = 2048;
#endif
if (ibufsize == com->ibufsize) {
disable_intr();
return (0);
}
/*
* Allocate input buffer. The extra factor of 2 in the size is
* to allow for an error byte for each input byte.
*/
ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
if (ibuf == NULL) {
disable_intr();
return (ENOMEM);
}
/* Initialize non-critical variables. */
com->ibufold = com->ibuf;
com->ibufsize = ibufsize;
tp = com->tp;
if (tp != NULL) {
tp->t_ififosize = 2 * ibufsize;
tp->t_ispeedwat = (speed_t)-1;
tp->t_ospeedwat = (speed_t)-1;
}
/*
* Read current input buffer, if any. Continue with interrupts
* disabled.
*/
disable_intr();
if (com->iptr != com->ibuf)
sioinput(com);
/*-
* Initialize critical variables, including input buffer watermarks.
* The external device is asked to stop sending when the buffer
* exactly reaches high water, or when the high level requests it.
* The high level is notified immediately (rather than at a later
* clock tick) when this watermark is reached.
* The buffer size is chosen so the watermark should almost never
* be reached.
* The low watermark is invisibly 0 since the buffer is always
* emptied all at once.
*/
com->iptr = com->ibuf = ibuf;
com->ibufend = ibuf + ibufsize;
com->ierroff = ibufsize;
com->ihighwater = ibuf + 3 * ibufsize / 4;
return (0);
}
static void
comstart(tp)
struct tty *tp;
{
struct com_s *com;
int s;
int unit;
#ifdef PC98
int tmp;
#endif
unit = DEV_TO_UNIT(tp->t_dev);
com = com_addr(unit);
s = spltty();
disable_intr();
if (tp->t_state & TS_TTSTOP)
com->state &= ~CS_TTGO;
else
com->state |= CS_TTGO;
if (tp->t_state & TS_TBLOCK) {
#ifdef PC98
if (IS_8251(com->pc98_if_type))
tmp = com_tiocm_get(com) & TIOCM_RTS;
else
tmp = com->mcr_image & MCR_RTS;
if (tmp && (com->state & CS_RTS_IFLOW))
#else
if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
#endif
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_tiocm_bic(com, TIOCM_RTS);
else
#endif
outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
} else {
#ifdef PC98
if (IS_8251(com->pc98_if_type))
tmp = com_tiocm_get(com) & TIOCM_RTS;
else
tmp = com->mcr_image & MCR_RTS;
if (!(tmp) && com->iptr < com->ihighwater
&& com->state & CS_RTS_IFLOW)
#else
if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
&& com->state & CS_RTS_IFLOW)
#endif
#ifdef PC98
if (IS_8251(com->pc98_if_type))
com_tiocm_bis(com, TIOCM_RTS);
else
#endif
outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
}
enable_intr();
if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
ttwwakeup(tp);
#ifdef PC98
/* if(IS_8251(com->pc98_if_type))
com_int_Tx_enable(com); */
#endif
splx(s);
return;
}
if (tp->t_outq.c_cc != 0) {
struct lbq *qp;
struct lbq *next;
if (!com->obufs[0].l_queued) {
com->obufs[0].l_tail
= com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
#ifndef PC98
sizeof com->obuf1);
#else
com->obufsize);
#endif
com->obufs[0].l_next = NULL;
com->obufs[0].l_queued = TRUE;
disable_intr();
if (com->state & CS_BUSY) {
qp = com->obufq.l_next;
while ((next = qp->l_next) != NULL)
qp = next;
qp->l_next = &com->obufs[0];
} else {
com->obufq.l_head = com->obufs[0].l_head;
com->obufq.l_tail = com->obufs[0].l_tail;
com->obufq.l_next = &com->obufs[0];
com->state |= CS_BUSY;
}
enable_intr();
}
if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
com->obufs[1].l_tail
= com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
#ifndef PC98
sizeof com->obuf2);
#else
com->obufsize);
#endif
com->obufs[1].l_next = NULL;
com->obufs[1].l_queued = TRUE;
disable_intr();
if (com->state & CS_BUSY) {
qp = com->obufq.l_next;
while ((next = qp->l_next) != NULL)
qp = next;
qp->l_next = &com->obufs[1];
} else {
com->obufq.l_head = com->obufs[1].l_head;
com->obufq.l_tail = com->obufs[1].l_tail;
com->obufq.l_next = &com->obufs[1];
com->state |= CS_BUSY;
}
enable_intr();
}
tp->t_state |= TS_BUSY;
}
disable_intr();
if (com->state >= (CS_BUSY | CS_TTGO))
siointr1(com); /* fake interrupt to start output */
enable_intr();
#ifdef PC98
/* if(IS_8251(com->pc98_if_type))
com_int_Tx_enable(com); */
#endif
ttwwakeup(tp);
splx(s);
}
static void
siostop(tp, rw)
struct tty *tp;
int rw;
{
struct com_s *com;
#ifdef PC98
int port_shift = 0;
int rsa98_tmp = 0;
#endif
com = com_addr(DEV_TO_UNIT(tp->t_dev));
if (com->gone)
return;
#ifdef PC98
if (IS_8251(com->pc98_if_type))
port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
#endif
disable_intr();
if (rw & FWRITE) {
if (com->hasfifo)
#ifdef COM_ESP
/* XXX avoid h/w bug. */
if (!com->esp)
#endif
#ifdef PC98
outb(com->iobase + (com_fifo << port_shift),
FIFO_XMT_RST | com->fifo_image);
if (com->pc98_if_type == COM_IF_RSA98III)
for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
outb(com->iobase + (com_fifo << port_shift),
FIFO_XMT_RST | com->fifo_image);
#else
outb(com->iobase + com_fifo,
FIFO_XMT_RST | com->fifo_image);
#endif
com->obufs[0].l_queued = FALSE;
com->obufs[1].l_queued = FALSE;
if (com->state & CS_ODONE)
com_events -= LOTS_OF_EVENTS;
com->state &= ~(CS_ODONE | CS_BUSY);
com->tp->t_state &= ~TS_BUSY;
}
if (rw & FREAD) {
if (com->hasfifo)
#ifdef COM_ESP
/* XXX avoid h/w bug. */
if (!com->esp)
#endif
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III) {
for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
inb(com->data_port);
}
outb(com->iobase + (com_fifo << port_shift),
FIFO_RCV_RST | com->fifo_image);
#else
outb(com->iobase + com_fifo,
FIFO_RCV_RST | com->fifo_image);
#endif
com_events -= (com->iptr - com->ibuf);
com->iptr = com->ibuf;
}
enable_intr();
comstart(tp);
}
static struct tty *
siodevtotty(dev)
dev_t dev;
{
int mynor;
int unit;
mynor = minor(dev);
if (mynor & CONTROL_MASK)
return (NULL);
unit = MINOR_TO_UNIT(mynor);
if ((u_int) unit >= NSIOTOT)
return (NULL);
return (&sio_tty[unit]);
}
static int
commctl(com, bits, how)
struct com_s *com;
int bits;
int how;
{
int mcr;
int msr;
if (how == DMGET) {
bits = TIOCM_LE; /* XXX - always enabled while open */
mcr = com->mcr_image;
if (mcr & MCR_DTR)
bits |= TIOCM_DTR;
if (mcr & MCR_RTS)
bits |= TIOCM_RTS;
msr = com->prev_modem_status;
if (msr & MSR_CTS)
bits |= TIOCM_CTS;
if (msr & MSR_DCD)
bits |= TIOCM_CD;
if (msr & MSR_DSR)
bits |= TIOCM_DSR;
/*
* XXX - MSR_RI is naturally volatile, and we make MSR_TERI
* more volatile by reading the modem status a lot. Perhaps
* we should latch both bits until the status is read here.
*/
if (msr & (MSR_RI | MSR_TERI))
bits |= TIOCM_RI;
return (bits);
}
mcr = 0;
if (bits & TIOCM_DTR)
mcr |= MCR_DTR;
if (bits & TIOCM_RTS)
mcr |= MCR_RTS;
if (com->gone)
return(0);
disable_intr();
switch (how) {
case DMSET:
outb(com->modem_ctl_port,
com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
break;
case DMBIS:
outb(com->modem_ctl_port, com->mcr_image |= mcr);
break;
case DMBIC:
outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
break;
}
enable_intr();
return (0);
}
static void
siosettimeout()
{
struct com_s *com;
bool_t someopen;
int unit;
/*
* Set our timeout period to 1 second if no polled devices are open.
* Otherwise set it to max(1/200, 1/hz).
* Enable timeouts iff some device is open.
*/
untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
sio_timeout = hz;
someopen = FALSE;
for (unit = 0; unit < NSIOTOT; ++unit) {
com = com_addr(unit);
if (com != NULL && com->tp != NULL
&& com->tp->t_state & TS_ISOPEN && !com->gone) {
someopen = TRUE;
if (com->poll || com->poll_output) {
sio_timeout = hz > 200 ? hz / 200 : 1;
break;
}
}
}
if (someopen) {
sio_timeouts_until_log = hz / sio_timeout;
sio_timeout_handle = timeout(comwakeup, (void *)NULL,
sio_timeout);
} else {
/* Flush error messages, if any. */
sio_timeouts_until_log = 1;
comwakeup((void *)NULL);
untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
}
}
static void
comwakeup(chan)
void *chan;
{
struct com_s *com;
int unit;
sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
/*
* Recover from lost output interrupts.
* Poll any lines that don't use interrupts.
*/
for (unit = 0; unit < NSIOTOT; ++unit) {
com = com_addr(unit);
if (com != NULL && !com->gone
&& (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
disable_intr();
siointr1(com);
enable_intr();
}
}
/*
* Check for and log errors, but not too often.
*/
if (--sio_timeouts_until_log > 0)
return;
sio_timeouts_until_log = hz / sio_timeout;
for (unit = 0; unit < NSIOTOT; ++unit) {
int errnum;
com = com_addr(unit);
if (com == NULL)
continue;
if (com->gone)
continue;
for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
u_int delta;
u_long total;
disable_intr();
delta = com->delta_error_counts[errnum];
com->delta_error_counts[errnum] = 0;
enable_intr();
if (delta == 0)
continue;
total = com->error_counts[errnum] += delta;
log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
unit, delta, error_desc[errnum],
delta == 1 ? "" : "s", total);
}
}
}
#ifdef PC98
/* commint is called when modem control line changes */
static void
commint(dev_t dev)
{
register struct tty *tp;
int stat,delta;
struct com_s *com;
int mynor,unit;
mynor = minor(dev);
unit = MINOR_TO_UNIT(mynor);
com = com_addr(unit);
tp = com->tp;
stat = com_tiocm_get(com);
delta = com_tiocm_get_delta(com);
if (com->state & CS_CTS_OFLOW) {
if (stat & TIOCM_CTS)
com->state |= CS_ODEVREADY;
else
com->state &= ~CS_ODEVREADY;
}
if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
if (stat & TIOCM_CAR )
(void)(*linesw[tp->t_line].l_modem)(tp, 1);
else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
/* negate DTR, RTS */
com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
/* disable IENABLE */
com_int_TxRx_disable( com );
}
}
}
#endif
static void
disc_optim(tp, t, com)
struct tty *tp;
struct termios *t;
struct com_s *com;
{
if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
&& (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
&& (!(t->c_iflag & PARMRK)
|| (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
&& !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
&& linesw[tp->t_line].l_rint == ttyinput)
tp->t_state |= TS_CAN_BYPASS_L_RINT;
else
tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
com->hotchar = linesw[tp->t_line].l_hotchar;
}
/*
* Following are all routines needed for SIO to act as console
*/
#include <machine/cons.h>
struct siocnstate {
u_char dlbl;
u_char dlbh;
u_char ier;
u_char cfcr;
u_char mcr;
};
static speed_t siocngetspeed __P((Port_t, struct speedtab *));
static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
static void siocntxwait __P((Port_t iobase));
#ifdef __i386__
static cn_probe_t siocnprobe;
static cn_init_t siocninit;
static cn_checkc_t siocncheckc;
static cn_getc_t siocngetc;
static cn_putc_t siocnputc;
CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
/* To get the GDB related variables */
#if DDB > 0
#include <ddb/ddb.h>
#endif
#endif
static void
siocntxwait(iobase)
Port_t iobase;
{
int timo;
/*
* Wait for any pending transmission to finish. Required to avoid
* the UART lockup bug when the speed is changed, and for normal
* transmits.
*/
timo = 100000;
while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
!= (LSR_TSRE | LSR_TXRDY) && --timo != 0)
;
}
/*
* Read the serial port specified and try to figure out what speed
* it's currently running at. We're assuming the serial port has
* been initialized and is basicly idle. This routine is only intended
* to be run at system startup.
*
* If the value read from the serial port doesn't make sense, return 0.
*/
static speed_t
siocngetspeed(iobase, table)
Port_t iobase;
struct speedtab *table;
{
int code;
u_char dlbh;
u_char dlbl;
u_char cfcr;
cfcr = inb(iobase + com_cfcr);
outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
dlbl = inb(iobase + com_dlbl);
dlbh = inb(iobase + com_dlbh);
outb(iobase + com_cfcr, cfcr);
code = dlbh << 8 | dlbl;
for ( ; table->sp_speed != -1; table++)
if (table->sp_code == code)
return (table->sp_speed);
return 0; /* didn't match anything sane */
}
static void
siocnopen(sp, iobase, speed)
struct siocnstate *sp;
Port_t iobase;
int speed;
{
int divisor;
u_char dlbh;
u_char dlbl;
/*
* Save all the device control registers except the fifo register
* and set our default ones (cs8 -parenb speed=comdefaultrate).
* We can't save the fifo register since it is read-only.
*/
sp->ier = inb(iobase + com_ier);
outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
siocntxwait(iobase);
sp->cfcr = inb(iobase + com_cfcr);
outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
sp->dlbl = inb(iobase + com_dlbl);
sp->dlbh = inb(iobase + com_dlbh);
/*
* Only set the divisor registers if they would change, since on
* some 16550 incompatibles (Startech), setting them clears the
* data input register. This also reduces the effects of the
* UMC8669F bug.
*/
divisor = ttspeedtab(speed, comspeedtab);
dlbl = divisor & 0xFF;
if (sp->dlbl != dlbl)
outb(iobase + com_dlbl, dlbl);
dlbh = (u_int) divisor >> 8;
if (sp->dlbh != dlbh)
outb(iobase + com_dlbh, dlbh);
outb(iobase + com_cfcr, CFCR_8BITS);
sp->mcr = inb(iobase + com_mcr);
/*
* We don't want interrupts, but must be careful not to "disable"
* them by clearing the MCR_IENABLE bit, since that might cause
* an interrupt by floating the IRQ line.
*/
outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
}
static void
siocnclose(sp, iobase)
struct siocnstate *sp;
Port_t iobase;
{
/*
* Restore the device control registers.
*/
siocntxwait(iobase);
outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
if (sp->dlbl != inb(iobase + com_dlbl))
outb(iobase + com_dlbl, sp->dlbl);
if (sp->dlbh != inb(iobase + com_dlbh))
outb(iobase + com_dlbh, sp->dlbh);
outb(iobase + com_cfcr, sp->cfcr);
/*
* XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
*/
outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
outb(iobase + com_ier, sp->ier);
}
#ifdef __i386__
static
#endif
void
siocnprobe(cp)
struct consdev *cp;
{
speed_t boot_speed;
u_char cfcr;
int s, unit;
struct siocnstate sp;
/*
* Find our first enabled console, if any. If it is a high-level
* console device, then initialize it and return successfully.
* If it is a low-level console device, then initialize it and
* return unsuccessfully. It must be initialized in both cases
* for early use by console drivers and debuggers. Initializing
* the hardware is not necessary in all cases, since the i/o
* routines initialize it on the fly, but it is necessary if
* input might arrive while the hardware is switched back to an
* uninitialized state. We can't handle multiple console devices
* yet because our low-level routines don't take a device arg.
* We trust the user to set the console flags properly so that we
* don't need to probe.
*/
cp->cn_pri = CN_DEAD;
for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
int flags;
if (resource_int_value("sio", unit, "flags", &flags))
continue;
if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
int port;
Port_t iobase;
if (resource_int_value("sio", unit, "port", &port))
continue;
iobase = port;
s = spltty();
if (boothowto & RB_SERIAL) {
boot_speed = siocngetspeed(iobase, comspeedtab);
if (boot_speed)
comdefaultrate = boot_speed;
}
/*
* Initialize the divisor latch. We can't rely on
* siocnopen() to do this the first time, since it
* avoids writing to the latch if the latch appears
* to have the correct value. Also, if we didn't
* just read the speed from the hardware, then we
* need to set the speed in hardware so that
* switching it later is null.
*/
cfcr = inb(iobase + com_cfcr);
outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
outb(iobase + com_dlbl,
COMBRD(comdefaultrate) & 0xff);
outb(iobase + com_dlbh,
(u_int) COMBRD(comdefaultrate) >> 8);
outb(iobase + com_cfcr, cfcr);
siocnopen(&sp, iobase, comdefaultrate);
splx(s);
if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
cp->cn_dev = makedev(CDEV_MAJOR, unit);
cp->cn_pri = COM_FORCECONSOLE(flags)
|| boothowto & RB_SERIAL
? CN_REMOTE : CN_NORMAL;
printf("sio%d: system console\n", unit);
siocniobase = iobase;
siocnunit = unit;
}
if (COM_DEBUGGER(flags) && !COM_LLCONSOLE(flags)) {
printf("sio%d: gdb debugging port\n", unit);
siogdbiobase = iobase;
siogdbunit = unit;
#ifdef __i386__
#if DDB > 0
gdbdev = makedev(CDEV_MAJOR, unit);
gdb_getc = siocngetc;
gdb_putc = siocnputc;
#endif
#endif
}
}
}
#ifdef __i386__
#if DDB > 0
/*
* XXX Ugly Compatability.
* If no gdb port has been specified, set it to be the console
* as some configuration files don't specify the gdb port.
*/
if (gdbdev == NODEV && (boothowto & RB_GDB)) {
printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
siocnunit);
printf("Set flag 0x80 on desired GDB port in your\n");
printf("configuration file (currently sio only).\n");
siogdbiobase = siocniobase;
siogdbunit = siocnunit;
gdbdev = makedev(CDEV_MAJOR, siocnunit);
gdb_getc = siocngetc;
gdb_putc = siocnputc;
}
#endif
#endif
}
#ifdef __alpha__
struct consdev siocons = {
NULL, NULL, siocngetc, siocncheckc, siocnputc,
NULL, 0, CN_NORMAL,
};
extern struct consdev *cn_tab;
int
siocnattach(port, speed)
int port;
int speed;
{
int s;
u_char cfcr;
struct siocnstate sp;
siocniobase = port;
comdefaultrate = speed;
s = spltty();
/*
* Initialize the divisor latch. We can't rely on
* siocnopen() to do this the first time, since it
* avoids writing to the latch if the latch appears
* to have the correct value. Also, if we didn't
* just read the speed from the hardware, then we
* need to set the speed in hardware so that
* switching it later is null.
*/
cfcr = inb(siocniobase + com_cfcr);
outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
outb(siocniobase + com_dlbl,
COMBRD(comdefaultrate) & 0xff);
outb(siocniobase + com_dlbh,
(u_int) COMBRD(comdefaultrate) >> 8);
outb(siocniobase + com_cfcr, cfcr);
siocnopen(&sp, siocniobase, comdefaultrate);
splx(s);
siocons.cn_dev = makedev(CDEV_MAJOR, 0);
cn_tab = &siocons;
return 0;
}
int
siogdbattach(port, speed)
int port;
int speed;
{
int s;
u_char cfcr;
struct siocnstate sp;
siogdbiobase = port;
gdbdefaultrate = speed;
s = spltty();
/*
* Initialize the divisor latch. We can't rely on
* siocnopen() to do this the first time, since it
* avoids writing to the latch if the latch appears
* to have the correct value. Also, if we didn't
* just read the speed from the hardware, then we
* need to set the speed in hardware so that
* switching it later is null.
*/
cfcr = inb(siogdbiobase + com_cfcr);
outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
outb(siogdbiobase + com_dlbl,
COMBRD(gdbdefaultrate) & 0xff);
outb(siogdbiobase + com_dlbh,
(u_int) COMBRD(gdbdefaultrate) >> 8);
outb(siogdbiobase + com_cfcr, cfcr);
siocnopen(&sp, siogdbiobase, gdbdefaultrate);
splx(s);
return 0;
}
#endif
#ifdef __i386__
static
#endif
void
siocninit(cp)
struct consdev *cp;
{
comconsole = DEV_TO_UNIT(cp->cn_dev);
}
#ifdef __i386__
static
#endif
int
siocncheckc(dev)
dev_t dev;
{
int c;
Port_t iobase;
int s;
struct siocnstate sp;
if (minor(dev) == siogdbunit)
iobase = siogdbiobase;
else
iobase = siocniobase;
s = spltty();
siocnopen(&sp, iobase, comdefaultrate);
if (inb(iobase + com_lsr) & LSR_RXRDY)
c = inb(iobase + com_data);
else
c = -1;
siocnclose(&sp, iobase);
splx(s);
return (c);
}
int
siocngetc(dev)
dev_t dev;
{
int c;
Port_t iobase;
int s;
struct siocnstate sp;
if (minor(dev) == siogdbunit)
iobase = siogdbiobase;
else
iobase = siocniobase;
s = spltty();
siocnopen(&sp, iobase, comdefaultrate);
while (!(inb(iobase + com_lsr) & LSR_RXRDY))
;
c = inb(iobase + com_data);
siocnclose(&sp, iobase);
splx(s);
return (c);
}
void
siocnputc(dev, c)
dev_t dev;
int c;
{
int s;
struct siocnstate sp;
Port_t iobase;
if (minor(dev) == siogdbunit)
iobase = siogdbiobase;
else
iobase = siocniobase;
s = spltty();
siocnopen(&sp, iobase, comdefaultrate);
siocntxwait(iobase);
outb(iobase + com_data, c);
siocnclose(&sp, iobase);
splx(s);
}
#ifdef __alpha__
int
siogdbgetc()
{
int c;
Port_t iobase;
int s;
struct siocnstate sp;
iobase = siogdbiobase;
s = spltty();
siocnopen(&sp, iobase, gdbdefaultrate);
while (!(inb(iobase + com_lsr) & LSR_RXRDY))
;
c = inb(iobase + com_data);
siocnclose(&sp, iobase);
splx(s);
return (c);
}
void
siogdbputc(c)
int c;
{
int s;
struct siocnstate sp;
s = spltty();
siocnopen(&sp, siogdbiobase, gdbdefaultrate);
siocntxwait(siogdbiobase);
outb(siogdbiobase + com_data, c);
siocnclose(&sp, siogdbiobase);
splx(s);
}
#endif
/*
* support PnP cards if we are using 'em
*/
#if NPNP > 0
static pnpid_t siopnp_ids[] = {
{ 0x5015f435, "MOT1550"},
{ 0x8113b04e, "Supra1381"},
{ 0x9012b04e, "Supra1290"},
{ 0x7121b04e, "SupraExpress 56i Sp"},
{ 0x11007256, "USR0011"},
{ 0x30207256, "USR2030"},
{ 0x31307256, "USR3031"},
{ 0x90307256, "USR3090"},
{ 0x0100440e, "Cardinal MVP288IV"},
{ 0 }
};
static char *siopnp_probe(u_long csn, u_long vend_id);
static void siopnp_attach(u_long csn, u_long vend_id, char *name,
struct isa_device *dev);
static u_long nsiopnp = NSIO;
static struct pnp_device siopnp = {
"siopnp",
siopnp_probe,
siopnp_attach,
&nsiopnp,
&tty_imask
};
DATA_SET (pnpdevice_set, siopnp);
static char *
siopnp_probe(u_long csn, u_long vend_id)
{
pnpid_t *id;
char *s = NULL;
for(id = siopnp_ids; id->vend_id != 0; id++) {
if (vend_id == id->vend_id) {
s = id->id_str;
break;
}
}
if (s) {
struct pnp_cinfo d;
read_pnp_parms(&d, 0);
if (d.enable == 0 || d.flags & 1) {
printf("CSN %lu is disabled.\n", csn);
return (NULL);
}
}
return (s);
}
static void
siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
{
struct pnp_cinfo d;
if (dev->id_unit >= NSIOTOT)
return;
if (read_pnp_parms(&d, 0) == 0) {
printf("failed to read pnp parms\n");
return;
}
write_pnp_parms(&d, 0);
enable_pnp_card();
dev->id_iobase = d.port[0];
dev->id_irq = (1 << d.irq[0]);
dev->id_ointr = siointr;
dev->id_ri_flags = RI_FAST;
dev->id_drq = -1;
if (dev->id_driver == NULL) {
dev->id_driver = &siodriver;
dev->id_id = isa_compat_nextid();
}
if ((dev->id_alive = sioprobe(dev)) != 0)
sioattach(dev);
else
printf("sio%d: probe failed\n", dev->id_unit);
}
#endif
DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass,
CDEV_MAJOR, NOMAJ, sio_cdevsw, 0, 0);
#ifdef PC98
/*
* pc98 local function
*/
static void
com_tiocm_set(struct com_s *com, int msr)
{
int s;
int tmp = 0;
int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
s=spltty();
com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
| ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
tmp |= (CMD8251_TxEN|CMD8251_RxEN);
if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
pc98_i8251_clear_or_cmd( com, mask, tmp );
splx(s);
}
static void
com_tiocm_bis(struct com_s *com, int msr)
{
int s;
int tmp = 0;
s=spltty();
com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
tmp |= CMD8251_TxEN|CMD8251_RxEN;
if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
pc98_i8251_or_cmd( com, tmp );
splx(s);
}
static void
com_tiocm_bic(struct com_s *com, int msr)
{
int s;
int tmp = msr;
s=spltty();
com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
pc98_i8251_clear_cmd( com, tmp );
splx(s);
}
static int
com_tiocm_get(struct com_s *com)
{
return( com->pc98_prev_modem_status );
}
static int
com_tiocm_get_delta(struct com_s *com)
{
int tmp;
tmp = com->pc98_modem_delta;
com->pc98_modem_delta = 0;
return( tmp );
}
/* convert to TIOCM_?? ( ioctl.h ) */
static int
pc98_get_modem_status(struct com_s *com)
{
int stat, stat2;
register int msr;
stat = inb(com->sts_port);
stat2 = inb(com->in_modem_port);
msr = com->pc98_prev_modem_status
& ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
#if COM_CARRIER_DETECT_EMULATE
if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
msr |= TIOCM_CAR;
}
#endif
return(msr);
}
static void
pc98_check_msr(void* chan)
{
int msr, delta;
int s;
register struct tty *tp;
struct com_s *com;
int mynor;
int unit;
dev_t dev;
dev=(dev_t)chan;
mynor = minor(dev);
unit = MINOR_TO_UNIT(mynor);
com = com_addr(unit);
tp = com->tp;
s = spltty();
msr = pc98_get_modem_status(com);
/* make change flag */
delta = msr ^ com->pc98_prev_modem_status;
if ( delta & TIOCM_CAR ) {
if ( com->modem_car_chg_timer ) {
if ( -- com->modem_car_chg_timer )
msr ^= TIOCM_CAR;
} else {
if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
msr ^= TIOCM_CAR;
}
} else
com->modem_car_chg_timer = 0;
delta = ( msr ^ com->pc98_prev_modem_status ) &
(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
com->pc98_prev_modem_status = msr;
delta = ( com->pc98_modem_delta |= delta );
splx(s);
if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
if ( delta ) {
commint(dev);
}
timeout(pc98_check_msr, (caddr_t)dev,
PC98_CHECK_MODEM_INTERVAL);
} else {
com->modem_checking = 0;
}
}
static void
pc98_msrint_start(dev_t dev)
{
struct com_s *com;
int mynor;
int unit;
int s = spltty();
mynor = minor(dev);
unit = MINOR_TO_UNIT(mynor);
com = com_addr(unit);
/* modem control line check routine envoke interval is 1/10 sec */
if ( com->modem_checking == 0 ) {
com->pc98_prev_modem_status = pc98_get_modem_status(com);
com->pc98_modem_delta = 0;
timeout(pc98_check_msr, (caddr_t)dev,
PC98_CHECK_MODEM_INTERVAL);
com->modem_checking = 1;
}
splx(s);
}
static void
pc98_disable_i8251_interrupt(struct com_s *com, int mod)
{
/* disable interrupt */
register int tmp;
mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
COM_INT_DISABLE
tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
COM_INT_ENABLE
}
static void
pc98_enable_i8251_interrupt(struct com_s *com, int mod)
{
register int tmp;
COM_INT_DISABLE
tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
COM_INT_ENABLE
}
static int
pc98_check_i8251_interrupt(struct com_s *com)
{
return ( com->intr_enable & 0x07 );
}
static void
pc98_i8251_clear_cmd(struct com_s *com, int x)
{
int tmp;
COM_INT_DISABLE
tmp = com->pc98_prev_siocmd & ~(x);
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
COM_INT_ENABLE
}
static void
pc98_i8251_or_cmd(struct com_s *com, int x)
{
int tmp;
COM_INT_DISABLE
tmp = com->pc98_prev_siocmd | (x);
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
COM_INT_ENABLE
}
static void
pc98_i8251_set_cmd(struct com_s *com, int x)
{
int tmp;
COM_INT_DISABLE
tmp = (x);
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
COM_INT_ENABLE
}
static void
pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
{
int tmp;
COM_INT_DISABLE
tmp = com->pc98_prev_siocmd & ~(clr);
tmp |= (x);
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
COM_INT_ENABLE
}
static int
pc98_i8251_get_cmd(struct com_s *com)
{
return com->pc98_prev_siocmd;
}
static int
pc98_i8251_get_mod(struct com_s *com)
{
return com->pc98_prev_siomod;
}
static void
pc98_i8251_reset(struct com_s *com, int mode, int command)
{
outb(com->cmd_port, 0); /* dummy */
DELAY(2);
outb(com->cmd_port, 0); /* dummy */
DELAY(2);
outb(com->cmd_port, 0); /* dummy */
DELAY(2);
outb(com->cmd_port, CMD8251_RESET); /* internal reset */
DELAY(2);
outb(com->cmd_port, mode ); /* mode register */
com->pc98_prev_siomod = mode;
DELAY(2);
pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
}
static void
pc98_check_sysclock(void)
{
/* get system clock from port */
if ( pc98_machine_type & M_8M ) {
/* 8 MHz system & H98 */
sysclock = 8;
} else {
/* 5 MHz system */
sysclock = 5;
}
}
static void
com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
{
int cfcr=0, count;
int previnterrupt;
count = pc98_ttspeedtab( com, speed );
if ( count < 0 ) return;
previnterrupt = pc98_check_i8251_interrupt(com);
pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
switch ( cflag&CSIZE ) {
case CS5:
cfcr = MOD8251_5BITS; break;
case CS6:
cfcr = MOD8251_6BITS; break;
case CS7:
cfcr = MOD8251_7BITS; break;
case CS8:
cfcr = MOD8251_8BITS; break;
}
if ( cflag&PARENB ) {
if ( cflag&PARODD )
cfcr |= MOD8251_PODD;
else
cfcr |= MOD8251_PEVEN;
} else
cfcr |= MOD8251_PDISAB;
if ( cflag&CSTOPB )
cfcr |= MOD8251_STOP2;
else
cfcr |= MOD8251_STOP1;
if ( count & 0x10000 )
cfcr |= MOD8251_CLKX1;
else
cfcr |= MOD8251_CLKX16;
if (epson_machine_id != 0x20) { /* XXX */
int tmp;
while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
;
}
/* set baud rate from ospeed */
pc98_set_baud_rate( com, count );
if ( cfcr != pc98_i8251_get_mod(com) )
pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
pc98_enable_i8251_interrupt( com, previnterrupt );
}
static int
pc98_ttspeedtab(struct com_s *com, int speed)
{
int if_type, effect_sp, count = -1, mod;
if_type = com->pc98_if_type & 0x0f;
switch (com->pc98_if_type) {
case COM_IF_INTERNAL:
if (PC98SIO_baud_rate_port(if_type) != -1) {
count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
if (count > 0) {
count |= COM1_EXT_CLOCK;
break;
}
}
/* for *1CLK asynchronous! mode, TEFUTEFU */
mod = (sysclock == 5) ? 2457600 : 1996800;
effect_sp = ttspeedtab( speed, pc98speedtab );
if ( effect_sp < 0 ) /* XXX */
effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
if ( effect_sp <= 0 )
return effect_sp;
if ( effect_sp == speed )
mod /= 16;
if ( mod % effect_sp )
return(-1);
count = mod / effect_sp;
if ( count > 65535 )
return(-1);
if ( effect_sp != speed )
count |= 0x10000;
break;
case COM_IF_PC9861K_1:
case COM_IF_PC9861K_2:
count = 1;
break;
case COM_IF_IND_SS_1:
case COM_IF_IND_SS_2:
case COM_IF_PIO9032B_1:
case COM_IF_PIO9032B_2:
if ( speed == 0 ) return 0;
count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
break;
case COM_IF_B98_01_1:
case COM_IF_B98_01_2:
if ( speed == 0 ) return 0;
count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
#ifdef B98_01_OLD
if (count == 0 || count == 1) {
count += 4;
count |= 0x20000; /* x1 mode for 76800 and 153600 */
}
#endif
break;
}
return count;
}
static void
pc98_set_baud_rate( struct com_s *com, int count )
{
int if_type, io, s;
if_type = com->pc98_if_type & 0x0f;
io = com->iobase & 0xff00;
switch (com->pc98_if_type) {
case COM_IF_INTERNAL:
if (PC98SIO_baud_rate_port(if_type) != -1) {
if (count & COM1_EXT_CLOCK) {
outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
break;
} else {
outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
}
}
if ( count < 0 ) {
printf( "[ Illegal count : %d ]", count );
return;
} else if ( count == 0 )
return;
/* set i8253 */
s = splclock();
if (count != 3)
outb( 0x77, 0xb6 );
else
outb( 0x77, 0xb4 );
outb( 0x5f, 0);
outb( 0x75, count & 0xff );
outb( 0x5f, 0);
outb( 0x75, (count >> 8) & 0xff );
splx(s);
break;
case COM_IF_IND_SS_1:
case COM_IF_IND_SS_2:
outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
outb(io | PC98SIO_baud_rate_port(if_type), 0);
outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
break;
case COM_IF_PIO9032B_1:
case COM_IF_PIO9032B_2:
outb(io | PC98SIO_baud_rate_port(if_type), count);
break;
case COM_IF_B98_01_1:
case COM_IF_B98_01_2:
outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
#ifdef B98_01_OLD
/*
* Some old B98_01 board should be controlled
* in different way, but this hasn't been tested yet.
*/
outb(io | PC98SIO_func_port(if_type),
(count & 0x20000) ? 0xf0 : 0xf2);
#endif
break;
}
}
static int
pc98_check_if_type(device_t dev, struct siodev *iod)
{
int irr, io, if_type, tmp;
static short irq_tab[2][8] = {
{ 3, 5, 6, 9, 10, 12, 13, -1},
{ 3, 10, 12, 13, 5, 6, 9, -1}
};
iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff;
if ((if_type < 0 || if_type > COM_IF_END1) &&
(if_type < 0x10 || if_type > COM_IF_END2))
return(-1);
if_type &= 0x0f;
iod->irq = 0;
io = isa_get_port(dev) & 0xff00;
if (IS_8251(iod->if_type)) {
if (PC98SIO_func_port(if_type) != -1) {
outb(io | PC98SIO_func_port(if_type), 0xf2);
tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
outb(io | PC98SIO_baud_rate_port(if_type), tmp);
}
iod->cmd = io | PC98SIO_cmd_port(if_type);
iod->sts = io | PC98SIO_sts_port(if_type);
iod->mod = io | PC98SIO_in_modem_port(if_type);
iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
if (iod->if_type == COM_IF_INTERNAL) {
iod->irq = 4;
/* XXX check new internal port. */
outb(0x138, 0);
DELAY(10);
for (tmp = 0; tmp < 100; tmp++) {
if ((inb(0x138) & 1) == 0) {
PC98SIO_baud_rate_port(if_type) = 0x13a;
if_8251_type[if_type].name = " (internal fast)";
if_8251_type[if_type].speedtab = pc98fast_speedtab;
break;
}
DELAY(1);
}
} else {
tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
if ((isa_get_port(dev) & 0xff) == IO_COM2)
iod->irq = irq_tab[0][tmp];
else
iod->irq = irq_tab[1][tmp];
}
} else {
irr = if_16550a_type[if_type].irr_read;
#ifdef COM_MULTIPORT
if (!COM_ISMULTIPORT(isa_get_flags(dev)) ||
device_get_unit(dev) == COM_MPMASTER(isa_get_flags(dev)))
#endif
if (irr != -1) {
tmp = inb(io | irr);
if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
iod->irq = irq_tab[1][tmp >> 3];
else
iod->irq = irq_tab[0][tmp & 0x07];
}
}
if ( iod->irq == -1 ) return -1;
return 0;
}
static int
pc98_set_ioport( struct com_s *com, int id_flags )
{
int io, if_type;
if_type = (id_flags >> 24) & 0xff;
if (IS_8251(if_type)) {
pc98_check_sysclock();
io = com->iobase & 0xff00;
com->pc98_if_type = if_type;
if_type &= 0x0f;
com->data_port = io | PC98SIO_data_port(if_type);
com->cmd_port = io | PC98SIO_cmd_port(if_type);
com->sts_port = io | PC98SIO_sts_port(if_type);
com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
return 0;
}
return -1;
}
#endif /* PC98 defined */
|