summaryrefslogtreecommitdiffstats
path: root/sys/dev/uart/uart_dev_z8530.c
blob: f948b26fa2fa6e3db1df20c5fa76d1b2b5bf0e64 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
/*-
 * Copyright (c) 2003 Marcel Moolenaar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <machine/bus.h>

#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <dev/uart/uart_bus.h>

#include <dev/ic/z8530.h>

#include "uart_if.h"

#define	DEFAULT_RCLK	307200

/* Hack! */
#ifdef __powerpc__
#define	UART_PCLK	0
#else
#define	UART_PCLK	MCB2_PCLK
#endif

/* Multiplexed I/O. */
static __inline void
uart_setmreg(struct uart_bas *bas, int reg, int val)
{

	uart_setreg(bas, REG_CTRL, reg);
	uart_barrier(bas);
	uart_setreg(bas, REG_CTRL, val);
}

static __inline uint8_t
uart_getmreg(struct uart_bas *bas, int reg)
{

	uart_setreg(bas, REG_CTRL, reg);
	uart_barrier(bas);
	return (uart_getreg(bas, REG_CTRL));
}

static int
z8530_divisor(int rclk, int baudrate)
{
	int act_baud, divisor, error;

	if (baudrate == 0)
		return (-1);

	divisor = (rclk + baudrate) / (baudrate << 1) - 2;
	if (divisor < 0 || divisor >= 65536)
		return (-1);
	act_baud = rclk / 2 / (divisor + 2);

	/* 10 times error in percent: */
	error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;

	/* 3.0% maximum error tolerance: */
	if (error < -30 || error > 30)
		return (-1);

	return (divisor);
}

static int
z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
    int parity, uint8_t *tpcp)
{
	int divisor;
	uint8_t mpm, rpc, tpc;

	rpc = RPC_RXE;
	mpm = MPM_CM16;
	tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));

	if (databits >= 8) {
		rpc |= RPC_RB8;
		tpc |= TPC_TB8;
	} else if (databits == 7) {
		rpc |= RPC_RB7;
		tpc |= TPC_TB7;
	} else if (databits == 6) {
		rpc |= RPC_RB6;
		tpc |= TPC_TB6;
	} else {
		rpc |= RPC_RB5;
		tpc |= TPC_TB5;
	}
	mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
	switch (parity) {
	case UART_PARITY_EVEN:	mpm |= MPM_PE | MPM_EVEN; break;
	case UART_PARITY_NONE:	break;
	case UART_PARITY_ODD:	mpm |= MPM_PE; break;
	default:		return (EINVAL);
	}

	if (baudrate > 0) {
		divisor = z8530_divisor(bas->rclk, baudrate);
		if (divisor == -1)
			return (EINVAL);
	} else
		divisor = -1;

	uart_setmreg(bas, WR_MCB2, UART_PCLK);
	uart_barrier(bas);

	if (divisor >= 0) {
		uart_setmreg(bas, WR_TCL, divisor & 0xff);
		uart_barrier(bas);
		uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
		uart_barrier(bas);
	}

	uart_setmreg(bas, WR_RPC, rpc);
	uart_barrier(bas);
	uart_setmreg(bas, WR_MPM, mpm);
	uart_barrier(bas);
	uart_setmreg(bas, WR_TPC, tpc);
	uart_barrier(bas);
	uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
	uart_barrier(bas);
	*tpcp = tpc;
	return (0);
}

static int
z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
    int parity)
{
	uint8_t tpc;

	if (bas->rclk == 0)
		bas->rclk = DEFAULT_RCLK;

	/* Assume we don't need to perform a full hardware reset. */
	switch (bas->chan) {
	case 1:
		uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
		break;
	case 2:
		uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
		break;
	}
	uart_barrier(bas);
	/* Set clock sources. */
	uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
	uart_setmreg(bas, WR_MCB2, UART_PCLK);
	uart_barrier(bas);
	/* Set data encoding. */
	uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
	uart_barrier(bas);

	tpc = TPC_DTR | TPC_RTS;
	z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
	return (int)tpc;
}

/*
 * Low-level UART interface.
 */
static int z8530_probe(struct uart_bas *bas);
static void z8530_init(struct uart_bas *bas, int, int, int, int);
static void z8530_term(struct uart_bas *bas);
static void z8530_putc(struct uart_bas *bas, int);
static int z8530_rxready(struct uart_bas *bas);
static int z8530_getc(struct uart_bas *bas, struct mtx *);

static struct uart_ops uart_z8530_ops = {
	.probe = z8530_probe,
	.init = z8530_init,
	.term = z8530_term,
	.putc = z8530_putc,
	.rxready = z8530_rxready,
	.getc = z8530_getc,
};

static int
z8530_probe(struct uart_bas *bas)
{

	return (0);
}

static void
z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
    int parity)
{

	z8530_setup(bas, baudrate, databits, stopbits, parity);
}

static void
z8530_term(struct uart_bas *bas)
{
}

static void
z8530_putc(struct uart_bas *bas, int c)
{

	while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
		;
	uart_setreg(bas, REG_DATA, c);
	uart_barrier(bas);
}

static int
z8530_rxready(struct uart_bas *bas)
{

	return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
}

static int
z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
{
	int c;

	uart_lock(hwmtx);

	while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
		uart_unlock(hwmtx);
		DELAY(10);
		uart_lock(hwmtx);
	}

	c = uart_getreg(bas, REG_DATA);

	uart_unlock(hwmtx);

	return (c);
}

/*
 * High-level UART interface.
 */
struct z8530_softc {
	struct uart_softc base;
	uint8_t	tpc;
	uint8_t	txidle;
};

static int z8530_bus_attach(struct uart_softc *);
static int z8530_bus_detach(struct uart_softc *);
static int z8530_bus_flush(struct uart_softc *, int);
static int z8530_bus_getsig(struct uart_softc *);
static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
static int z8530_bus_ipend(struct uart_softc *);
static int z8530_bus_param(struct uart_softc *, int, int, int, int);
static int z8530_bus_probe(struct uart_softc *);
static int z8530_bus_receive(struct uart_softc *);
static int z8530_bus_setsig(struct uart_softc *, int);
static int z8530_bus_transmit(struct uart_softc *);

static kobj_method_t z8530_methods[] = {
	KOBJMETHOD(uart_attach,		z8530_bus_attach),
	KOBJMETHOD(uart_detach,		z8530_bus_detach),
	KOBJMETHOD(uart_flush,		z8530_bus_flush),
	KOBJMETHOD(uart_getsig,		z8530_bus_getsig),
	KOBJMETHOD(uart_ioctl,		z8530_bus_ioctl),
	KOBJMETHOD(uart_ipend,		z8530_bus_ipend),
	KOBJMETHOD(uart_param,		z8530_bus_param),
	KOBJMETHOD(uart_probe,		z8530_bus_probe),
	KOBJMETHOD(uart_receive,	z8530_bus_receive),
	KOBJMETHOD(uart_setsig,		z8530_bus_setsig),
	KOBJMETHOD(uart_transmit,	z8530_bus_transmit),
	{ 0, 0 }
};

struct uart_class uart_z8530_class = {
	"z8530",
	z8530_methods,
	sizeof(struct z8530_softc),
	.uc_ops = &uart_z8530_ops,
	.uc_range = 2,
	.uc_rclk = DEFAULT_RCLK
};

#define	SIGCHG(c, i, s, d)				\
	if (c) {					\
		i |= (i & s) ? s : s | d;		\
	} else {					\
		i = (i & s) ? (i & ~s) | d : i;		\
	}

static int
z8530_bus_attach(struct uart_softc *sc)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	struct uart_bas *bas;
	struct uart_devinfo *di;

	bas = &sc->sc_bas;
	if (sc->sc_sysdev != NULL) {
		di = sc->sc_sysdev;
		z8530->tpc = TPC_DTR|TPC_RTS;
		z8530_param(bas, di->baudrate, di->databits, di->stopbits,
		    di->parity, &z8530->tpc);
	} else {
		z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
		z8530->tpc &= ~(TPC_DTR|TPC_RTS);
	}
	z8530->txidle = 1;	/* Report SER_INT_TXIDLE. */

	(void)z8530_bus_getsig(sc);

	uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
	uart_barrier(bas);
	uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
	uart_barrier(bas);
	uart_setmreg(bas, WR_IV, 0);
	uart_barrier(bas);
	uart_setmreg(bas, WR_TPC, z8530->tpc);
	uart_barrier(bas);
	uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
	uart_barrier(bas);
	return (0);
}

static int
z8530_bus_detach(struct uart_softc *sc)
{

	return (0);
}

static int
z8530_bus_flush(struct uart_softc *sc, int what)
{

	return (0);
}

static int
z8530_bus_getsig(struct uart_softc *sc)
{
	uint32_t new, old, sig;
	uint8_t bes;

	do {
		old = sc->sc_hwsig;
		sig = old;
		uart_lock(sc->sc_hwmtx);
		bes = uart_getmreg(&sc->sc_bas, RR_BES);
		uart_unlock(sc->sc_hwmtx);
		SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
		SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
		SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
		new = sig & ~SER_MASK_DELTA;
	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
	return (sig);
}

static int
z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	struct uart_bas *bas;
	int baudrate, divisor, error;

	bas = &sc->sc_bas;
	error = 0;
	uart_lock(sc->sc_hwmtx);
	switch (request) {
	case UART_IOCTL_BREAK:
		if (data)
			z8530->tpc |= TPC_BRK;
		else
			z8530->tpc &= ~TPC_BRK;
		uart_setmreg(bas, WR_TPC, z8530->tpc);
		uart_barrier(bas);
		break;
	case UART_IOCTL_BAUD:
		divisor = uart_getmreg(bas, RR_TCH);
		divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
		baudrate = bas->rclk / 2 / (divisor + 2);
		*(int*)data = baudrate;
		break;
	default:
		error = EINVAL;
		break;
	}
	uart_unlock(sc->sc_hwmtx);
	return (error);
}

static int
z8530_bus_ipend(struct uart_softc *sc)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	struct uart_bas *bas;
	int ipend;
	uint32_t sig;
	uint8_t bes, ip, iv, src;

	bas = &sc->sc_bas;
	ipend = 0;

	uart_lock(sc->sc_hwmtx);
	switch (bas->chan) {
	case 1:
		ip = uart_getmreg(bas, RR_IP);
		break;
	case 2:	/* XXX hack!!! */
		iv = uart_getmreg(bas, RR_IV) & 0x0E;
		switch (iv) {
		case IV_TEB:	ip = IP_TIA; break;
		case IV_XSB:	ip = IP_SIA; break;
		case IV_RAB:	ip = IP_RIA; break;
		default:	ip = 0; break;
		}
		break;
	default:
		ip = 0;
		break;
	}

	if (ip & IP_RIA)
		ipend |= SER_INT_RXREADY;

	if (ip & IP_TIA) {
		uart_setreg(bas, REG_CTRL, CR_RSTTXI);
		uart_barrier(bas);
		if (z8530->txidle) {
			ipend |= SER_INT_TXIDLE;
			z8530->txidle = 0;	/* Mask SER_INT_TXIDLE. */
		}
	}

	if (ip & IP_SIA) {
		uart_setreg(bas, REG_CTRL, CR_RSTXSI);
		uart_barrier(bas);
		bes = uart_getmreg(bas, RR_BES);
		if (bes & BES_BRK)
			ipend |= SER_INT_BREAK;
		sig = sc->sc_hwsig;
		SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
		SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
		SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
		if (sig & SER_MASK_DELTA)
			ipend |= SER_INT_SIGCHG;
		src = uart_getmreg(bas, RR_SRC);
		if (src & SRC_OVR) {
			uart_setreg(bas, REG_CTRL, CR_RSTERR);
			uart_barrier(bas);
			ipend |= SER_INT_OVERRUN;
		}
	}

	if (ipend) {
		uart_setreg(bas, REG_CTRL, CR_RSTIUS);
		uart_barrier(bas);
	}

	uart_unlock(sc->sc_hwmtx);

	return (ipend);
}

static int
z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
    int stopbits, int parity)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	int error;

	uart_lock(sc->sc_hwmtx);
	error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
	    &z8530->tpc);
	uart_unlock(sc->sc_hwmtx);
	return (error);
}

static int
z8530_bus_probe(struct uart_softc *sc)
{
	char buf[80];
	int error;
	char ch;

	error = z8530_probe(&sc->sc_bas);
	if (error)
		return (error);

	sc->sc_rxfifosz = 3;
	sc->sc_txfifosz = 1;

	ch = sc->sc_bas.chan - 1 + 'A';

	snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
	device_set_desc_copy(sc->sc_dev, buf);
	return (0);
}

static int
z8530_bus_receive(struct uart_softc *sc)
{
	struct uart_bas *bas;
	int xc;
	uint8_t bes, src;

	bas = &sc->sc_bas;
	uart_lock(sc->sc_hwmtx);
	bes = uart_getmreg(bas, RR_BES);
	while (bes & BES_RXA) {
		if (uart_rx_full(sc)) {
			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
			break;
		}
		xc = uart_getreg(bas, REG_DATA);
		uart_barrier(bas);
		src = uart_getmreg(bas, RR_SRC);
		if (src & SRC_FE)
			xc |= UART_STAT_FRAMERR;
		if (src & SRC_PE)
			xc |= UART_STAT_PARERR;
		if (src & SRC_OVR)
			xc |= UART_STAT_OVERRUN;
		uart_rx_put(sc, xc);
		if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
			uart_setreg(bas, REG_CTRL, CR_RSTERR);
			uart_barrier(bas);
		}
		bes = uart_getmreg(bas, RR_BES);
	}
	/* Discard everything left in the Rx FIFO. */
	while (bes & BES_RXA) {
		(void)uart_getreg(bas, REG_DATA);
		uart_barrier(bas);
		src = uart_getmreg(bas, RR_SRC);
		if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
			uart_setreg(bas, REG_CTRL, CR_RSTERR);
			uart_barrier(bas);
		}
		bes = uart_getmreg(bas, RR_BES);
	}
	uart_unlock(sc->sc_hwmtx);
	return (0);
}

static int
z8530_bus_setsig(struct uart_softc *sc, int sig)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	struct uart_bas *bas;
	uint32_t new, old;

	bas = &sc->sc_bas;
	do {
		old = sc->sc_hwsig;
		new = old;
		if (sig & SER_DDTR) {
			SIGCHG(sig & SER_DTR, new, SER_DTR,
			    SER_DDTR);
		}
		if (sig & SER_DRTS) {
			SIGCHG(sig & SER_RTS, new, SER_RTS,
			    SER_DRTS);
		}
	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));

	uart_lock(sc->sc_hwmtx);
	if (new & SER_DTR)
		z8530->tpc |= TPC_DTR;
	else
		z8530->tpc &= ~TPC_DTR;
	if (new & SER_RTS)
		z8530->tpc |= TPC_RTS;
	else
		z8530->tpc &= ~TPC_RTS;
	uart_setmreg(bas, WR_TPC, z8530->tpc);
	uart_barrier(bas);
	uart_unlock(sc->sc_hwmtx);
	return (0);
}

static int
z8530_bus_transmit(struct uart_softc *sc)
{
	struct z8530_softc *z8530 = (struct z8530_softc*)sc;
	struct uart_bas *bas;

	bas = &sc->sc_bas;
	uart_lock(sc->sc_hwmtx);
	while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
		;
	uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
	uart_barrier(bas);
	sc->sc_txbusy = 1;
	z8530->txidle = 1;	/* Report SER_INT_TXIDLE again. */
	uart_unlock(sc->sc_hwmtx);
	return (0);
}
OpenPOWER on IntegriCloud