summaryrefslogtreecommitdiffstats
path: root/sys/dev/sr/if_sr.c
blob: db4eafb60913c607773de9953d60f560b1eba71e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
/*-
 * Copyright (c) 1996 - 2001 John Hay.
 * Copyright (c) 1996 SDL Communications, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

/*
 * Programming assumptions and other issues.
 *
 * Only a 16K window will be used.
 *
 * The descriptors of a DMA channel will fit in a 16K memory window.
 *
 * The buffers of a transmit DMA channel will fit in a 16K memory window.
 *
 * When interface is going up, handshaking is set and it is only cleared
 * when the interface is down'ed.
 *
 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
 * internal/external clock, etc.....
 *
 */

#include "opt_netgraph.h"
#ifdef NETGRAPH
#include <dev/sr/if_sr.h>
#endif	/* NETGRAPH */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/mbuf.h>
#include <sys/sockio.h>
#include <sys/socket.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>

#include <net/if.h>
#ifdef NETGRAPH
#include <sys/syslog.h>
#else /* NETGRAPH */
#include <net/if_sppp.h>

#include <net/bpf.h>
#endif	/* NETGRAPH */

#include <machine/md_var.h>

#include <dev/ic/hd64570.h>
#include <dev/sr/if_srregs.h>

#ifdef NETGRAPH
#include <netgraph/ng_message.h>
#include <netgraph/netgraph.h>
#endif /* NETGRAPH */
/* #define USE_MODEMCK */

#ifndef BUGGY
#define BUGGY		0
#endif

#ifndef NETGRAPH
#define PPP_HEADER_LEN	4
#endif /* NETGRAPH */

static int	next_sc_unit = 0;
#ifndef NETGRAPH
#ifdef USE_MODEMCK
static int	sr_watcher = 0;
#endif
#endif /* NETGRAPH */

/*
 * Define the software interface for the card... There is one for
 * every channel (port).
 */
struct sr_softc {
#ifndef NETGRAPH
	struct	sppp ifsppp;	/* PPP service w/in system */
#endif /* NETGRAPH */
	struct	sr_hardc *hc;	/* card-level information */

	int	unit;		/* With regard to all sr devices */
	int	subunit;	/* With regard to this card */

	struct	buf_block {
		u_int	txdesc;	/* DPRAM offset */
		u_int	txstart;/* DPRAM offset */
		u_int	txend;	/* DPRAM offset */
		u_int	txtail;	/* # of 1st free gran */
		u_int	txmax;	/* # of free grans */
		u_int	txeda;	/* err descr addr */
	} block[SR_TX_BLOCKS];

	char	xmit_busy;	/* Transmitter is busy */
	char	txb_inuse;	/* # of tx grans in use */
	u_int	txb_new;	/* ndx to new buffer */
	u_int	txb_next_tx;	/* ndx to next gran rdy tx */

	u_int	rxdesc;		/* DPRAM offset */
	u_int	rxstart;	/* DPRAM offset */
	u_int	rxend;		/* DPRAM offset */
	u_int	rxhind;		/* ndx to the hd of rx bufrs */
	u_int	rxmax;		/* # of avail grans */

	u_int	clk_cfg;	/* Clock configuration */

	int	scachan;	/* channel # on card */
#ifdef NETGRAPH
	int	running;	/* something is attached so we are running */
	int	dcd;		/* do we have dcd? */
	/* ---netgraph bits --- */
	char		nodename[NG_NODESIZ]; /* store our node name */
	int		datahooks;	/* number of data hooks attached */
	node_p		node;		/* netgraph node */
	hook_p		hook;		/* data hook */
	hook_p		debug_hook;
	struct ifqueue	xmitq_hipri;	/* hi-priority transmit queue */
	struct ifqueue	xmitq;		/* transmit queue */
	int		flags;		/* state */
#define	SCF_RUNNING	0x01		/* board is active */
#define	SCF_OACTIVE	0x02		/* output is active */
	int		out_dog;	/* watchdog cycles output count-down */
	struct callout_handle handle;	/* timeout(9) handle */
	u_long		inbytes, outbytes;	/* stats */
	u_long		lastinbytes, lastoutbytes; /* a second ago */
	u_long		inrate, outrate;	/* highest rate seen */
	u_long		inlast;		/* last input N secs ago */
	u_long		out_deficit;	/* output since last input */
	u_long		oerrors, ierrors[6];
	u_long		opackets, ipackets;
#endif /* NETGRAPH */
};

#ifdef NETGRAPH
#define	DOG_HOLDOFF	6	/* dog holds off for 6 secs */
#define	QUITE_A_WHILE	300	/* 5 MINUTES */
#define	LOTS_OF_PACKETS	100	
#endif /* NETGRAPH */

/*
 * Baud Rate table for Sync Mode.
 * Each entry consists of 3 elements:
 * Baud Rate (x100) , TMC, BR
 *
 * Baud Rate = FCLK / TMC / 2^BR
 * Baud table for Crystal freq. of 9.8304 Mhz
 */
#ifdef N2_TEST_SPEED
struct rate_line {
	int	target;		/* target rate/100 */
	int	tmc_reg;	/* TMC register value */
	int	br_reg;		/* BR (BaudRateClk) selector */
} n2_rates[] = {
	/* Baudx100	TMC		BR */
	{ 3,		128,		8 },
	{ 6,		128,		7 },
	{ 12,		128,		6 },
	{ 24,		128,		5 },
	{ 48,		128,		4 },
	{ 96,		128,		3 },
	{ 192,		128,		2 },
	{ 384,		128,		1 },
	{ 560,		88,		1 },
	{ 640,		77,		1 },
	{ 1280,		38,		1 },
	{ 2560,		19,		1 },
	{ 5120,		10,		1 },
	{ 10000,	5,		1 },
	{ 15000,	3,		1 },
	{ 25000,	2,		1 },
	{ 50000,	1,		1 },
	{ 0,		0,		0 }
};

int	sr_test_speed[] = {
	N2_TEST_SPEED,
	N2_TEST_SPEED
};

int	etc0vals[] = {
	SR_MCR_ETC0,		/* ISA channel 0 */
	SR_MCR_ETC1,		/* ISA channel 1 */
	SR_FECR_ETC0,		/* PCI channel 0 */
	SR_FECR_ETC1		/* PCI channel 1 */
};
#endif

devclass_t sr_devclass;
#ifndef NETGRAPH
MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
#endif

static void	srintr(void *arg);
static void	sr_xmit(struct sr_softc *sc);
#ifndef NETGRAPH
static void	srstart(struct ifnet *ifp);
static int	srioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
static void	srwatchdog(struct ifnet *ifp);
#else
static void	srstart(struct sr_softc *sc);
static void	srwatchdog(struct sr_softc *sc);
#endif /* NETGRAPH */
static int	sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
static void	sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
static void	sr_eat_packet(struct sr_softc *sc, int single);
static void	sr_get_packets(struct sr_softc *sc);

static void	sr_up(struct sr_softc *sc);
static void	sr_down(struct sr_softc *sc);
static void	src_init(struct sr_hardc *hc);
static void	sr_init_sca(struct sr_hardc *hc);
static void	sr_init_msci(struct sr_softc *sc);
static void	sr_init_rx_dmac(struct sr_softc *sc);
static void	sr_init_tx_dmac(struct sr_softc *sc);
static void	sr_dmac_intr(struct sr_hardc *hc, u_char isr);
static void	sr_msci_intr(struct sr_hardc *hc, u_char isr);
static void	sr_timer_intr(struct sr_hardc *hc, u_char isr);
#ifndef NETGRAPH
#ifdef USE_MODEMCK
static void	sr_modemck(void *x);
#endif
#else
static void	sr_modemck(struct sr_softc *x);
#endif /* NETGRAPH */

#ifdef NETGRAPH
static	void	ngsr_watchdog_frame(void * arg);

static ng_constructor_t	ngsr_constructor;
static ng_rcvmsg_t	ngsr_rcvmsg;
static ng_shutdown_t	ngsr_shutdown;
static ng_newhook_t	ngsr_newhook;
/*static ng_findhook_t	ngsr_findhook; */
static ng_connect_t	ngsr_connect;
static ng_rcvdata_t	ngsr_rcvdata;
static ng_disconnect_t	ngsr_disconnect;

static struct ng_type typestruct = {
	.version =	NG_ABI_VERSION,
	.name =		NG_SR_NODE_TYPE,
	.constructor =	ngsr_constructor,
	.rcvmsg =	ngsr_rcvmsg,
	.shutdown =	ngsr_shutdown,
	.newhook =	ngsr_newhook,
	.connect =	ngsr_connect,
	.rcvdata =	ngsr_rcvdata,
	.disconnect =	ngsr_disconnect,
};
NETGRAPH_INIT_ORDERED(sync_sr, &typestruct, SI_SUB_DRIVERS, SI_ORDER_FIRST);
#endif /* NETGRAPH */

/*
 * Register the ports on the adapter.
 * Fill in the info for each port.
#ifndef NETGRAPH
 * Attach each port to sppp and bpf.
#endif
 */
int
sr_attach(device_t device)
{
	int intf_sw, pndx;
	u_int32_t flags;
	u_int fecr;
	struct sr_hardc *hc;
	struct sr_softc *sc;
#ifndef NETGRAPH
	struct ifnet *ifp;
#endif /* NETGRAPH */
	int unit;		/* index: channel w/in card */

	hc = (struct sr_hardc *)device_get_softc(device);
	MALLOC(sc, struct sr_softc *,
		hc->numports * sizeof(struct sr_softc),
		M_DEVBUF, M_WAITOK | M_ZERO);
	if (sc == NULL)
		goto errexit;
	hc->sc = sc;

	/*
	 * Get the TX clock direction and configuration. The default is a
	 * single external clock which is used by RX and TX.
	 */
	switch(hc->cardtype) {
	case SR_CRD_N2:
		flags = device_get_flags(device);
#ifdef N2_TEST_SPEED
		if (sr_test_speed[0] > 0)
			hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
		else
#endif
		if (flags & SR_FLAGS_0_CLK_MSK)
			hc->sc[0].clk_cfg =
			    (flags & SR_FLAGS_0_CLK_MSK)
			    >> SR_FLAGS_CLK_SHFT;

		if (hc->numports == 2)
#ifdef N2_TEST_SPEED
			if (sr_test_speed[1] > 0)
				hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
			else
#endif
			if (flags & SR_FLAGS_1_CLK_MSK)
				hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
				    >> (SR_FLAGS_CLK_SHFT +
				    SR_FLAGS_CLK_CHAN_SHFT);
		break;
	case SR_CRD_N2PCI:
		fecr = sr_read_fecr(hc);
		for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
			switch (pndx) {
			case 1:
				intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
				break;
			case 0:
			default:
				intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
			}

#ifdef N2_TEST_SPEED
			if (sr_test_speed[pndx] > 0)
				sc->clk_cfg = SR_FLAGS_INT_CLK;
			else
#endif
				switch (intf_sw) {
				default:
				case SR_FE_ID_RS232:
				case SR_FE_ID_HSSI:
				case SR_FE_ID_RS422:
				case SR_FE_ID_TEST:
					break;

				case SR_FE_ID_V35:
					sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
					break;

				case SR_FE_ID_X21:
					sc->clk_cfg = SR_FLAGS_EXT_CLK;
					break;
				}
		}
		sc = hc->sc;
		break;
	}

	/*
	 * Report Card configuration information before we start configuring
	 * each channel on the card...
	 */
	printf("src%d: %uK RAM (%d mempages) @ %p-%p, %u ports.\n",
	       hc->cunit, hc->memsize / 1024, hc->mempages,
	       hc->mem_start, hc->mem_end, hc->numports);

	src_init(hc);
	sr_init_sca(hc);

	if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
	    INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
		goto errexit;

	/*
	 * Now configure each port on the card.
	 */
	for (unit = 0; unit < hc->numports; sc++, unit++) {
		sc->hc = hc;
		sc->subunit = unit;
		sc->unit = next_sc_unit;
		next_sc_unit++;
		sc->scachan = unit % NCHAN;

		sr_init_rx_dmac(sc);
		sr_init_tx_dmac(sc);
		sr_init_msci(sc);

		printf("sr%d: Adapter %d, port %d.\n",
		       sc->unit, hc->cunit, sc->subunit);

#ifndef NETGRAPH
		ifp = &sc->ifsppp.pp_if;
		ifp->if_softc = sc;
		if_initname(ifp, device_get_name(device),
		    device_get_unit(device));
		ifp->if_mtu = PP_MTU;
		ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST |
		    IFF_NEEDSGIANT;
		ifp->if_ioctl = srioctl;
		ifp->if_start = srstart;
		ifp->if_watchdog = srwatchdog;

		sc->ifsppp.pp_flags = PP_KEEPALIVE;
		sppp_attach((struct ifnet *)&sc->ifsppp);
		if_attach(ifp);

		bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
#else	/* NETGRAPH */
		if (ng_make_node_common(&typestruct, &sc->node) != 0)
			goto errexit;
		sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
		if (ng_name_node(sc->node, sc->nodename)) {
			NG_NODE_UNREF(sc->node); /* make it go away again */
			goto errexit;
		}
		NG_NODE_SET_PRIVATE(sc->node, sc);
		callout_handle_init(&sc->handle);
		sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
		sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
		mtx_init(&sc->xmitq.ifq_mtx, "sr_xmitq", NULL, MTX_DEF);
		mtx_init(&sc->xmitq_hipri.ifq_mtx, "sr_xmitq_hipri", NULL,
		    MTX_DEF);
		sc->running = 0;
#endif	/* NETGRAPH */
	}

	if (hc->mempages)
		SRC_SET_OFF(hc);

	return (0);

errexit:
	sr_deallocate_resources(device);
	return (ENXIO);
}

int
sr_detach(device_t device)
{
	device_t parent = device_get_parent(device);
	struct sr_hardc *hc = device_get_softc(device);

	if (hc->intr_cookie != NULL) {
		if (BUS_TEARDOWN_INTR(parent, device,
			hc->res_irq, hc->intr_cookie) != 0) {
				printf("intr teardown failed.. continuing\n");
		}
		hc->intr_cookie = NULL;
	}

	/* XXX Stop the DMA. */

	/*
	 * deallocate any system resources we may have
	 * allocated on behalf of this driver.
	 */
	FREE(hc->sc, M_DEVBUF);
	hc->sc = NULL;
	hc->mem_start = NULL;
	return (sr_deallocate_resources(device));
}

int
sr_allocate_ioport(device_t device, int rid, u_long size)
{
	struct sr_hardc *hc = device_get_softc(device);

	hc->rid_ioport = rid;
	hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
			&hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
	if (hc->res_ioport == NULL) {
		goto errexit;
	}
	hc->bt_ioport = rman_get_bustag(hc->res_ioport);
	hc->bh_ioport = rman_get_bushandle(hc->res_ioport);

	return (0);

errexit:
	sr_deallocate_resources(device);
	return (ENXIO);
}

int
sr_allocate_irq(device_t device, int rid, u_long size)
{
	struct sr_hardc *hc = device_get_softc(device);

	hc->rid_irq = rid;
	hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
			&hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
	if (hc->res_irq == NULL) {
		goto errexit;
	}
	return (0);

errexit:
	sr_deallocate_resources(device);
	return (ENXIO);
}

int
sr_allocate_memory(device_t device, int rid, u_long size)
{
	struct sr_hardc *hc = device_get_softc(device);

	hc->rid_memory = rid;
	hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
			&hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
	if (hc->res_memory == NULL) {
		goto errexit;
	}
	hc->bt_memory = rman_get_bustag(hc->res_memory);
	hc->bh_memory = rman_get_bushandle(hc->res_memory);

	return (0);

errexit:
	sr_deallocate_resources(device);
	return (ENXIO);
}

int
sr_allocate_plx_memory(device_t device, int rid, u_long size)
{
	struct sr_hardc *hc = device_get_softc(device);

	hc->rid_plx_memory = rid;
	hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
			&hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
	if (hc->res_plx_memory == NULL) {
		goto errexit;
	}
	return (0);

errexit:
	sr_deallocate_resources(device);
	return (ENXIO);
}

int
sr_deallocate_resources(device_t device)
{
	struct sr_hardc *hc = device_get_softc(device);

	if (hc->res_irq != 0) {
		bus_deactivate_resource(device, SYS_RES_IRQ,
			hc->rid_irq, hc->res_irq);
		bus_release_resource(device, SYS_RES_IRQ,
			hc->rid_irq, hc->res_irq);
		hc->res_irq = 0;
	}
	if (hc->res_ioport != 0) {
		bus_deactivate_resource(device, SYS_RES_IOPORT,
			hc->rid_ioport, hc->res_ioport);
		bus_release_resource(device, SYS_RES_IOPORT,
			hc->rid_ioport, hc->res_ioport);
		hc->res_ioport = 0;
	}
	if (hc->res_memory != 0) {
		bus_deactivate_resource(device, SYS_RES_MEMORY,
			hc->rid_memory, hc->res_memory);
		bus_release_resource(device, SYS_RES_MEMORY,
			hc->rid_memory, hc->res_memory);
		hc->res_memory = 0;
	}
	if (hc->res_plx_memory != 0) {
		bus_deactivate_resource(device, SYS_RES_MEMORY,
			hc->rid_plx_memory, hc->res_plx_memory);
		bus_release_resource(device, SYS_RES_MEMORY,
			hc->rid_plx_memory, hc->res_plx_memory);
		hc->res_plx_memory = 0;
	}
	return (0);
}

/*
 * N2 Interrupt Service Routine
 *
 * First figure out which SCA gave the interrupt.
 * Process it.
 * See if there is other interrupts pending.
 * Repeat until there no interrupts remain.
 */
static void
srintr(void *arg)
{
	struct sr_hardc *hc = (struct sr_hardc *)arg;
	sca_regs *sca = hc->sca;	/* MSCI register tree */
	u_char  isr0, isr1, isr2;	/* interrupt statii captured */

#if BUGGY > 1
	printf("sr: srintr_hc(hc=%08x)\n", hc);
#endif

	/*
	 * Since multiple interfaces may share this interrupt, we must loop
	 * until no interrupts are still pending service.
	 */
	while (1) {
		/*
		 * Read all three interrupt status registers from the N2
		 * card...
		 */
		isr0 = SRC_GET8(hc, sca->isr0);
		isr1 = SRC_GET8(hc, sca->isr1);
		isr2 = SRC_GET8(hc, sca->isr2);

		/*
		 * If all three registers returned 0, we've finished
		 * processing interrupts from this device, so we can quit
		 * this loop...
		 */
		if ((isr0 | isr1 | isr2) == 0)
			break;

#if BUGGY > 2
		printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
#ifndef NETGRAPH
			unit, isr0, isr1, isr2);
#else
			hc->cunit, isr0, isr1, isr2);
#endif /* NETGRAPH */
#endif

		/*
		 * Now we can dispatch the interrupts. Since we don't expect
		 * either MSCI or timer interrupts, we'll test for DMA
		 * interrupts first...
		 */
		if (isr1)	/* DMA-initiated interrupt */
			sr_dmac_intr(hc, isr1);

		if (isr0)	/* serial part IRQ? */
			sr_msci_intr(hc, isr0);

		if (isr2)	/* timer-initiated interrupt */
			sr_timer_intr(hc, isr2);
	}
}

/*
 * This will only start the transmitter. It is assumed that the data
 * is already there.
 * It is normally called from srstart() or sr_dmac_intr().
 */
static void
sr_xmit(struct sr_softc *sc)
{
	u_short cda_value;	/* starting descriptor */
	u_short eda_value;	/* ending descriptor */
	struct sr_hardc *hc;
#ifndef NETGRAPH
	struct ifnet *ifp;	/* O/S Network Services */
#endif /* NETGRAPH */
	dmac_channel *dmac;	/* DMA channel registers */

#if BUGGY > 0
	printf("sr: sr_xmit( sc=%08x)\n", sc);
#endif

	hc = sc->hc;
#ifndef NETGRAPH
	ifp = &sc->ifsppp.pp_if;
#endif /* NETGRAPH */
	dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];

	/*
	 * Get the starting and ending addresses of the chain to be
	 * transmitted and pass these on to the DMA engine on-chip.
	 */
	cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
	cda_value &= 0x00ffff;
	eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
	eda_value &= 0x00ffff;

	SRC_PUT16(hc, dmac->cda, cda_value);
	SRC_PUT16(hc, dmac->eda, eda_value);

	/*
	 * Now we'll let the DMA status register know about this change
	 */
	SRC_PUT8(hc, dmac->dsr, SCA_DSR_DE);

	sc->xmit_busy = 1;	/* mark transmitter busy */

#if BUGGY > 2
	printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
	       sc->unit, cda_value, eda_value,
	       sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
#endif

	sc->txb_next_tx++;	/* update next transmit seq# */

	if (sc->txb_next_tx == SR_TX_BLOCKS)	/* handle wrap... */
		sc->txb_next_tx = 0;

#ifndef NETGRAPH
	/*
	 * Finally, we'll set a timout (which will start srwatchdog())
	 * within the O/S network services layer...
	 */
	ifp->if_timer = 2;	/* Value in seconds. */
#else
	/*
	 * Don't time out for a while.
	 */
	sc->out_dog = DOG_HOLDOFF;	/* give ourself some breathing space*/
#endif /* NETGRAPH */
}

/*
 * This function will be called from the upper level when a user add a
 * packet to be send, and from the interrupt handler after a finished
 * transmit.
 *
 * NOTE: it should run at spl_imp().
 *
 * This function only place the data in the oncard buffers. It does not
 * start the transmition. sr_xmit() does that.
 *
 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 * The function that clears that should ensure that the transmitter
 * and its DMA is in a "good" idle state.
 */
#ifndef NETGRAPH
static void
srstart(struct ifnet *ifp)
{
	struct sr_softc *sc;	/* channel control structure */
#else
static void
srstart(struct sr_softc *sc)
{
#endif /* NETGRAPH */
	struct sr_hardc *hc;	/* card control/config block */
	int len;		/* total length of a packet */
	int pkts;		/* packets placed in DPRAM */
	int tlen;		/* working length of pkt */
	u_int i;
	struct mbuf *mtx;	/* message buffer from O/S */
	u_char *txdata;		/* buffer address in DPRAM */
	sca_descriptor *txdesc;	/* working descriptor pointr */
	struct buf_block *blkp;

#ifndef NETGRAPH
#if BUGGY > 0
	printf("sr: srstart( ifp=%08x)\n", ifp);
#endif
	sc = ifp->if_softc;
	if ((ifp->if_flags & IFF_RUNNING) == 0)
		return;
#endif /* NETGRAPH */
	hc = sc->hc;
	/*
	 * It is OK to set the memory window outside the loop because all tx
	 * buffers and descriptors are assumed to be in the same 16K window.
	 */
	if (hc->mempages) {
		SRC_SET_ON(hc);
		SRC_SET_MEM(hc, sc->block[0].txdesc);
	}

	/*
	 * Loop to place packets into DPRAM.
	 *
	 * We stay in this loop until there is nothing in
	 * the TX queue left or the tx buffers are full.
	 */
top_srstart:

	/*
	 * See if we have space for more packets.
	 */
	if (sc->txb_inuse == SR_TX_BLOCKS) {	/* out of space? */
#ifndef NETGRAPH
		ifp->if_flags |= IFF_OACTIVE;	/* yes, mark active */
#else
		/*ifp->if_flags |= IFF_OACTIVE;*/	/* yes, mark active */
#endif /* NETGRAPH */

		if (hc->mempages)
			SRC_SET_OFF(hc);

#if BUGGY > 9
		printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
		       sc->unit, sc->txb_inuse);
#endif
		return;
	}
	/*
	 * OK, the card can take more traffic.  Let's see if there's any
	 * pending from the system...
	 *
	 * NOTE:
	 * The architecture of the networking interface doesn't
	 * actually call us like 'write()', providing an address.  We get
	 * started, a lot like a disk strategy routine, and we actually call
	 * back out to the system to get traffic to send...
	 *
	 * NOTE:
	 * If we were gonna run through another layer, we would use a
	 * dispatch table to select the service we're getting a packet
	 * from...
	 */
#ifndef NETGRAPH
	mtx = sppp_dequeue(ifp);
#else /* NETGRAPH */
	IF_DEQUEUE(&sc->xmitq_hipri, mtx);
	if (mtx == NULL) {
		IF_DEQUEUE(&sc->xmitq, mtx);
	}
#endif /* NETGRAPH */
	if (!mtx) {
		if (hc->mempages)
			SRC_SET_OFF(hc);
		return;
	}
	/*
	 * OK, we got a packet from the network services of the O/S. Now we
	 * can move it into the DPRAM (under control of the descriptors) and
	 * fire it off...
	 */
	pkts = 0;
	i = 0;			/* counts # of granules used */

	blkp = &sc->block[sc->txb_new];	/* address of free granule */
	txdesc = (sca_descriptor *)
	    (hc->mem_start + (blkp->txdesc & hc->winmsk));

	txdata = (u_char *)(hc->mem_start
			    + (blkp->txstart & hc->winmsk));

	/*
	 * Now we'll try to install as many packets as possible into the
	 * card's DP RAM buffers.
	 */
	for (;;) {		/* perform actual copy of packet */
		len = mtx->m_pkthdr.len;	/* length of message */

#if BUGGY > 1
		printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
			   sc->unit, mtx, len);
#endif

#ifndef NETGRAPH
		BPF_MTAP(ifp, mtx);
#else	/* NETGRAPH */
		sc->outbytes += len;
#endif	/* NETGRAPH */

		/*
		 * We can perform a straight copy because the tranmit
		 * buffers won't wrap.
		 */
		m_copydata(mtx, 0, len, txdata);

		/*
		 * Now we know how big the message is gonna be.  We must now
		 * construct the descriptors to drive this message out...
		 */
		tlen = len;
		while (tlen > SR_BUF_SIZ) {	/* loop for full granules */
			txdesc->stat = 0;	/* reset bits */
			txdesc->len = SR_BUF_SIZ;	/* size of granule */
			tlen -= SR_BUF_SIZ;

			txdesc++;	/* move to next dscr */
			txdata += SR_BUF_SIZ;	/* adjust data addr */
			i++;
		}

		/*
		 * This section handles the setting of the final piece of a
		 * message.
		 */
		txdesc->stat = SCA_DESC_EOM;
		txdesc->len = tlen;
		pkts++;

		/*
		 * prepare for subsequent packets (if any)
		 */
		txdesc++;
		txdata += SR_BUF_SIZ;	/* next mem granule */
		i++;		/* count of granules */

		/*
		 * OK, we've now placed the message into the DPRAM where it
		 * can be transmitted.  We'll now release the message memory
		 * and update the statistics...
		 */
		m_freem(mtx);
#ifndef NETGRAPH
		++sc->ifsppp.pp_if.if_opackets;
#else	/* NETGRAPH */
		sc->opackets++;
#endif /* NETGRAPH */

		/*
		 * Check if we have space for another packet. XXX This is
		 * hardcoded.  A packet can't be larger than 3 buffers (3 x
		 * 512).
		 */
		if ((i + 3) >= blkp->txmax) {	/* enough remains? */
#if BUGGY > 9
			printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
			       sc->unit, i, pkts);
#endif
			break;
		}
		/*
		 * We'll pull the next message to be sent (if any)
		 */
#ifndef NETGRAPH
		mtx = sppp_dequeue(ifp);
#else /* NETGRAPH */
		IF_DEQUEUE(&sc->xmitq_hipri, mtx);
		if (mtx == NULL) {
			IF_DEQUEUE(&sc->xmitq, mtx);
		}
#endif /* NETGRAPH */
		if (!mtx) {	/* no message?  We're done! */
#if BUGGY > 9
			printf("sr%d.srstart: pending=0, pkts=%d\n",
			       sc->unit, pkts);
#endif
			break;
		}
	}

	blkp->txtail = i;	/* record next free granule */

	/*
	 * Mark the last descriptor, so that the SCA know where to stop.
	 */
	txdesc--;		/* back up to last descriptor in list */
	txdesc->stat |= SCA_DESC_EOT;	/* mark as end of list */

	/*
	 * Now we'll reset the transmit granule's descriptor address so we
	 * can record this in the structure and fire it off w/ the DMA
	 * processor of the serial chip...
	 */
	txdesc = (sca_descriptor *)(uintptr_t)blkp->txdesc;
	blkp->txeda = (u_short)((uintptr_t)&txdesc[i]);

	sc->txb_inuse++;	/* update inuse status */
	sc->txb_new++;		/* new traffic wuz added */

	if (sc->txb_new == SR_TX_BLOCKS)
		sc->txb_new = 0;

	/*
	 * If the tranmitter wasn't marked as "busy" we will force it to be
	 * started...
	 */
	if (sc->xmit_busy == 0) {
		sr_xmit(sc);
#if BUGGY > 9
		printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
#endif
	}
	goto top_srstart;
}

#ifndef NETGRAPH
/*
 * Handle ioctl's at the device level, though we *will* call up
 * a layer...
 */
#if BUGGY > 2
static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
#endif

static int
srioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
{
	int s, error, was_up, should_be_up;
	struct sr_softc *sc = ifp->if_softc;

#if BUGGY > 0
	if_printf(ifp, "srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
	       ifp, cmd, data);
#endif

	was_up = ifp->if_flags & IFF_RUNNING;

	error = sppp_ioctl(ifp, cmd, data);

#if BUGGY > 1
	if_printf(ifp, "ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
	      ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
#endif

	if (error)
		return error;

	if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
#if BUGGY > 2
		if (bug_splats[sc->unit]++ < 2) {
			printf("sr(%d).if_addrlist = %08x\n",
			       sc->unit, ifp->if_addrlist);
			printf("sr(%d).if_bpf = %08x\n",
			       sc->unit, ifp->if_bpf);
			printf("sr(%d).if_init = %08x\n",
			       sc->unit, ifp->if_init);
			printf("sr(%d).if_output = %08x\n",
			       sc->unit, ifp->if_output);
			printf("sr(%d).if_start = %08x\n",
			       sc->unit, ifp->if_start);
			printf("sr(%d).if_done = %08x\n",
			       sc->unit, ifp->if_done);
			printf("sr(%d).if_ioctl = %08x\n",
			       sc->unit, ifp->if_ioctl);
			printf("sr(%d).if_reset = %08x\n",
			       sc->unit, ifp->if_reset);
			printf("sr(%d).if_watchdog = %08x\n",
			       sc->unit, ifp->if_watchdog);
		}
#endif
		return 0;
	}

	s = splimp();
	should_be_up = ifp->if_flags & IFF_RUNNING;

	if (!was_up && should_be_up) {
		/*
		 * Interface should be up -- start it.
		 */
		sr_up(sc);
		srstart(ifp);

		/*
		 * XXX Clear the IFF_UP flag so that the link will only go
		 * up after sppp lcp and ipcp negotiation.
		 */
		/* ifp->if_flags &= ~IFF_UP; */
	} else if (was_up && !should_be_up) {
		/*
		 * Interface should be down -- stop it.
		 */
		sr_down(sc);
		sppp_flush(ifp);
	}
	splx(s);
	return 0;
}
#endif /* NETGRAPH */

/*
 * This is to catch lost tx interrupts.
 */
static void
#ifndef NETGRAPH
srwatchdog(struct ifnet *ifp)
#else
srwatchdog(struct sr_softc *sc)
#endif /* NETGRAPH */
{
	int     got_st0, got_st1, got_st3, got_dsr;
#ifndef NETGRAPH
	struct sr_softc *sc = ifp->if_softc;
#endif /* NETGRAPH */
	struct sr_hardc *hc = sc->hc;
	msci_channel *msci = &hc->sca->msci[sc->scachan];
	dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];

#if BUGGY > 0
#ifndef NETGRAPH
	printf("srwatchdog(unit=%d)\n", unit);
#else
	printf("srwatchdog(unit=%d)\n", sc->unit);
#endif /* NETGRAPH */
#endif

#ifndef NETGRAPH
	if (!(ifp->if_flags & IFF_RUNNING))
		return;

	ifp->if_oerrors++;	/* update output error count */
#else	/* NETGRAPH */
	sc->oerrors++;	/* update output error count */
#endif /* NETGRAPH */

	got_st0 = SRC_GET8(hc, msci->st0);
	got_st1 = SRC_GET8(hc, msci->st1);
	got_st3 = SRC_GET8(hc, msci->st3);
	got_dsr = SRC_GET8(hc, dmac->dsr);

#ifndef NETGRAPH
#if	0
	if (ifp->if_flags & IFF_DEBUG)
#endif
		printf("sr%d: transmit failed, "
#else	/* NETGRAPH */
	printf("sr%d: transmit failed, "
#endif /* NETGRAPH */
		       "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
		       sc->unit,
		       got_st0, got_st1, got_st3, got_dsr);

	if (SRC_GET8(hc, msci->st1) & SCA_ST1_UDRN) {
		SRC_PUT8(hc, msci->cmd, SCA_CMD_TXABORT);
		SRC_PUT8(hc, msci->cmd, SCA_CMD_TXENABLE);
		SRC_PUT8(hc, msci->st1, SCA_ST1_UDRN);
	}
	sc->xmit_busy = 0;
#ifndef NETGRAPH
	ifp->if_flags &= ~IFF_OACTIVE;
#else
	/*ifp->if_flags &= ~IFF_OACTIVE; */
#endif /* NETGRAPH */

	if (sc->txb_inuse && --sc->txb_inuse)
		sr_xmit(sc);

#ifndef NETGRAPH
	srstart(ifp);	/* restart transmitter */
#else
	srstart(sc);	/* restart transmitter */
#endif /* NETGRAPH */
}

static void
sr_up(struct sr_softc *sc)
{
	struct sr_hardc *hc = sc->hc;
	sca_regs *sca = hc->sca;
	msci_channel *msci = &sca->msci[sc->scachan];

#if BUGGY > 0
	printf("sr_up(sc=%08x)\n", sc);
#endif

	/*
	 * Enable transmitter and receiver. Raise DTR and RTS. Enable
	 * interrupts.
	 *
	 * XXX What about using AUTO mode in msci->md0 ???
	 */
	SRC_PUT8(hc, msci->ctl, SRC_GET8(hc, msci->ctl) & ~SCA_CTL_RTS);

	if (sc->scachan == 0)
		switch (hc->cardtype) {
		case SR_CRD_N2:
			sr_outb(hc, SR_MCR,
			    (sr_inb(hc, SR_MCR) & ~SR_MCR_DTR0));
			break;
		case SR_CRD_N2PCI:
			sr_write_fecr(hc, sr_read_fecr(hc) & ~SR_FECR_DTR0);
			break;
		}
	else
		switch (hc->cardtype) {
		case SR_CRD_N2:
			sr_outb(hc, SR_MCR,
			    (sr_inb(hc, SR_MCR) & ~SR_MCR_DTR1));
			break;
		case SR_CRD_N2PCI:
			sr_write_fecr(hc, sr_read_fecr(hc) & ~SR_FECR_DTR1);
			break;
		}

	if (sc->scachan == 0) {
		SRC_PUT8(hc, sca->ier0, SRC_GET8(hc, sca->ier0) | 0x000F);
		SRC_PUT8(hc, sca->ier1, SRC_GET8(hc, sca->ier1) | 0x000F);
	} else {
		SRC_PUT8(hc, sca->ier0, SRC_GET8(hc, sca->ier0) | 0x00F0);
		SRC_PUT8(hc, sca->ier1, SRC_GET8(hc, sca->ier1) | 0x00F0);
	}

	SRC_PUT8(hc, msci->cmd, SCA_CMD_RXENABLE);
	sr_inb(hc, 0);	/* XXX slow it down a bit. */
	SRC_PUT8(hc, msci->cmd, SCA_CMD_TXENABLE);

#ifndef NETGRAPH
#ifdef USE_MODEMCK
	if (sr_watcher == 0)
		sr_modemck(NULL);
#endif
#else	/* NETGRAPH */
	untimeout(ngsr_watchdog_frame, sc, sc->handle);
	sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
	sc->running = 1;
#endif /* NETGRAPH */
}

static void
sr_down(struct sr_softc *sc)
{
	struct sr_hardc *hc = sc->hc;
	sca_regs *sca = hc->sca;
	msci_channel *msci = &sca->msci[sc->scachan];

#if BUGGY > 0
	printf("sr_down(sc=%08x)\n", sc);
#endif
#ifdef NETGRAPH
	untimeout(ngsr_watchdog_frame, sc, sc->handle);
	sc->running = 0;
#endif /* NETGRAPH */

	/*
	 * Disable transmitter and receiver. Lower DTR and RTS. Disable
	 * interrupts.
	 */
	SRC_PUT8(hc, msci->cmd, SCA_CMD_RXDISABLE);
	sr_inb(hc, 0);	/* XXX slow it down a bit. */
	SRC_PUT8(hc, msci->cmd, SCA_CMD_TXDISABLE);

	SRC_PUT8(hc, msci->ctl, SRC_GET8(hc, msci->ctl) | SCA_CTL_RTS);

	if (sc->scachan == 0)
		switch (hc->cardtype) {
		case SR_CRD_N2:
			sr_outb(hc, SR_MCR, sr_inb(hc, SR_MCR) | SR_MCR_DTR0);
			break;
		case SR_CRD_N2PCI:
			sr_write_fecr(hc, sr_read_fecr(hc) | SR_FECR_DTR0);
			break;
		}
	else
		switch (hc->cardtype) {
		case SR_CRD_N2:
			sr_outb(hc, SR_MCR, sr_inb(hc, SR_MCR) | SR_MCR_DTR1);
			break;
		case SR_CRD_N2PCI:
			sr_write_fecr(hc, sr_read_fecr(hc) | SR_FECR_DTR1);
			break;
		}

	if (sc->scachan == 0) {
		SRC_PUT8(hc, sca->ier0, SRC_GET8(hc, sca->ier0) & ~0x0F);
		SRC_PUT8(hc, sca->ier1, SRC_GET8(hc, sca->ier1) & ~0x0F);
	} else {
		SRC_PUT8(hc, sca->ier0, SRC_GET8(hc, sca->ier0) & ~0xF0);
		SRC_PUT8(hc, sca->ier1, SRC_GET8(hc, sca->ier1) & ~0xF0);
	}
}

/*
 * Initialize the card, allocate memory for the sr_softc structures
 * and fill in the pointers.
 */
static void
src_init(struct sr_hardc *hc)
{
	struct sr_softc *sc = hc->sc;
	int x;
	u_int chanmem;
	u_int bufmem;
	u_int next;
	u_int descneeded;

#if BUGGY > 0
	printf("src_init(hc=%08x)\n", hc);
#endif

	chanmem = hc->memsize / hc->numports;
	next = 0;

	for (x = 0; x < hc->numports; x++, sc++) {
		int blk;

		for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
			sc->block[blk].txdesc = next;
			bufmem = (16 * 1024) / SR_TX_BLOCKS;
			descneeded = bufmem / SR_BUF_SIZ;

			sc->block[blk].txstart = sc->block[blk].txdesc
			    + ((((descneeded * sizeof(sca_descriptor))
				 / SR_BUF_SIZ) + 1)
			       * SR_BUF_SIZ);

			sc->block[blk].txend = next + bufmem;
			sc->block[blk].txmax =
			    (sc->block[blk].txend - sc->block[blk].txstart)
			    / SR_BUF_SIZ;
			next += bufmem;

#if BUGGY > 2
			printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
			       sc->unit, blk,
			       sc->block[blk].txdesc, sc->block[blk].txstart);
#endif
		}

		sc->rxdesc = next;
		bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
		descneeded = bufmem / SR_BUF_SIZ;
		sc->rxstart = sc->rxdesc +
		    ((((descneeded * sizeof(sca_descriptor)) /
		       SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
		sc->rxend = next + bufmem;
		sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
		next += bufmem;
	}
}

/*
 * The things done here are channel independent.
 *
 * Configure the sca waitstates.
 * Configure the global interrupt registers.
 * Enable master dma enable.
 */
static void
sr_init_sca(struct sr_hardc *hc)
{
	sca_regs *sca = hc->sca;

#if BUGGY > 0
	printf("sr_init_sca(hc=%08x)\n", hc);
#endif

	/*
	 * Do the wait registers. Set everything to 0 wait states.
	 */
	SRC_PUT8(hc, sca->pabr0, 0);
	SRC_PUT8(hc, sca->pabr1, 0);
	SRC_PUT8(hc, sca->wcrl, 0);
	SRC_PUT8(hc, sca->wcrm, 0);
	SRC_PUT8(hc, sca->wcrh, 0);

	/*
	 * Configure the interrupt registers. Most are cleared until the
	 * interface is configured.
	 */
	SRC_PUT8(hc, sca->ier0, 0x00);		/* MSCI interrupts. */
	SRC_PUT8(hc, sca->ier1, 0x00);		/* DMAC interrupts */
	SRC_PUT8(hc, sca->ier2, 0x00);		/* TIMER interrupts. */
	SRC_PUT8(hc, sca->itcr, 0x00);		/* Use ivr and no intr ack */
	SRC_PUT8(hc, sca->ivr, 0x40);		/* Interrupt vector. */
	SRC_PUT8(hc, sca->imvr, 0x40);

	/*
	 * Configure the timers. XXX Later
	 */

	/*
	 * Set the DMA channel priority to rotate between all four channels.
	 *
	 * Enable all dma channels.
	 */
	SRC_PUT8(hc, sca->pcr, SCA_PCR_PR2);
	SRC_PUT8(hc, sca->dmer, SCA_DMER_EN);
}

/*
 * Configure the msci
 *
 * NOTE: The serial port configuration is hardcoded at the moment.
 */
static void
sr_init_msci(struct sr_softc *sc)
{
	int portndx;		/* on-board port number */
	u_int mcr_v;		/* contents of modem control */
	struct sr_hardc *hc = sc->hc;
	msci_channel *msci = &hc->sca->msci[sc->scachan];
#ifdef N2_TEST_SPEED
	int br_v;		/* contents for BR divisor */
	int etcndx;		/* index into ETC table */
	int fifo_v, gotspeed;	/* final tabled speed found */
	int tmc_v;		/* timer control register */
	int wanted;		/* speed (bitrate) wanted... */
	struct rate_line *rtp;
#endif

	portndx = sc->scachan;

#if BUGGY > 0
	printf("sr: sr_init_msci( sc=%08x)\n", sc);
#endif

	SRC_PUT8(hc, msci->cmd, SCA_CMD_RESET);
	SRC_PUT8(hc, msci->md0, SCA_MD0_CRC_1 | SCA_MD0_CRC_CCITT |
	    SCA_MD0_CRC_ENABLE | SCA_MD0_MODE_HDLC);
	SRC_PUT8(hc, msci->md1, SCA_MD1_NOADDRCHK);
	SRC_PUT8(hc, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);

	/*
	 * According to the manual I should give a reset after changing the
	 * mode registers.
	 */
	SRC_PUT8(hc, msci->cmd, SCA_CMD_RXRESET);
	SRC_PUT8(hc, msci->ctl, SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS);

	/*
	 * XXX Later we will have to support different clock settings.
	 */
	switch (sc->clk_cfg) {
	default:
#if BUGGY > 0
		printf("sr%: clk_cfg=%08x, selected default clock.\n",
		       portndx, sc->clk_cfg);
#endif
		/* FALLTHROUGH */
	case SR_FLAGS_EXT_CLK:
		/*
		 * For now all interfaces are programmed to use the RX clock
		 * for the TX clock.
		 */

#if BUGGY > 0
		printf("sr%d: External Clock Selected.\n", portndx);
#endif

		SRC_PUT8(hc, msci->rxs, SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
		SRC_PUT8(hc, msci->txs, SCA_TXS_CLK_RX | SCA_TXS_DIV1);
		break;

	case SR_FLAGS_EXT_SEP_CLK:
#if BUGGY > 0
		printf("sr%d: Split Clocking Selected.\n", portndx);
#endif

		SRC_PUT8(hc, msci->rxs, SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
		SRC_PUT8(hc, msci->txs, SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
		break;

	case SR_FLAGS_INT_CLK:
#if BUGGY > 0
		printf("sr%d: Internal Clocking selected.\n", portndx);
#endif

		/*
		 * XXX I do need some code to set the baud rate here!
		 */
#ifdef N2_TEST_SPEED
		switch (hc->cardtype) {
		case SR_CRD_N2PCI:
			mcr_v = sr_read_fecr(hc);
			etcndx = 2;
			break;
		case SR_CRD_N2:
		default:
			mcr_v = sr_inb(hc, SR_MCR);
			etcndx = 0;
		}

		fifo_v = 0x10;	/* stolen from Linux version */

		/*
		 * search for appropriate speed in table, don't calc it:
		 */
		wanted = sr_test_speed[portndx];
		rtp = &n2_rates[0];	/* point to first table item */

		while ((rtp->target > 0)	/* search table for speed */
		       &&(rtp->target != wanted))
			rtp++;

		/*
		 * We've searched the table for a matching speed.  If we've
		 * found the correct rate line, we'll get the pre-calc'd
		 * values for the TMC and baud rate divisor for subsequent
		 * use...
		 */
		if (rtp->target > 0) {	/* use table-provided values */
			gotspeed = wanted;
			tmc_v = rtp->tmc_reg;
			br_v = rtp->br_reg;
		} else {	/* otherwise assume 1MBit comm rate */
			gotspeed = 10000;
			tmc_v = 5;
			br_v = 1;
		}

		/*
		 * Now we mask in the enable clock output for the MCR:
		 */
		mcr_v |= etc0vals[etcndx + portndx];

		/*
		 * Now we'll program the registers with these speed- related
		 * contents...
		 */
		SRC_PUT8(hc, msci->tmc, tmc_v);
		SRC_PUT8(hc, msci->trc0, fifo_v);
		SRC_PUT8(hc, msci->rxs, SCA_RXS_CLK_INT + br_v);
		SRC_PUT8(hc, msci->txs, SCA_TXS_CLK_INT + br_v);

		switch (hc->cardtype) {
		case SR_CRD_N2PCI:
			sr_write_fecr(hc, mcr_v);
			break;
		case SR_CRD_N2:
		default:
			sr_outb(hc, SR_MCR, mcr_v);
		}

#if BUGGY > 0
		if (wanted != gotspeed)
			printf("sr%d: Speed wanted=%d, found=%d\n",
			       wanted, gotspeed);

		printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
		       portndx, gotspeed, tmc_v, br_v);
#endif
#else
		SRC_PUT8(hc, msci->rxs, SCA_RXS_CLK_INT | SCA_RXS_DIV1);
		SRC_PUT8(hc, msci->txs, SCA_TXS_CLK_INT | SCA_TXS_DIV1);

		SRC_PUT8(hc, msci->tmc, 5);

		if (portndx == 0)
			switch (hc->cardtype) {
			case SR_CRD_N2PCI:
				sr_write_fecr(hc,
				    sr_read_fecr(hc) | SR_FECR_ETC0);
				break;
			case SR_CRD_N2:
			default:
				mcr_v = sr_inb(hc, SR_MCR);
				mcr_v |= SR_MCR_ETC0;
				sr_outb(hc, SR_MCR, mcr_v);
			}
		else
			switch (hc->cardtype) {
			case SR_CRD_N2:
				mcr_v = sr_inb(hc, SR_MCR);
				mcr_v |= SR_MCR_ETC1;
				sr_outb(hc, SR_MCR, mcr_v);
				break;
			case SR_CRD_N2PCI:
				sr_write_fecr(hc,
				    sr_read_fecr(hc) | SR_FECR_ETC1);
				break;
			}
#endif
	}

	/*
	 * XXX Disable all interrupts for now. I think if you are using the
	 * dmac you don't use these interrupts.
	 */
	SRC_PUT8(hc, msci->ie0, 0);
	SRC_PUT8(hc, msci->ie1, 0x0C);
	SRC_PUT8(hc, msci->ie2, 0);
	SRC_PUT8(hc, msci->fie, 0);

	SRC_PUT8(hc, msci->sa0, 0);
	SRC_PUT8(hc, msci->sa1, 0);

	SRC_PUT8(hc, msci->idl, 0x7E);	/* set flags value */

	SRC_PUT8(hc, msci->rrc, 0x0E);
	SRC_PUT8(hc, msci->trc0, 0x10);
	SRC_PUT8(hc, msci->trc1, 0x1F);
}

/*
 * Configure the rx dma controller.
 */
static void
sr_init_rx_dmac(struct sr_softc *sc)
{
	struct sr_hardc *hc;
	dmac_channel *dmac;
	sca_descriptor *rxd;
	u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;

#if BUGGY > 0
	printf("sr_init_rx_dmac(sc=%08x)\n", sc);
#endif

	hc = sc->hc;
	dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];

	if (hc->mempages)
		SRC_SET_MEM(hc, sc->rxdesc);

	/*
	 * This phase initializes the contents of the descriptor table
	 * needed to construct a circular buffer...
	 */
	rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
	rxda_d = (uintptr_t) hc->mem_start - (sc->rxdesc & ~hc->winmsk);

	for (rxbuf = sc->rxstart;
	     rxbuf < sc->rxend;
	     rxbuf += SR_BUF_SIZ, rxd++) {
		/*
		 * construct the circular chain...
		 */
		rxda = (uintptr_t) &rxd[1] - rxda_d + hc->mem_pstart;
		rxd->cp = (u_short)(rxda & 0xffff);

		/*
		 * set the on-card buffer address...
		 */
		rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
		rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);

		rxd->len = 0;	/* bytes resident w/in granule */
		rxd->stat = 0xff;	/* The sca write here when finished */
	}

	/*
	 * heal the chain so that the last entry points to the first...
	 */
	rxd--;
	rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);

	/*
	 * reset the reception handler's index...
	 */
	sc->rxhind = 0;

	/*
	 * We'll now configure the receiver's DMA logic...
	 */
	SRC_PUT8(hc, dmac->dsr, 0);	/* Disable DMA transfer */
	SRC_PUT8(hc, dmac->dcr, SCA_DCR_ABRT);

	/* XXX maybe also SCA_DMR_CNTE */
	SRC_PUT8(hc, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
	SRC_PUT16(hc, dmac->bfl, SR_BUF_SIZ);

	cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
	sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);

	SRC_PUT16(hc, dmac->cda, cda_v);
	SRC_PUT8(hc, dmac->sarb, sarb_v);

	rxd = (sca_descriptor *)(uintptr_t)sc->rxstart;

	SRC_PUT16(hc, dmac->eda,
	    (u_short)((uintptr_t)&rxd[sc->rxmax - 1] & 0xffff));

	SRC_PUT8(hc, dmac->dir, 0xF0);

	SRC_PUT8(hc, dmac->dsr, SCA_DSR_DE);	/* Enable DMA */
}

/*
 * Configure the TX DMA descriptors.
 * Initialize the needed values and chain the descriptors.
 */
static void
sr_init_tx_dmac(struct sr_softc *sc)
{
	int blk;
	u_int txbuf, txda, txda_d;
	struct sr_hardc *hc;
	sca_descriptor *txd;
	dmac_channel *dmac;
	struct buf_block *blkp;
	u_int x;
	u_int sarb_v;

#if BUGGY > 0
	printf("sr_init_tx_dmac(sc=%08x)\n", sc);
#endif

	hc = sc->hc;
	dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];

	if (hc->mempages)
		SRC_SET_MEM(hc, sc->block[0].txdesc);

	/*
	 * Initialize the array of descriptors for transmission
	 */
	for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
		blkp = &sc->block[blk];
		txd = (sca_descriptor *)(hc->mem_start
					 + (blkp->txdesc & hc->winmsk));
		txda_d = (uintptr_t) hc->mem_start
		    - (blkp->txdesc & ~hc->winmsk);

		x = 0;
		txbuf = blkp->txstart;
		for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
			txda = (uintptr_t) &txd[1] - txda_d + hc->mem_pstart;
			txd->cp = (u_short)(txda & 0xffff);

			txd->bp = (u_short)((txbuf + hc->mem_pstart)
					    & 0xffff);
			txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
					    & 0xff);
			txd->len = 0;
			txd->stat = 0;
			x++;
		}

		txd--;
		txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
				    & 0xffff);

		blkp->txtail = (uintptr_t)txd - (uintptr_t)hc->mem_start;
	}

	SRC_PUT8(hc, dmac->dsr, 0);	/* Disable DMA */
	SRC_PUT8(hc, dmac->dcr, SCA_DCR_ABRT);
	SRC_PUT8(hc, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
	SRC_PUT8(hc, dmac->dir, SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);

	sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
	sarb_v &= 0x00ff;

	SRC_PUT8(hc, dmac->sarb, (u_char) sarb_v);
}

/*
 * Look through the descriptors to see if there is a complete packet
 * available. Stop if we get to where the sca is busy.
 *
 * Return the length and status of the packet.
 * Return nonzero if there is a packet available.
 *
 * NOTE:
 * It seems that we get the interrupt a bit early. The updateing of
 * descriptor values is not always completed when this is called.
 */
static int
sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
{
	int granules;	/* count of granules in pkt */
	int wki, wko;
	struct sr_hardc *hc;
	sca_descriptor *rxdesc;	/* current descriptor */
	sca_descriptor *endp;	/* ending descriptor */
	sca_descriptor *cda;	/* starting descriptor */

	hc = sc->hc;		/* get card's information */

	/*
	 * set up starting descriptor by pulling that info from the DMA half
	 * of the HD chip...
	 */
	wki = DMAC_RXCH(sc->scachan);
	wko = SRC_GET16(hc, hc->sca->dmac[wki].cda);

	cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));

#if BUGGY > 1
	printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
	       wki, wko, cda);
#endif

	/*
	 * open the appropriate memory window and set our expectations...
	 */
	if (hc->mempages) {
		SRC_SET_MEM(hc, sc->rxdesc);
		SRC_SET_ON(hc);
	}
	rxdesc = (sca_descriptor *)
	    (hc->mem_start + (sc->rxdesc & hc->winmsk));
	endp = rxdesc;
	rxdesc = &rxdesc[sc->rxhind];
	endp = &endp[sc->rxmax];

	*len = 0;		/* reset result total length */
	granules = 0;		/* reset count of granules */

	/*
	 * This loop will scan descriptors, but it *will* puke up if we wrap
	 * around to our starting point...
	 */
	while (rxdesc != cda) {
		*len += rxdesc->len;	/* increment result length */
		granules++;

		/*
		 * If we hit a valid packet's completion we'll know we've
		 * got a live one, and that we can deliver the packet.
		 * Since we're only allowed to report a packet available,
		 * somebody else does that...
		 */
		if (rxdesc->stat & SCA_DESC_EOM) {	/* End Of Message */
			*rxstat = rxdesc->stat;	/* return closing */
#if BUGGY > 0
			printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
			       sc->unit, *len, *rxstat, granules);
#endif
			return 1;	/* indicate success */
		}
		/*
		 * OK, this packet take up multiple granules.  Move on to
		 * the next descriptor so we can consider it...
		 */
		rxdesc++;

		if (rxdesc == endp)	/* recognize & act on wrap point */
			rxdesc = (sca_descriptor *)
			    (hc->mem_start + (sc->rxdesc & hc->winmsk));
	}

	/*
	 * Nothing found in the DPRAM.  Let the caller know...
	 */
	*len = 0;
	*rxstat = 0;

	return 0;
}

/*
 * Copy a packet from the on card memory into a provided mbuf.
 * Take into account that buffers wrap and that a packet may
 * be larger than a buffer.
 */
static void
sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
{
	struct sr_hardc *hc;
	sca_descriptor *rxdesc;
	u_int rxdata;
	u_int rxmax;
	u_int off = 0;
	u_int tlen;

#if BUGGY > 0
	printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
	       m, sc, len);
#endif

	hc = sc->hc;

	rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
	rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);

	rxdesc = (sca_descriptor *)
	    (hc->mem_start + (sc->rxdesc & hc->winmsk));
	rxdesc = &rxdesc[sc->rxhind];

	/*
	 * Using the count of bytes in the received packet, we decrement it
	 * for each granule (controller by an SCA descriptor) to control the
	 * looping...
	 */
	while (len) {
		/*
		 * tlen gets the length of *this* granule... ...which is
		 * then copied to the target buffer.
		 */
		tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;

		if (hc->mempages)
			SRC_SET_MEM(hc, rxdata);

		bcopy(hc->mem_start + (rxdata & hc->winmsk),
		      mtod(m, caddr_t) +off,
		      tlen);

		off += tlen;
		len -= tlen;

		/*
		 * now, return to the descriptor's window in DPRAM and reset
		 * the descriptor we've just suctioned...
		 */
		if (hc->mempages)
			SRC_SET_MEM(hc, sc->rxdesc);

		rxdesc->len = 0;
		rxdesc->stat = 0xff;

		/*
		 * Move on to the next granule.  If we've any remaining
		 * bytes to process we'll just continue in our loop...
		 */
		rxdata += SR_BUF_SIZ;
		rxdesc++;

		if (rxdata == rxmax) {	/* handle the wrap point */
			rxdata = sc->rxstart;
			rxdesc = (sca_descriptor *)
			    (hc->mem_start + (sc->rxdesc & hc->winmsk));
		}
	}
}

/*
 * If single is set, just eat a packet. Otherwise eat everything up to
 * where cda points. Update pointers to point to the next packet.
 *
 * This handles "flushing" of a packet as received...
 *
 * If the "single" parameter is zero, all pending reeceive traffic will
 * be flushed out of existence.  A non-zero value will only drop the
 * *next* (currently) pending packet...
 */
static void
sr_eat_packet(struct sr_softc *sc, int single)
{
	struct sr_hardc *hc;
	sca_descriptor *rxdesc;	/* current descriptor being eval'd */
	sca_descriptor *endp;	/* last descriptor in chain */
	sca_descriptor *cda;	/* current start point */
	u_int loopcnt = 0;	/* count of packets flushed ??? */
	u_char stat;		/* captured status byte from descr */

	hc = sc->hc;
	cda = (sca_descriptor *)(hc->mem_start + (SRC_GET16(hc,
	    hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) & hc->winmsk));

	/*
	 * loop until desc->stat == (0xff || EOM) Clear the status and
	 * length in the descriptor. Increment the descriptor.
	 */
	if (hc->mempages)
		SRC_SET_MEM(hc, sc->rxdesc);

	rxdesc = (sca_descriptor *)
	    (hc->mem_start + (sc->rxdesc & hc->winmsk));
	endp = rxdesc;
	rxdesc = &rxdesc[sc->rxhind];
	endp = &endp[sc->rxmax];

	/*
	 * allow loop, but abort it if we wrap completely...
	 */
	while (rxdesc != cda) {
		loopcnt++;

		if (loopcnt > sc->rxmax) {
			printf("sr%d: eat pkt %d loop, cda %p, "
			       "rxdesc %p, stat %x.\n",
			       sc->unit, loopcnt, cda, rxdesc,
			       rxdesc->stat);
			break;
		}
		stat = rxdesc->stat;

		rxdesc->len = 0;
		rxdesc->stat = 0xff;

		rxdesc++;
		sc->rxhind++;

		if (rxdesc == endp) {
			rxdesc = (sca_descriptor *)
			    (hc->mem_start + (sc->rxdesc & hc->winmsk));
			sc->rxhind = 0;
		}
		if (single && (stat == SCA_DESC_EOM))
			break;
	}

	/*
	 * Update the eda to the previous descriptor.
	 */
	rxdesc = (sca_descriptor *)(uintptr_t)sc->rxdesc;
	rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];

	SRC_PUT16(hc, hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
	    (u_short)(((uintptr_t)rxdesc + hc->mem_pstart) & 0xffff));
}

/*
 * While there is packets available in the rx buffer, read them out
 * into mbufs and ship them off.
 */
static void
sr_get_packets(struct sr_softc *sc)
{
	u_char rxstat;		/* acquired status byte */
	int i;
	int pkts;		/* count of packets found */
	int rxndx;		/* rcv buffer index */
	int tries;		/* settling time counter */
	u_int len;		/* length of pending packet */
	struct sr_hardc *hc;	/* card-level information */
	sca_descriptor *rxdesc;	/* descriptor in memory */
#ifndef NETGRAPH
	struct ifnet *ifp;	/* network intf ctl table */
#else
	int error;
#endif /* NETGRAPH */
	struct mbuf *m = NULL;	/* message buffer */

#if BUGGY > 0
	printf("sr_get_packets(sc=%08x)\n", sc);
#endif

	hc = sc->hc;
#ifndef NETGRAPH
	ifp = &sc->ifsppp.pp_if;
#endif /* NETGRAPH */

	if (hc->mempages) {
		SRC_SET_MEM(hc, sc->rxdesc);
		SRC_SET_ON(hc);	/* enable shared memory */
	}
	pkts = 0;		/* reset count of found packets */

	/*
	 * for each complete packet in the receiving pool, process each
	 * packet...
	 */
	while (sr_packet_avail(sc, &len, &rxstat)) {	/* packet pending? */
		/*
		 * I have seen situations where we got the interrupt but the
		 * status value wasn't deposited.  This code should allow
		 * the status byte's value to settle...
		 */

		tries = 5;

		while ((rxstat == 0x00ff)
		       && --tries)
			sr_packet_avail(sc, &len, &rxstat);

#if BUGGY > 1
		printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
		       len, rxstat);
#endif

		pkts++;
#ifdef NETGRAPH
		sc->inbytes += len;
		sc->inlast = 0;
#endif /* NETGRAPH */

		/*
		 * OK, we've settled the incoming message status. We can now
		 * process it...
		 */
		if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
#if BUGGY > 1
			printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
			       sc->unit, rxstat, len);
#endif

			MGETHDR(m, M_DONTWAIT, MT_DATA);
			if (m == NULL) {
				/*
				 * eat (flush) packet if get mbuf fail!!
				 */
				sr_eat_packet(sc, 1);
				continue;
			}
			/*
			 * construct control information for pass-off
			 */
#ifndef NETGRAPH
			m->m_pkthdr.rcvif = ifp;
#else
			m->m_pkthdr.rcvif = NULL;
#endif /* NETGRAPH */
			m->m_pkthdr.len = m->m_len = len;
			if (len > MHLEN) {
				MCLGET(m, M_DONTWAIT);
				if ((m->m_flags & M_EXT) == 0) {
					/*
					 * We couldn't get a big enough
					 * message packet, so we'll send the
					 * packet to /dev/null...
					 */
					m_freem(m);
					sr_eat_packet(sc, 1);
					continue;
				}
			}
			/*
			 * OK, we've got a good message buffer.  Now we can
			 * copy the received message into it
			 */
			sr_copy_rxbuf(m, sc, len);	/* copy from DPRAM */

#ifndef NETGRAPH
			BPF_MTAP(ifp, m);

#if BUGGY > 3
			{
				u_char *bp;

				bp = (u_char *)m;
				printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
				       sc->unit,
				       bp[0], bp[1], bp[2],
				       bp[4], bp[5], bp[6]);
			}
#endif
			sppp_input(ifp, m);
			ifp->if_ipackets++;

#else	/* NETGRAPH */
#if BUGGY > 3
			{
				u_char *bp;

				bp = mtod(m,u_char *);
				printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
				       sc->unit,
				       bp[0], bp[1], bp[2],
				       bp[4], bp[5], bp[6]);
				printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
				       bp[6], bp[7], bp[8],
				       bp[9], bp[10], bp[11]);
			}
#endif
			NG_SEND_DATA_ONLY(error, sc->hook, m);
			sc->ipackets++;
#endif /* NETGRAPH */
			/*
			 * Update the eda to the previous descriptor.
			 */
			i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
			sc->rxhind = (sc->rxhind + i) % sc->rxmax;

			rxdesc = (sca_descriptor *)(uintptr_t)sc->rxdesc;
			rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
			rxdesc = &rxdesc[rxndx];

			SRC_PUT16(hc, hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
			    (u_short)(((uintptr_t)rxdesc + hc->mem_pstart)
			    & 0xffff));

		} else {
			int got_st3, got_cda, got_eda;
			int tries = 5;

			while ((rxstat == 0xff) && --tries)
				sr_packet_avail(sc, &len, &rxstat);

			/*
			 * It look like we get an interrupt early
			 * sometimes and then the status is not
			 * filled in yet.
			 */
			if (tries && (tries != 5))
				continue;

			/*
			 * This chunk of code handles the error packets.
			 * We'll log them for posterity...
			 */
			sr_eat_packet(sc, 1);

#ifndef NETGRAPH
			ifp->if_ierrors++;
#else
			sc->ierrors[0]++;
#endif /* NETGRAPH */

			got_st3 = SRC_GET8(hc,
				  hc->sca->msci[sc->scachan].st3);
			got_cda = SRC_GET16(hc,
				  hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
			got_eda = SRC_GET16(hc,
				  hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);

#if BUGGY > 0
			printf("sr%d: Receive error chan %d, "
			       "stat %02x, msci st3 %02x,"
			       "rxhind %d, cda %04x, eda %04x.\n",
			       sc->unit, sc->scachan, rxstat,
			       got_st3, sc->rxhind, got_cda, got_eda);
#endif
		}
	}

#if BUGGY > 0
	printf("sr%d: sr_get_packets() found %d packet(s)\n",
	       sc->unit, pkts);
#endif

	if (hc->mempages)
		SRC_SET_OFF(hc);
}

/*
 * All DMA interrupts come here.
 *
 * Each channel has two interrupts.
 * Interrupt A for errors and Interrupt B for normal stuff like end
 * of transmit or receive dmas.
 */
static void
sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
{
	u_char dsr;		/* contents of DMA Stat Reg */
	u_char dotxstart;	/* enables for tranmit part */
	int mch;		/* channel being processed */
	struct sr_softc *sc;	/* channel's softc structure */
	sca_regs *sca = hc->sca;
	dmac_channel *dmac;	/* dma structure of chip */

#if BUGGY > 0
	printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
#endif

	mch = 0;		/* assume chan0 on card */
	dotxstart = isr1;	/* copy for xmitter starts */

	/*
	 * Shortcut if there is no interrupts for dma channel 0 or 1.
	 * Skip processing for channel 0 if no incoming hit
	 */
	if ((isr1 & 0x0F) == 0) {
		mch = 1;
		isr1 >>= 4;
	}
	do {
		sc = &hc->sc[mch];

		/*
		 * Transmit channel - DMA Status Register Evaluation
		 */
		if (isr1 & 0x0C) {
			dmac = &sca->dmac[DMAC_TXCH(mch)];

			/*
			 * get the DMA Status Register contents and write
			 * back to reset interrupt...
			 */
			dsr = SRC_GET8(hc, dmac->dsr);
			SRC_PUT8(hc, dmac->dsr, dsr);

			/*
			 * Check for (& process) a Counter overflow
			 */
			if (dsr & SCA_DSR_COF) {
				printf("sr%d: TX DMA Counter overflow, "
				       "txpacket no %lu.\n",
#ifndef NETGRAPH
				       sc->unit, sc->ifsppp.pp_if.if_opackets);
				sc->ifsppp.pp_if.if_oerrors++;
#else
				       sc->unit, sc->opackets);
				sc->oerrors++;
#endif /* NETGRAPH */
			}
			/*
			 * Check for (& process) a Buffer overflow
			 */
			if (dsr & SCA_DSR_BOF) {
				printf("sr%d: TX DMA Buffer overflow, "
				       "txpacket no %lu, dsr %02x, "
				       "cda %04x, eda %04x.\n",
#ifndef NETGRAPH
				       sc->unit, sc->ifsppp.pp_if.if_opackets,
#else
				       sc->unit, sc->opackets,
#endif /* NETGRAPH */
				       dsr,
				       SRC_GET16(hc, dmac->cda),
				       SRC_GET16(hc, dmac->eda));
#ifndef NETGRAPH
				sc->ifsppp.pp_if.if_oerrors++;
#else
				sc->oerrors++;
#endif /* NETGRAPH */
			}
			/*
			 * Check for (& process) an End of Transfer (OK)
			 */
			if (dsr & SCA_DSR_EOT) {
				/*
				 * This should be the most common case.
				 *
				 * Clear the IFF_OACTIVE flag.
				 *
				 * Call srstart to start a new transmit if
				 * there is data to transmit.
				 */
#if BUGGY > 0
				printf("sr%d: TX Completed OK\n", sc->unit);
#endif
				sc->xmit_busy = 0;
#ifndef NETGRAPH
				sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
				sc->ifsppp.pp_if.if_timer = 0;
#else
				/* XXX may need to mark tx inactive? */
				sc->out_deficit++;
				sc->out_dog = DOG_HOLDOFF;
#endif /* NETGRAPH */

				if (sc->txb_inuse && --sc->txb_inuse)
					sr_xmit(sc);
			}
		}
		/*
		 * Receive channel processing of DMA Status Register
		 */
		if (isr1 & 0x03) {
			dmac = &sca->dmac[DMAC_RXCH(mch)];

			dsr = SRC_GET8(hc, dmac->dsr);
			SRC_PUT8(hc, dmac->dsr, dsr);

			/*
			 * End of frame processing (MSG OK?)
			 */
			if (dsr & SCA_DSR_EOM) {
#if BUGGY > 0
				int tt, ind;

#ifndef NETGRAPH
				tt = sc->ifsppp.pp_if.if_ipackets;
#else	/* NETGRAPH */
				tt = sc->ipackets;
#endif /* NETGRAPH */
				ind = sc->rxhind;
#endif

				sr_get_packets(sc);
#if BUGGY > 0
#ifndef NETGRAPH
				if (tt == sc->ifsppp.pp_if.if_ipackets)
#else	/* NETGRAPH */
				if (tt == sc->ipackets)
#endif /* NETGRAPH */
				{
					sca_descriptor *rxdesc;
					int i;

					printf("SR: RXINTR isr1 %x, dsr %x, "
					       "no data %d pkts, orxind %d.\n",
					       dotxstart, dsr, tt, ind);
					printf("SR: rxdesc %x, rxstart %x, "
					       "rxend %x, rxhind %d, "
					       "rxmax %d.\n",
					       sc->rxdesc, sc->rxstart,
					       sc->rxend, sc->rxhind,
					       sc->rxmax);
					printf("SR: cda %x, eda %x.\n",
					    SRC_GET16(hc, dmac->cda),
					    SRC_GET16(hc, dmac->eda));

					if (hc->mempages) {
						SRC_SET_ON(hc);
						SRC_SET_MEM(hc, sc->rxdesc);
					}
					rxdesc = (sca_descriptor *)
					         (hc->mem_start +
					          (sc->rxdesc & hc->winmsk));
					rxdesc = &rxdesc[sc->rxhind];

					for (i = 0; i < 3; i++, rxdesc++)
						printf("SR: rxdesc->stat %x, "
						       "len %d.\n",
						       rxdesc->stat,
						       rxdesc->len);

					if (hc->mempages)
						SRC_SET_OFF(hc);
				}
#endif /* BUGGY */
			}
			/*
			 * Check for Counter overflow
			 */
			if (dsr & SCA_DSR_COF) {
				printf("sr%d: RX DMA Counter overflow, "
				       "rxpkts %lu.\n",
#ifndef NETGRAPH
				       sc->unit, sc->ifsppp.pp_if.if_ipackets);
				sc->ifsppp.pp_if.if_ierrors++;
#else	/* NETGRAPH */
				       sc->unit, sc->ipackets);
				sc->ierrors[1]++;
#endif /* NETGRAPH */
			}
			/*
			 * Check for Buffer overflow
			 */
			if (dsr & SCA_DSR_BOF) {
				printf("sr%d: RX DMA Buffer overflow, "
				       "rxpkts %lu, rxind %d, "
				       "cda %x, eda %x, dsr %x.\n",
#ifndef NETGRAPH
				       sc->unit, sc->ifsppp.pp_if.if_ipackets,
#else	/* NETGRAPH */
				       sc->unit, sc->ipackets,
#endif /* NETGRAPH */
				       sc->rxhind,
				       SRC_GET16(hc, dmac->cda),
				       SRC_GET16(hc, dmac->eda),
				       dsr);

				/*
				 * Make sure we eat as many as possible.
				 * Then get the system running again.
				 */
				if (hc->mempages)
					SRC_SET_ON(hc);

				sr_eat_packet(sc, 0);
#ifndef NETGRAPH
				sc->ifsppp.pp_if.if_ierrors++;
#else	/* NETGRAPH */
				sc->ierrors[2]++;
#endif /* NETGRAPH */

				SRC_PUT8(hc, sca->msci[mch].cmd,
				    SCA_CMD_RXMSGREJ);

				SRC_PUT8(hc, dmac->dsr, SCA_DSR_DE);

#if BUGGY > 0
				printf("sr%d: RX DMA Buffer overflow, "
				       "rxpkts %lu, rxind %d, "
				       "cda %x, eda %x, dsr %x. After\n",
				       sc->unit,
#ifndef NETGRAPH
				       sc->ipackets,
#else	/* NETGRAPH */
				       sc->ifsppp.pp_if.if_ipackets,
#endif /* NETGRAPH */
				       sc->rxhind,
				       SRC_GET16(hc, dmac->cda),
				       SRC_GET16(hc, dmac->eda),
				       SRC_GET8(hc, dmac->dsr));
#endif

				if (hc->mempages)
					SRC_SET_OFF(hc);
			}
			/*
			 * End of Transfer
			 */
			if (dsr & SCA_DSR_EOT) {
				/*
				 * If this happen, it means that we are
				 * receiving faster than what the processor
				 * can handle.
				 * 
				 * XXX We should enable the dma again.
				 */
				printf("sr%d: RX End of xfer, rxpkts %lu.\n",
				       sc->unit,
#ifndef NETGRAPH
				       sc->ifsppp.pp_if.if_ipackets);
				sc->ifsppp.pp_if.if_ierrors++;
#else
				       sc->ipackets);
				sc->ierrors[3]++;
#endif /* NETGRAPH */
			}
		}
		isr1 >>= 4;	/* process next half of ISR */
		mch++;		/* and move to next channel */
	} while ((mch < NCHAN) && isr1);	/* loop for each chn */

	/*
	 * Now that we have done all the urgent things, see if we can fill
	 * the transmit buffers.
	 */
	for (mch = 0; mch < NCHAN; mch++) {
		if (dotxstart & 0x0C) {	/* TX initiation enabled? */
			sc = &hc->sc[mch];
#ifndef NETGRAPH
			srstart(&sc->ifsppp.pp_if);
#else
			srstart(sc);
#endif /* NETGRAPH */
		}
		dotxstart >>= 4;/* shift for next channel */
	}
}
#ifndef NETGRAPH
#ifdef USE_MODEMCK
/*
 * Perform timeout on an FR channel 
 *
 * Establish a periodic check of open N2 ports;  If
 * a port is open/active, its DCD state is checked
 * and a loss of DCD is recognized (and eventually
 * processed).
 */
static void
sr_modemck(void *arg)
{
	u_int s;
	int card;		/* card index in table */
	int cards;		/* card list index */
	int mch;		/* channel on card */
	u_char dcd_v;		/* Data Carrier Detect */
	u_char got_st0;		/* contents of ST0 */
	u_char got_st1;		/* contents of ST1 */
	u_char got_st2;		/* contents of ST2 */
	u_char got_st3;		/* contents of ST3 */
	struct sr_hardc *hc;	/* card's configuration */
	struct sr_hardc *Card[16];/* up to 16 cards in system */
	struct sr_softc *sc;	/* channel's softc structure */
	struct ifnet *ifp;	/* interface control table */
	msci_channel *msci;	/* regs specific to channel */

	s = splimp();

#if	0
	if (sr_opens == 0) {	/* count of "up" channels */
		sr_watcher = 0;	/* indicate no watcher */
		splx(s);
		return;
	}
#endif

	sr_watcher = 1;		/* mark that we're online */

	/*
	 * Now we'll need a list of cards to process.  Since we can handle
	 * both ISA and PCI cards (and I didn't think of making this logic
	 * global YET) we'll generate a single table of card table
	 * addresses.
	 */
	cards = 0;

	for (card = 0; card < NSR; card++) {
		hc = &sr_hardc[card];

		if (hc->sc == (void *)0)
			continue;

		Card[cards++] = hc;
	}

	hc = sr_hardc_pci;

	while (hc) {
		Card[cards++] = hc;
		hc = hc->next;
	}

	/*
	 * OK, we've got work we can do.  Let's do it... (Please note that
	 * this code _only_ deals w/ ISA cards)
	 */
	for (card = 0; card < cards; card++) {
		hc = Card[card];/* get card table */

		for (mch = 0; mch < hc->numports; mch++) {
			sc = &hc->sc[mch];

			ifp = &sc->ifsppp.pp_if;

			/*
			 * if this channel isn't "up", skip it
			 */
			if ((ifp->if_flags & IFF_UP) == 0)
				continue;

			/*
			 * OK, now we can go looking at this channel's
			 * actual register contents...
			 */
			msci = &hc->sca->msci[sc->scachan];

			/*
			 * OK, now we'll look into the actual status of this
			 * channel...
			 * 
			 * I suck in more registers than strictly needed
			 */
			got_st0 = SRC_GET8(hc, msci->st0);
			got_st1 = SRC_GET8(hc, msci->st1);
			got_st2 = SRC_GET8(hc, msci->st2);
			got_st3 = SRC_GET8(hc, msci->st3);

			/*
			 * We want to see if the DCD signal is up (DCD is
			 * true if zero)
			 */
			dcd_v = (got_st3 & SCA_ST3_DCD) == 0;

			if (dcd_v == 0)
				printf("sr%d: DCD lost\n", sc->unit);
		}
	}

	/*
	 * OK, now set up for the next modem signal checking pass...
	 */
	timeout(sr_modemck, NULL, hz);

	splx(s);
}
#endif
#else	/* NETGRAPH */
/*
 * If a port is open/active, it's DCD state is checked
 * and a loss of DCD is recognized (and eventually processed?).
 */
static void
sr_modemck(struct sr_softc *sc )
{
	u_int s;
	u_char got_st3;			/* contents of ST3 */
	struct sr_hardc *hc = sc->hc;	/* card's configuration */
	msci_channel *msci;		/* regs specific to channel */

	s = splimp();


	if (sc->running == 0)
		return;
	/*
	 * OK, now we can go looking at this channel's register contents...
	 */
	msci = &hc->sca->msci[sc->scachan];
	got_st3 = SRC_GET8(hc, msci->st3);

	/*
	 * We want to see if the DCD signal is up (DCD is true if zero)
	 */
	sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
	splx(s);
}

#endif	/* NETGRAPH */
static void
sr_msci_intr(struct sr_hardc *hc, u_char isr0)
{
	printf("src%d: SRINTR: MSCI\n", hc->cunit);
}

static void
sr_timer_intr(struct sr_hardc *hc, u_char isr2)
{
	printf("src%d: SRINTR: TIMER\n", hc->cunit);
}

#ifdef	NETGRAPH
/*****************************************
 * Device timeout/watchdog routine.
 * called once per second.
 * checks to see that if activity was expected, that it hapenned.
 * At present we only look to see if expected output was completed.
 */
static void
ngsr_watchdog_frame(void * arg)
{
	struct sr_softc * sc = arg;
	int s;
	int	speed;

	if (sc->running == 0)
		return; /* if we are not running let timeouts die */
	/*
	 * calculate the apparent throughputs 
	 *  XXX a real hack
	 */
	s = splimp();
	speed = sc->inbytes - sc->lastinbytes;
	sc->lastinbytes = sc->inbytes;
	if ( sc->inrate < speed )
		sc->inrate = speed;
	speed = sc->outbytes - sc->lastoutbytes;
	sc->lastoutbytes = sc->outbytes;
	if ( sc->outrate < speed )
		sc->outrate = speed;
	sc->inlast++;
	splx(s);

	if ((sc->inlast > QUITE_A_WHILE)
	&& (sc->out_deficit > LOTS_OF_PACKETS)) {
		log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
		s = splimp();
		sr_down(sc);
		sr_up(sc);
		sc->inlast = sc->out_deficit = 0;
		splx(s);
	} else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
		if (sc->out_dog == 0) { 
			log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
					sc->unit);
			s = splimp();
			srwatchdog(sc);
#if 0
			sr_down(sc);
			sr_up(sc);
#endif
			splx(s);
			sc->inlast = sc->out_deficit = 0;
		} else {
			sc->out_dog--;
		}
	}
	sr_modemck(sc); 	/* update the DCD status */
	sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
}

/***********************************************************************
 * This section contains the methods for the Netgraph interface
 ***********************************************************************/
/*
 * It is not possible or allowable to create a node of this type.
 * If the hardware exists, it will already have created it.
 */
static	int
ngsr_constructor(node_p node)
{
	return (EINVAL);
}

/*
 * give our ok for a hook to be added...
 * If we are not running this should kick the device into life.
 * The hook's private info points to our stash of info about that
 * channel.
 */
static int
ngsr_newhook(node_p node, hook_p hook, const char *name)
{
	struct sr_softc *	sc = NG_NODE_PRIVATE(node);

	/*
	 * check if it's our friend the debug hook
	 */
	if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
		NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
		sc->debug_hook = hook;
		return (0);
	}

	/*
	 * Check for raw mode hook.
	 */
	if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
		return (EINVAL);
	}
	NG_HOOK_SET_PRIVATE(hook, sc);
	sc->hook = hook;
	sc->datahooks++;
	sr_up(sc);
	return (0);
}

/*
 * incoming messages.
 * Just respond to the generic TEXT_STATUS message
 */
static	int
ngsr_rcvmsg(node_p node, item_p item, hook_p lasthook)
{
	struct sr_softc *	sc;
	struct ng_mesg *resp = NULL;
	int error = 0;
	struct ng_mesg *msg;

	NGI_GET_MSG(item,msg);
	sc = NG_NODE_PRIVATE(node);
	switch (msg->header.typecookie) {
	case	NG_SR_COOKIE: 
		error = EINVAL;
		break;
	case	NGM_GENERIC_COOKIE: 
		switch(msg->header.cmd) {
		case NGM_TEXT_STATUS: {
			char        *arg;
			int pos = 0;

			int resplen = sizeof(struct ng_mesg) + 512;
			NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT);
			if (resp == NULL) {
				error = ENOMEM;
				break;
			}
			arg = (resp)->data;
			pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
			    "highest rate seen: %ld B/S in, %ld B/S out\n",
			sc->inbytes, sc->outbytes,
			sc->inrate, sc->outrate);
			pos += sprintf(arg + pos,
				"%ld output errors\n",
			    	sc->oerrors);
			pos += sprintf(arg + pos,
				"ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
			    	sc->ierrors[0],
			    	sc->ierrors[1],
			    	sc->ierrors[2],
			    	sc->ierrors[3],
			    	sc->ierrors[4],
			    	sc->ierrors[5]);

			resp->header.arglen = pos + 1;
			break;
		      }
	    	default:
		 	error = EINVAL;
		 	break;
		}
		break;
	default:
		error = EINVAL;
		break;
	}
	/* Take care of synchronous response, if any */
	NG_RESPOND_MSG(error, node, item, resp);
	NG_FREE_MSG(msg);
	return (error);
}

/*
 * get data from another node and transmit it to the correct channel
 */
static	int
ngsr_rcvdata(hook_p hook, item_p item)
{
	int s;
	int error = 0;
	struct sr_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
	struct ifqueue	*xmitq_p;
	struct mbuf *m;
	struct ng_tag_prio *ptag;
	
	NGI_GET_M(item, m);
	NG_FREE_ITEM(item);
	/*
	 * data doesn't come in from just anywhere (e.g control hook)
	 */
	if ( NG_HOOK_PRIVATE(hook) == NULL) {
		error = ENETDOWN;
		goto bad;
	}

	/* 
	 * Now queue the data for when it can be sent
	 */
	if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE,
	    NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) )
		xmitq_p = (&sc->xmitq_hipri);
	else
		xmitq_p = (&sc->xmitq);

	s = splimp();
	IF_LOCK(xmitq_p);
	if (_IF_QFULL(xmitq_p)) {
		_IF_DROP(xmitq_p);
		IF_UNLOCK(xmitq_p);
		splx(s);
		error = ENOBUFS;
		goto bad;
	}
	_IF_ENQUEUE(xmitq_p, m);
	IF_UNLOCK(xmitq_p);
	srstart(sc);
	splx(s);
	return (0);

bad:
	/* 
	 * It was an error case.
	 * check if we need to free the mbuf, and then return the error
	 */
	NG_FREE_M(m);
	return (error);
}

/*
 * do local shutdown processing..
 * this node will refuse to go away, unless the hardware says to..
 * don't unref the node, or remove our name. just clear our links up.
 */
static	int
ngsr_shutdown(node_p node)
{
	struct sr_softc * sc = NG_NODE_PRIVATE(node);

	sr_down(sc);
	NG_NODE_UNREF(node);
/* XXX should drain queues! */
	if (ng_make_node_common(&typestruct, &sc->node) != 0)
		return (0);
	sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
	if (ng_name_node(sc->node, sc->nodename)) {
		printf("node naming failed\n");
		sc->node = NULL;
		NG_NODE_UNREF(sc->node); /* drop it again */
		return (0);
	}
	NG_NODE_SET_PRIVATE(sc->node, sc);
	callout_handle_init(&sc->handle); /* should kill timeout */
	sc->running = 0;
	return (0);
}

/* already linked */
static	int
ngsr_connect(hook_p hook)
{
	/* probably not at splnet, force outward queueing */
	NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
	/* be really amiable and just say "YUP that's OK by me! " */
	return (0);
}

/*
 * notify on hook disconnection (destruction)
 *
 * Invalidate the private data associated with this dlci.
 * For this type, removal of the last link resets tries to destroy the node.
 * As the device still exists, the shutdown method will not actually
 * destroy the node, but reset the device and leave it 'fresh' :)
 *
 * The node removal code will remove all references except that owned by the
 * driver. 
 */
static	int
ngsr_disconnect(hook_p hook)
{
	struct sr_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
	int	s;
	/*
	 * If it's the data hook, then free resources etc.
	 */
	if (NG_HOOK_PRIVATE(hook)) {
		s = splimp();
		sc->datahooks--;
		if (sc->datahooks == 0)
			sr_down(sc);
		splx(s);
	} else {
		sc->debug_hook = NULL;
	}
	return (0);
}
#endif /* NETGRAPH */

/*
 ********************************* END ************************************
 */
OpenPOWER on IntegriCloud