summaryrefslogtreecommitdiffstats
path: root/sys/dev/sound/isa/mss.c
blob: cc62df3bbacaf42fce97eb7d1b9506c39bf3775b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
/*-
 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
 * Copyright (c) 1997,1998 Luigi Rizzo
 * Copyright (c) 1994,1995 Hannu Savolainen
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_snd.h"
#endif

#include <dev/sound/pcm/sound.h>

SND_DECLARE_FILE("$FreeBSD$");

/* board-specific include files */
#include <dev/sound/isa/mss.h>
#include <dev/sound/isa/sb.h>
#include <dev/sound/chip.h>

#include <isa/isavar.h>

#include "mixer_if.h"

#define MSS_DEFAULT_BUFSZ (4096)
#define MSS_INDEXED_REGS 0x20
#define OPL_INDEXED_REGS 0x19

struct mss_info;

struct mss_chinfo {
	struct mss_info *parent;
	struct pcm_channel *channel;
	struct snd_dbuf *buffer;
	int dir;
	u_int32_t fmt, blksz;
};

struct mss_info {
    struct resource *io_base;	/* primary I/O address for the board */
    int		     io_rid;
    struct resource *conf_base; /* and the opti931 also has a config space */
    int		     conf_rid;
    struct resource *irq;
    int		     irq_rid;
    struct resource *drq1; /* play */
    int		     drq1_rid;
    struct resource *drq2; /* rec */
    int		     drq2_rid;
    void 	    *ih;
    bus_dma_tag_t    parent_dmat;
    struct mtx	    *lock;

    char mss_indexed_regs[MSS_INDEXED_REGS];
    char opl_indexed_regs[OPL_INDEXED_REGS];
    int bd_id;      /* used to hold board-id info, eg. sb version,
		     * mss codec type, etc. etc.
		     */
    int opti_offset;		/* offset from config_base for opti931 */
    u_long  bd_flags;       /* board-specific flags */
    int optibase;		/* base address for OPTi9xx config */
    struct resource *indir;	/* Indirect register index address */
    int indir_rid;
    int password;		/* password for opti9xx cards */
    int passwdreg;		/* password register */
    unsigned int bufsize;
    struct mss_chinfo pch, rch;
};

static int 		mss_probe(device_t dev);
static int 		mss_attach(device_t dev);

static driver_intr_t 	mss_intr;

/* prototypes for local functions */
static int 		mss_detect(device_t dev, struct mss_info *mss);
#ifndef PC98
static int		opti_detect(device_t dev, struct mss_info *mss);
#endif
static char 		*ymf_test(device_t dev, struct mss_info *mss);
static void		ad_unmute(struct mss_info *mss);

/* mixer set funcs */
static int 		mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
static int 		mss_set_recsrc(struct mss_info *mss, int mask);

/* io funcs */
static int 		ad_wait_init(struct mss_info *mss, int x);
static int 		ad_read(struct mss_info *mss, int reg);
static void 		ad_write(struct mss_info *mss, int reg, u_char data);
static void 		ad_write_cnt(struct mss_info *mss, int reg, u_short data);
static void    		ad_enter_MCE(struct mss_info *mss);
static void             ad_leave_MCE(struct mss_info *mss);

/* OPTi-specific functions */
static void		opti_write(struct mss_info *mss, u_char reg,
				   u_char data);
#ifndef PC98
static u_char		opti_read(struct mss_info *mss, u_char reg);
#endif
static int		opti_init(device_t dev, struct mss_info *mss);

/* io primitives */
static void 		conf_wr(struct mss_info *mss, u_char reg, u_char data);
static u_char 		conf_rd(struct mss_info *mss, u_char reg);

static int 		pnpmss_probe(device_t dev);
static int 		pnpmss_attach(device_t dev);

static driver_intr_t 	opti931_intr;

static u_int32_t mss_fmt[] = {
	SND_FORMAT(AFMT_U8, 1, 0),
	SND_FORMAT(AFMT_U8, 2, 0),
	SND_FORMAT(AFMT_S16_LE, 1, 0),
	SND_FORMAT(AFMT_S16_LE, 2, 0),
	SND_FORMAT(AFMT_MU_LAW, 1, 0),
	SND_FORMAT(AFMT_MU_LAW, 2, 0),
	SND_FORMAT(AFMT_A_LAW, 1, 0),
	SND_FORMAT(AFMT_A_LAW, 2, 0),
	0
};
static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};

static u_int32_t guspnp_fmt[] = {
	SND_FORMAT(AFMT_U8, 1, 0),
	SND_FORMAT(AFMT_U8, 2, 0),
	SND_FORMAT(AFMT_S16_LE, 1, 0),
	SND_FORMAT(AFMT_S16_LE, 2, 0),
	SND_FORMAT(AFMT_A_LAW, 1, 0),
	SND_FORMAT(AFMT_A_LAW, 2, 0),
	0
};
static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};

static u_int32_t opti931_fmt[] = {
	SND_FORMAT(AFMT_U8, 1, 0),
	SND_FORMAT(AFMT_U8, 2, 0),
	SND_FORMAT(AFMT_S16_LE, 1, 0),
	SND_FORMAT(AFMT_S16_LE, 2, 0),
	0
};
static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};

#define MD_AD1848	0x91
#define MD_AD1845	0x92
#define MD_CS42XX	0xA1
#define MD_CS423X	0xA2
#define MD_OPTI930	0xB0
#define	MD_OPTI931	0xB1
#define MD_OPTI925	0xB2
#define MD_OPTI924	0xB3
#define	MD_GUSPNP	0xB8
#define MD_GUSMAX	0xB9
#define	MD_YM0020	0xC1
#define	MD_VIVO		0xD1

#define	DV_F_TRUE_MSS	0x00010000	/* mss _with_ base regs */

#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)

static void
mss_lock(struct mss_info *mss)
{
	snd_mtxlock(mss->lock);
}

static void
mss_unlock(struct mss_info *mss)
{
	snd_mtxunlock(mss->lock);
}

static int
port_rd(struct resource *port, int off)
{
	if (port)
		return bus_space_read_1(rman_get_bustag(port),
					rman_get_bushandle(port),
					off);
	else
		return -1;
}

static void
port_wr(struct resource *port, int off, u_int8_t data)
{
	if (port)
		bus_space_write_1(rman_get_bustag(port),
				  rman_get_bushandle(port),
				  off, data);
}

static int
io_rd(struct mss_info *mss, int reg)
{
	if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
	return port_rd(mss->io_base, reg);
}

static void
io_wr(struct mss_info *mss, int reg, u_int8_t data)
{
	if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
	port_wr(mss->io_base, reg, data);
}

static void
conf_wr(struct mss_info *mss, u_char reg, u_char value)
{
    	port_wr(mss->conf_base, 0, reg);
    	port_wr(mss->conf_base, 1, value);
}

static u_char
conf_rd(struct mss_info *mss, u_char reg)
{
	port_wr(mss->conf_base, 0, reg);
    	return port_rd(mss->conf_base, 1);
}

static void
opti_wr(struct mss_info *mss, u_char reg, u_char value)
{
    	port_wr(mss->conf_base, mss->opti_offset + 0, reg);
    	port_wr(mss->conf_base, mss->opti_offset + 1, value);
}

static u_char
opti_rd(struct mss_info *mss, u_char reg)
{
	port_wr(mss->conf_base, mss->opti_offset + 0, reg);
    	return port_rd(mss->conf_base, mss->opti_offset + 1);
}

static void
gus_wr(struct mss_info *mss, u_char reg, u_char value)
{
    	port_wr(mss->conf_base, 3, reg);
    	port_wr(mss->conf_base, 5, value);
}

static u_char
gus_rd(struct mss_info *mss, u_char reg)
{
    	port_wr(mss->conf_base, 3, reg);
    	return port_rd(mss->conf_base, 5);
}

static void
mss_release_resources(struct mss_info *mss, device_t dev)
{
    	if (mss->irq) {
    		if (mss->ih)
			bus_teardown_intr(dev, mss->irq, mss->ih);
 		bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
				     mss->irq);
		mss->irq = 0;
    	}
    	if (mss->drq2) {
		if (mss->drq2 != mss->drq1) {
			isa_dma_release(rman_get_start(mss->drq2));
			bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
				     	mss->drq2);
		}
		mss->drq2 = 0;
    	}
     	if (mss->drq1) {
		isa_dma_release(rman_get_start(mss->drq1));
		bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
				     mss->drq1);
		mss->drq1 = 0;
    	}
   	if (mss->io_base) {
		bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
				     mss->io_base);
		mss->io_base = 0;
    	}
    	if (mss->conf_base) {
		bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
				     mss->conf_base);
		mss->conf_base = 0;
    	}
	if (mss->indir) {
		bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
				     mss->indir);
		mss->indir = 0;
	}
    	if (mss->parent_dmat) {
		bus_dma_tag_destroy(mss->parent_dmat);
		mss->parent_dmat = 0;
    	}
	if (mss->lock) snd_mtxfree(mss->lock);

     	free(mss, M_DEVBUF);
}

static int
mss_alloc_resources(struct mss_info *mss, device_t dev)
{
    	int pdma, rdma, ok = 1;
	if (!mss->io_base)
    		mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
						      &mss->io_rid, RF_ACTIVE);
	if (!mss->irq)
    		mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
						  &mss->irq_rid, RF_ACTIVE);
	if (!mss->drq1)
    		mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
						   &mss->drq1_rid,
						   RF_ACTIVE);
    	if (mss->conf_rid >= 0 && !mss->conf_base)
        	mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
							&mss->conf_rid,
							RF_ACTIVE);
    	if (mss->drq2_rid >= 0 && !mss->drq2)
        	mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
						   &mss->drq2_rid,
						   RF_ACTIVE);

	if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
	if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
	if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;

	if (ok) {
		pdma = rman_get_start(mss->drq1);
		isa_dma_acquire(pdma);
		isa_dmainit(pdma, mss->bufsize);
		mss->bd_flags &= ~BD_F_DUPLEX;
		if (mss->drq2) {
			rdma = rman_get_start(mss->drq2);
			isa_dma_acquire(rdma);
			isa_dmainit(rdma, mss->bufsize);
			mss->bd_flags |= BD_F_DUPLEX;
		} else mss->drq2 = mss->drq1;
	}
    	return ok;
}

/*
 * The various mixers use a variety of bitmasks etc. The Voxware
 * driver had a very nice technique to describe a mixer and interface
 * to it. A table defines, for each channel, which register, bits,
 * offset, polarity to use. This procedure creates the new value
 * using the table and the old value.
 */

static void
change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
{
    	u_char mask;
    	int shift;

    	DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
		"r %d p %d bit %d off %d\n",
		dev, chn, newval, *regval,
		(*t)[dev][chn].regno, (*t)[dev][chn].polarity,
		(*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );

    	if ( (*t)[dev][chn].polarity == 1)	/* reverse */
		newval = 100 - newval ;

    	mask = (1 << (*t)[dev][chn].nbits) - 1;
    	newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
    	shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;

    	*regval &= ~(mask << shift);        /* Filter out the previous value */
    	*regval |= (newval & mask) << shift;        /* Set the new value */
}

/* -------------------------------------------------------------------- */
/* only one source can be set... */
static int
mss_set_recsrc(struct mss_info *mss, int mask)
{
    	u_char   recdev;

    	switch (mask) {
    	case SOUND_MASK_LINE:
    	case SOUND_MASK_LINE3:
		recdev = 0;
		break;

    	case SOUND_MASK_CD:
    	case SOUND_MASK_LINE1:
		recdev = 0x40;
		break;

    	case SOUND_MASK_IMIX:
		recdev = 0xc0;
		break;

    	case SOUND_MASK_MIC:
    	default:
		mask = SOUND_MASK_MIC;
		recdev = 0x80;
    	}
    	ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
    	ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
    	return mask;
}

/* there are differences in the mixer depending on the actual sound card. */
static int
mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
{
    	int        regoffs;
    	mixer_tab *mix_d;
    	u_char     old, val;

	switch (mss->bd_id) {
		case MD_OPTI931:
			mix_d = &opti931_devices;
			break;
		case MD_OPTI930:
			mix_d = &opti930_devices;
			break;
		default:
			mix_d = &mix_devices;
	}

    	if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
		DEB(printf("nbits = 0 for dev %d\n", dev));
		return -1;
    	}

    	if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */

    	/* Set the left channel */

    	regoffs = (*mix_d)[dev][LEFT_CHN].regno;
    	old = val = ad_read(mss, regoffs);
    	/* if volume is 0, mute chan. Otherwise, unmute. */
    	if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
    	change_bits(mix_d, &val, dev, LEFT_CHN, left);
    	ad_write(mss, regoffs, val);

    	DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
		dev, regoffs, old, val));

    	if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
		/* Set the right channel */
		regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
		old = val = ad_read(mss, regoffs);
		if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
		change_bits(mix_d, &val, dev, RIGHT_CHN, right);
		ad_write(mss, regoffs, val);

		DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
	    	dev, regoffs, old, val));
    	}
    	return 0; /* success */
}

/* -------------------------------------------------------------------- */

static int
mssmix_init(struct snd_mixer *m)
{
	struct mss_info *mss = mix_getdevinfo(m);

	mix_setdevs(m, MODE2_MIXER_DEVICES);
	mix_setrecdevs(m, MSS_REC_DEVICES);
	switch(mss->bd_id) {
	case MD_OPTI930:
		mix_setdevs(m, OPTI930_MIXER_DEVICES);
		break;

	case MD_OPTI931:
		mix_setdevs(m, OPTI931_MIXER_DEVICES);
		mss_lock(mss);
		ad_write(mss, 20, 0x88);
		ad_write(mss, 21, 0x88);
		mss_unlock(mss);
		break;

	case MD_AD1848:
		mix_setdevs(m, MODE1_MIXER_DEVICES);
		break;

	case MD_GUSPNP:
	case MD_GUSMAX:
		/* this is only necessary in mode 3 ... */
		mss_lock(mss);
		ad_write(mss, 22, 0x88);
		ad_write(mss, 23, 0x88);
		mss_unlock(mss);
		break;
	}
	return 0;
}

static int
mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
{
	struct mss_info *mss = mix_getdevinfo(m);

	mss_lock(mss);
	mss_mixer_set(mss, dev, left, right);
	mss_unlock(mss);

	return left | (right << 8);
}

static u_int32_t
mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
{
	struct mss_info *mss = mix_getdevinfo(m);

	mss_lock(mss);
	src = mss_set_recsrc(mss, src);
	mss_unlock(mss);
	return src;
}

static kobj_method_t mssmix_mixer_methods[] = {
    	KOBJMETHOD(mixer_init,		mssmix_init),
    	KOBJMETHOD(mixer_set,		mssmix_set),
    	KOBJMETHOD(mixer_setrecsrc,	mssmix_setrecsrc),
	KOBJMETHOD_END
};
MIXER_DECLARE(mssmix_mixer);

/* -------------------------------------------------------------------- */

static int
ymmix_init(struct snd_mixer *m)
{
	struct mss_info *mss = mix_getdevinfo(m);

	mssmix_init(m);
	mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
				      | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
	/* Set master volume */
	mss_lock(mss);
	conf_wr(mss, OPL3SAx_VOLUMEL, 7);
	conf_wr(mss, OPL3SAx_VOLUMER, 7);
	mss_unlock(mss);

	return 0;
}

static int
ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
{
	struct mss_info *mss = mix_getdevinfo(m);
	int t, l, r;

	mss_lock(mss);
	switch (dev) {
	case SOUND_MIXER_VOLUME:
		if (left) t = 15 - (left * 15) / 100;
		else t = 0x80; /* mute */
		conf_wr(mss, OPL3SAx_VOLUMEL, t);
		if (right) t = 15 - (right * 15) / 100;
		else t = 0x80; /* mute */
		conf_wr(mss, OPL3SAx_VOLUMER, t);
		break;

	case SOUND_MIXER_MIC:
		t = left;
		if (left) t = 31 - (left * 31) / 100;
		else t = 0x80; /* mute */
		conf_wr(mss, OPL3SAx_MIC, t);
		break;

	case SOUND_MIXER_BASS:
		l = (left * 7) / 100;
		r = (right * 7) / 100;
		t = (r << 4) | l;
		conf_wr(mss, OPL3SAx_BASS, t);
		break;

	case SOUND_MIXER_TREBLE:
		l = (left * 7) / 100;
		r = (right * 7) / 100;
		t = (r << 4) | l;
		conf_wr(mss, OPL3SAx_TREBLE, t);
		break;

	default:
		mss_mixer_set(mss, dev, left, right);
	}
	mss_unlock(mss);

	return left | (right << 8);
}

static u_int32_t
ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
{
	struct mss_info *mss = mix_getdevinfo(m);
	mss_lock(mss);
	src = mss_set_recsrc(mss, src);
	mss_unlock(mss);
	return src;
}

static kobj_method_t ymmix_mixer_methods[] = {
    	KOBJMETHOD(mixer_init,		ymmix_init),
    	KOBJMETHOD(mixer_set,		ymmix_set),
    	KOBJMETHOD(mixer_setrecsrc,	ymmix_setrecsrc),
	KOBJMETHOD_END
};
MIXER_DECLARE(ymmix_mixer);

/* -------------------------------------------------------------------- */
/*
 * XXX This might be better off in the gusc driver.
 */
static void
gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
{
	static const unsigned char irq_bits[16] = {
		0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
	};
	static const unsigned char dma_bits[8] = {
		0, 1, 0, 2, 0, 3, 4, 5
	};
	device_t parent = device_get_parent(dev);
	unsigned char irqctl, dmactl;
	int s;

	s = splhigh();

	port_wr(alt, 0x0f, 0x05);
	port_wr(alt, 0x00, 0x0c);
	port_wr(alt, 0x0b, 0x00);

	port_wr(alt, 0x0f, 0x00);

	irqctl = irq_bits[isa_get_irq(parent)];
	/* Share the IRQ with the MIDI driver.  */
	irqctl |= 0x40;
	dmactl = dma_bits[isa_get_drq(parent)];
	if (device_get_flags(parent) & DV_F_DUAL_DMA)
		dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
		    << 3;

	/*
	 * Set the DMA and IRQ control latches.
	 */
	port_wr(alt, 0x00, 0x0c);
	port_wr(alt, 0x0b, dmactl | 0x80);
	port_wr(alt, 0x00, 0x4c);
	port_wr(alt, 0x0b, irqctl);

	port_wr(alt, 0x00, 0x0c);
	port_wr(alt, 0x0b, dmactl);
	port_wr(alt, 0x00, 0x4c);
	port_wr(alt, 0x0b, irqctl);

	port_wr(mss->conf_base, 2, 0);
	port_wr(alt, 0x00, 0x0c);
	port_wr(mss->conf_base, 2, 0);

	splx(s);
}

static int
mss_init(struct mss_info *mss, device_t dev)
{
       	u_char r6, r9;
	struct resource *alt;
	int rid, tmp;

	mss->bd_flags |= BD_F_MCE_BIT;
	switch(mss->bd_id) {
	case MD_OPTI931:
		/*
		 * The MED3931 v.1.0 allocates 3 bytes for the config
		 * space, whereas v.2.0 allocates 4 bytes. What I know
		 * for sure is that the upper two ports must be used,
		 * and they should end on a boundary of 4 bytes. So I
		 * need the following trick.
		 */
		mss->opti_offset =
			(rman_get_start(mss->conf_base) & ~3) + 2
			- rman_get_start(mss->conf_base);
		BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
    		opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
    		ad_write(mss, 10, 2); /* enable interrupts */
    		opti_wr(mss, 6, 2);  /* MCIR6: mss enable, sb disable */
    		opti_wr(mss, 5, 0x28);  /* MCIR5: codec in exp. mode,fifo */
		break;

	case MD_GUSPNP:
	case MD_GUSMAX:
		gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
    		DELAY(1000 * 30);
    		/* release reset  and enable DAC */
    		gus_wr(mss, 0x4c /* _URSTI */, 3);
    		DELAY(1000 * 30);
    		/* end of reset */

		rid = 0;
    		alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
					     RF_ACTIVE);
		if (alt == NULL) {
			printf("XXX couldn't init GUS PnP/MAX\n");
			break;
		}
    		port_wr(alt, 0, 0xC); /* enable int and dma */
		if (mss->bd_id == MD_GUSMAX)
			gusmax_setup(mss, dev, alt);
		bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);

    		/*
     		 * unmute left & right line. Need to go in mode3, unmute,
     		 * and back to mode 2
     		 */
    		tmp = ad_read(mss, 0x0c);
    		ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
    		ad_write(mss, 0x19, 0); /* unmute left */
    		ad_write(mss, 0x1b, 0); /* unmute right */
    		ad_write(mss, 0x0c, tmp); /* restore old mode */

    		/* send codec interrupts on irq1 and only use that one */
    		gus_wr(mss, 0x5a, 0x4f);

    		/* enable access to hidden regs */
    		tmp = gus_rd(mss, 0x5b /* IVERI */);
    		gus_wr(mss, 0x5b, tmp | 1);
    		BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
		break;

    	case MD_YM0020:
         	conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
        	r6 = conf_rd(mss, OPL3SAx_DMACONF);
        	r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
        	BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
		/* yamaha - set volume to max */
		conf_wr(mss, OPL3SAx_VOLUMEL, 0);
		conf_wr(mss, OPL3SAx_VOLUMER, 0);
		conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
		break;
 	}
    	if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
    		ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
	ad_enter_MCE(mss);
    	ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
    	ad_leave_MCE(mss);
	ad_write(mss, 10, 2); /* int enable */
    	io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
    	/* the following seem required on the CS4232 */
    	ad_unmute(mss);
	return 0;
}


/*
 * main irq handler for the CS423x. The OPTi931 code is
 * a separate one.
 * The correct way to operate for a device with multiple internal
 * interrupt sources is to loop on the status register and ack
 * interrupts until all interrupts are served and none are reported. At
 * this point the IRQ line to the ISA IRQ controller should go low
 * and be raised at the next interrupt.
 *
 * Since the ISA IRQ controller is sent EOI _before_ passing control
 * to the isr, it might happen that we serve an interrupt early, in
 * which case the status register at the next interrupt should just
 * say that there are no more interrupts...
 */

static void
mss_intr(void *arg)
{
    	struct mss_info *mss = arg;
    	u_char c = 0, served = 0;
    	int i;

    	DEB(printf("mss_intr\n"));
	mss_lock(mss);
    	ad_read(mss, 11); /* fake read of status bits */

    	/* loop until there are interrupts, but no more than 10 times. */
    	for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
		/* get exact reason for full-duplex boards */
		c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
		c &= ~served;
		if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
	    		served |= 0x10;
			mss_unlock(mss);
	    		chn_intr(mss->pch.channel);
			mss_lock(mss);
		}
		if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
	    		served |= 0x20;
			mss_unlock(mss);
	    		chn_intr(mss->rch.channel);
			mss_lock(mss);
		}
		/* now ack the interrupt */
		if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
		else io_wr(mss, MSS_STATUS, 0);	/* Clear interrupt status */
    	}
    	if (i == 10) {
		BVDDB(printf("mss_intr: irq, but not from mss\n"));
	} else if (served == 0) {
		BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
		/*
	 	* this should not happen... I have no idea what to do now.
	 	* maybe should do a sanity check and restart dmas ?
	 	*/
		io_wr(mss, MSS_STATUS, 0);	/* Clear interrupt status */
    	}
	mss_unlock(mss);
}

/*
 * AD_WAIT_INIT waits if we are initializing the board and
 * we cannot modify its settings
 */
static int
ad_wait_init(struct mss_info *mss, int x)
{
    	int arg = x, n = 0; /* to shut up the compiler... */
    	for (; x > 0; x--)
		if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
		else return n;
    	printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
    	return n;
}

static int
ad_read(struct mss_info *mss, int reg)
{
    	int             x;

    	ad_wait_init(mss, 201000);
    	x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
    	io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
    	x = io_rd(mss, MSS_IDATA);
	/* printf("ad_read %d, %x\n", reg, x); */
    	return x;
}

static void
ad_write(struct mss_info *mss, int reg, u_char data)
{
    	int x;

	/* printf("ad_write %d, %x\n", reg, data); */
    	ad_wait_init(mss, 1002000);
    	x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
    	io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
    	io_wr(mss, MSS_IDATA, data);
}

static void
ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
{
    	ad_write(mss, reg+1, cnt & 0xff);
    	ad_write(mss, reg, cnt >> 8); /* upper base must be last */
}

static void
wait_for_calibration(struct mss_info *mss)
{
    	int t;

    	/*
     	 * Wait until the auto calibration process has finished.
     	 *
     	 * 1) Wait until the chip becomes ready (reads don't return 0x80).
     	 * 2) Wait until the ACI bit of I11 gets on
     	 * 3) Wait until the ACI bit of I11 gets off
     	 */

    	t = ad_wait_init(mss, 1000000);
    	if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");

	/*
	 * The calibration mode for chips that support it is set so that
	 * we never see ACI go on.
	 */
	if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
		for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
	} else {
       		/*
		 * XXX This should only be enabled for cards that *really*
		 * need it.  Are there any?
		 */
  		for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
	}
    	for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
}

static void
ad_unmute(struct mss_info *mss)
{
    	ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
    	ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
}

static void
ad_enter_MCE(struct mss_info *mss)
{
    	int prev;

    	mss->bd_flags |= BD_F_MCE_BIT;
    	ad_wait_init(mss, 203000);
    	prev = io_rd(mss, MSS_INDEX);
    	prev &= ~MSS_TRD;
    	io_wr(mss, MSS_INDEX, prev | MSS_MCE);
}

static void
ad_leave_MCE(struct mss_info *mss)
{
    	u_char   prev;

    	if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
		DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
		return;
    	}

    	ad_wait_init(mss, 1000000);

    	mss->bd_flags &= ~BD_F_MCE_BIT;

    	prev = io_rd(mss, MSS_INDEX);
    	prev &= ~MSS_TRD;
    	io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
    	wait_for_calibration(mss);
}

static int
mss_speed(struct mss_chinfo *ch, int speed)
{
    	struct mss_info *mss = ch->parent;
    	/*
     	* In the CS4231, the low 4 bits of I8 are used to hold the
     	* sample rate.  Only a fixed number of values is allowed. This
     	* table lists them. The speed-setting routines scans the table
     	* looking for the closest match. This is the only supported method.
     	*
     	* In the CS4236, there is an alternate metod (which we do not
     	* support yet) which provides almost arbitrary frequency setting.
     	* In the AD1845, it looks like the sample rate can be
     	* almost arbitrary, and written directly to a register.
     	* In the OPTi931, there is a SB command which provides for
     	* almost arbitrary frequency setting.
     	*
     	*/
    	ad_enter_MCE(mss);
    	if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
		ad_write(mss, 22, (speed >> 8) & 0xff);	/* Speed MSB */
		ad_write(mss, 23, speed & 0xff);	/* Speed LSB */
		/* XXX must also do something in I27 for the ad1845 */
    	} else {
        	int i, sel = 0; /* assume entry 0 does not contain -1 */
        	static int speeds[] =
      	    	{8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
	    	-1, 37800, -1, 44100, 48000, 33075, 9600, 6615};

        	for (i = 1; i < 16; i++)
   		    	if (speeds[i] > 0 &&
			    abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
        	speed = speeds[sel];
        	ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
		ad_wait_init(mss, 10000);
    	}
    	ad_leave_MCE(mss);

    	return speed;
}

/*
 * mss_format checks that the format is supported (or defaults to AFMT_U8)
 * and returns the bit setting for the 1848 register corresponding to
 * the desired format.
 *
 * fixed lr970724
 */

static int
mss_format(struct mss_chinfo *ch, u_int32_t format)
{
    	struct mss_info *mss = ch->parent;
    	int i, arg = AFMT_ENCODING(format);

    	/*
     	* The data format uses 3 bits (just 2 on the 1848). For each
     	* bit setting, the following array returns the corresponding format.
     	* The code scans the array looking for a suitable format. In
     	* case it is not found, default to AFMT_U8 (not such a good
     	* choice, but let's do it for compatibility...).
     	*/

    	static int fmts[] =
        	{AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
		-1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};

	ch->fmt = format;
    	for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
    	arg = i << 1;
    	if (AFMT_CHANNEL(format) > 1) arg |= 1;
    	arg <<= 4;
    	ad_enter_MCE(mss);
    	ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
	ad_wait_init(mss, 10000);
    	if (ad_read(mss, 12) & 0x40) {	/* mode2? */
		ad_write(mss, 28, arg); /* capture mode */
		ad_wait_init(mss, 10000);
	}
    	ad_leave_MCE(mss);
    	return format;
}

static int
mss_trigger(struct mss_chinfo *ch, int go)
{
    	struct mss_info *mss = ch->parent;
    	u_char m;
    	int retry, wr, cnt, ss;

	ss = 1;
	ss <<= (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
	ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;

	wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
    	m = ad_read(mss, 9);
    	switch (go) {
    	case PCMTRIG_START:
		cnt = (ch->blksz / ss) - 1;

		DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
		m |= wr? I9_PEN : I9_CEN; /* enable DMA */
		ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
		break;

    	case PCMTRIG_STOP:
    	case PCMTRIG_ABORT: /* XXX check this... */
		m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
#if 0
		/*
	 	* try to disable DMA by clearing count registers. Not sure it
	 	* is needed, and it might cause false interrupts when the
	 	* DMA is re-enabled later.
	 	*/
		ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
#endif
    	}
    	/* on the OPTi931 the enable bit seems hard to set... */
    	for (retry = 10; retry > 0; retry--) {
        	ad_write(mss, 9, m);
        	if (ad_read(mss, 9) == m) break;
    	}
    	if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
			       m, ad_read(mss, 9)));
    	return 0;
}


/*
 * the opti931 seems to miss interrupts when working in full
 * duplex, so we try some heuristics to catch them.
 */
static void
opti931_intr(void *arg)
{
    	struct mss_info *mss = (struct mss_info *)arg;
    	u_char masked = 0, i11, mc11, c = 0;
    	u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
    	int loops = 10;

#if 0
    	reason = io_rd(mss, MSS_STATUS);
    	if (!(reason & 1)) {/* no int, maybe a shared line ? */
		DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
		return;
    	}
#endif
	mss_lock(mss);
    	i11 = ad_read(mss, 11); /* XXX what's for ? */
	again:

    	c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
    	mc11 &= 0x0c;
    	if (c & 0x10) {
		DEB(printf("Warning: CD interrupt\n");)
		mc11 |= 0x10;
    	}
    	if (c & 0x20) {
		DEB(printf("Warning: MPU interrupt\n");)
		mc11 |= 0x20;
    	}
    	if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
                              	  mc11, masked));
    	masked |= mc11;
    	/*
     	* the nice OPTi931 sets the IRQ line before setting the bits in
     	* mc11. So, on some occasions I have to retry (max 10 times).
     	*/
    	if (mc11 == 0) { /* perhaps can return ... */
		reason = io_rd(mss, MSS_STATUS);
		if (reason & 1) {
	    		DEB(printf("one more try...\n");)
	    		if (--loops) goto again;
	    		else BVDDB(printf("intr, but mc11 not set\n");)
		}
		if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
		mss_unlock(mss);
		return;
    	}

    	if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
		mss_unlock(mss);
		chn_intr(mss->rch.channel);
		mss_lock(mss);
	}
    	if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
		mss_unlock(mss);
		chn_intr(mss->pch.channel);
		mss_lock(mss);
	}
    	opti_wr(mss, 11, ~mc11); /* ack */
    	if (--loops) goto again;
	mss_unlock(mss);
    	DEB(printf("xxx too many loops\n");)
}

/* -------------------------------------------------------------------- */
/* channel interface */
static void *
msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
{
	struct mss_info *mss = devinfo;
	struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;

	ch->parent = mss;
	ch->channel = c;
	ch->buffer = b;
	ch->dir = dir;
	if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
		return NULL;
	sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
	return ch;
}

static int
msschan_setformat(kobj_t obj, void *data, u_int32_t format)
{
	struct mss_chinfo *ch = data;
	struct mss_info *mss = ch->parent;

	mss_lock(mss);
	mss_format(ch, format);
	mss_unlock(mss);
	return 0;
}

static u_int32_t
msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
{
	struct mss_chinfo *ch = data;
	struct mss_info *mss = ch->parent;
	u_int32_t r;

	mss_lock(mss);
	r = mss_speed(ch, speed);
	mss_unlock(mss);

	return r;
}

static u_int32_t
msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
{
	struct mss_chinfo *ch = data;

	ch->blksz = blocksize;
	sndbuf_resize(ch->buffer, 2, ch->blksz);

	return ch->blksz;
}

static int
msschan_trigger(kobj_t obj, void *data, int go)
{
	struct mss_chinfo *ch = data;
	struct mss_info *mss = ch->parent;

	if (!PCMTRIG_COMMON(go))
		return 0;

	sndbuf_dma(ch->buffer, go);
	mss_lock(mss);
	mss_trigger(ch, go);
	mss_unlock(mss);
	return 0;
}

static u_int32_t
msschan_getptr(kobj_t obj, void *data)
{
	struct mss_chinfo *ch = data;
	return sndbuf_dmaptr(ch->buffer);
}

static struct pcmchan_caps *
msschan_getcaps(kobj_t obj, void *data)
{
	struct mss_chinfo *ch = data;

	switch(ch->parent->bd_id) {
	case MD_OPTI931:
		return &opti931_caps;
		break;

	case MD_GUSPNP:
	case MD_GUSMAX:
		return &guspnp_caps;
		break;

	default:
		return &mss_caps;
		break;
	}
}

static kobj_method_t msschan_methods[] = {
    	KOBJMETHOD(channel_init,		msschan_init),
    	KOBJMETHOD(channel_setformat,		msschan_setformat),
    	KOBJMETHOD(channel_setspeed,		msschan_setspeed),
    	KOBJMETHOD(channel_setblocksize,	msschan_setblocksize),
    	KOBJMETHOD(channel_trigger,		msschan_trigger),
    	KOBJMETHOD(channel_getptr,		msschan_getptr),
    	KOBJMETHOD(channel_getcaps,		msschan_getcaps),
	KOBJMETHOD_END
};
CHANNEL_DECLARE(msschan);

/* -------------------------------------------------------------------- */

/*
 * mss_probe() is the probe routine. Note, it is not necessary to
 * go through this for PnP devices, since they are already
 * indentified precisely using their PnP id.
 *
 * The base address supplied in the device refers to the old MSS
 * specs where the four 4 registers in io space contain configuration
 * information. Some boards (as an example, early MSS boards)
 * has such a block of registers, whereas others (generally CS42xx)
 * do not.  In order to distinguish between the two and do not have
 * to supply two separate probe routines, the flags entry in isa_device
 * has a bit to mark this.
 *
 */

static int
mss_probe(device_t dev)
{
    	u_char tmp, tmpx;
    	int flags, irq, drq, result = ENXIO, setres = 0;
    	struct mss_info *mss;

    	if (isa_get_logicalid(dev)) return ENXIO; /* not yet */

    	mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
    	if (!mss) return ENXIO;

    	mss->io_rid = 0;
    	mss->conf_rid = -1;
    	mss->irq_rid = 0;
    	mss->drq1_rid = 0;
    	mss->drq2_rid = -1;
    	mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
				      	0, ~0, 8, RF_ACTIVE);
    	if (!mss->io_base) {
        	BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
		mss->io_rid = 0;
		/* XXX verify this */
		setres = 1;
		bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
    		         	0x530, 8);
		mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
					  	0, ~0, 8, RF_ACTIVE);
    	}
    	if (!mss->io_base) goto no;

    	/* got irq/dma regs? */
    	flags = device_get_flags(dev);
    	irq = isa_get_irq(dev);
    	drq = isa_get_drq(dev);

    	if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;

    	/*
     	* Check if the IO port returns valid signature. The original MS
     	* Sound system returns 0x04 while some cards
     	* (AudioTriX Pro for example) return 0x00 or 0x0f.
     	*/

    	device_set_desc(dev, "MSS");
    	tmpx = tmp = io_rd(mss, 3);
    	if (tmp == 0xff) {	/* Bus float */
		BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
		device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
		goto mss_probe_end;
    	}
    	tmp &= 0x3f;
    	if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00 || tmp == 0x05)) {
		BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
		     	rman_get_start(mss->io_base), tmpx));
		goto no;
    	}
#ifdef PC98
    	if (irq > 12) {
#else
    	if (irq > 11) {
#endif
		printf("MSS: Bad IRQ %d\n", irq);
		goto no;
    	}
    	if (!(drq == 0 || drq == 1 || drq == 3)) {
		printf("MSS: Bad DMA %d\n", drq);
		goto no;
    	}
    	if (tmpx & 0x80) {
		/* 8-bit board: only drq1/3 and irq7/9 */
		if (drq == 0) {
		    	printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
		    	goto no;
		}
		if (!(irq == 7 || irq == 9)) {
		    	printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
			       irq);
		    	goto no;
		}
    	}
	mss_probe_end:
    	result = mss_detect(dev, mss);
	no:
    	mss_release_resources(mss, dev);
#if 0
    	if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
    				    	SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
#endif
    	return result;
}

static int
mss_detect(device_t dev, struct mss_info *mss)
{
    	int          i;
    	u_char       tmp = 0, tmp1, tmp2;
    	char        *name, *yamaha;

    	if (mss->bd_id != 0) {
		device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
		      	device_get_desc(dev));
		return 0;
    	}

    	name = "AD1848";
    	mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */

#ifndef PC98
	if (opti_detect(dev, mss)) {
		switch (mss->bd_id) {
			case MD_OPTI924:
				name = "OPTi924";
				break;
			case MD_OPTI930:
				name = "OPTi930";
				break;
		}
		printf("Found OPTi device %s\n", name);
		if (opti_init(dev, mss) == 0) goto gotit;
	}
#endif

   	/*
     	* Check that the I/O address is in use.
     	*
     	* bit 7 of the base I/O port is known to be 0 after the chip has
     	* performed its power on initialization. Just assume this has
     	* happened before the OS is starting.
     	*
     	* If the I/O address is unused, it typically returns 0xff.
     	*/

    	for (i = 0; i < 10; i++)
		if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
		else break;

    	if (i >= 10) {	/* Not an AD1848 */
		BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
		goto no;
    	}
    	/*
     	* Test if it's possible to change contents of the indirect
     	* registers. Registers 0 and 1 are ADC volume registers. The bit
     	* 0x10 is read only so try to avoid using it.
     	*/

    	ad_write(mss, 0, 0xaa);
    	ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
    	tmp1 = ad_read(mss, 0);
    	tmp2 = ad_read(mss, 1);
    	if (tmp1 != 0xaa || tmp2 != 0x45) {
		BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
		goto no;
    	}

    	ad_write(mss, 0, 0x45);
    	ad_write(mss, 1, 0xaa);
    	tmp1 = ad_read(mss, 0);
    	tmp2 = ad_read(mss, 1);
    	if (tmp1 != 0x45 || tmp2 != 0xaa) {
		BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
		goto no;
    	}

    	/*
     	* The indirect register I12 has some read only bits. Lets try to
     	* change them.
     	*/

    	tmp = ad_read(mss, 12);
    	ad_write(mss, 12, (~tmp) & 0x0f);
    	tmp1 = ad_read(mss, 12);

    	if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
		BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
		goto no;
    	}

    	/*
     	* NOTE! Last 4 bits of the reg I12 tell the chip revision.
     	*	0x01=RevB
     	*  0x0A=RevC. also CS4231/CS4231A and OPTi931
     	*/

    	BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)

    	/*
     	* The original AD1848/CS4248 has just 16 indirect registers. This
     	* means that I0 and I16 should return the same value (etc.). Ensure
     	* that the Mode2 enable bit of I12 is 0. Otherwise this test fails
     	* with new parts.
     	*/

    	ad_write(mss, 12, 0);	/* Mode2=disabled */
#if 0
    	for (i = 0; i < 16; i++) {
		if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
	    	BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
			i, tmp1, tmp2));
	    	/*
	     	* note - this seems to fail on the 4232 on I11. So we just break
	     	* rather than fail.  (which makes this test pointless - cg)
	     	*/
	    	break; /* return 0; */
		}
    	}
#endif
    	/*
     	* Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
     	* (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
     	*
     	* On the OPTi931, however, I12 is readonly and only contains the
     	* chip revision ID (as in the CS4231A). The upper bits return 0.
     	*/

    	ad_write(mss, 12, 0x40);	/* Set mode2, clear 0x80 */

    	tmp1 = ad_read(mss, 12);
    	if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
    	if ((tmp1 & 0xf0) == 0x00) {
		BVDDB(printf("this should be an OPTi931\n");)
    	} else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
	/*
	* The 4231 has bit7=1 always, and bit6 we just set to 1.
	* We want to check that this is really a CS4231
	* Verify that setting I0 doesn't change I16.
	*/
	ad_write(mss, 16, 0);	/* Set I16 to known value */
	ad_write(mss, 0, 0x45);
	if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;

	ad_write(mss, 0, 0xaa);
       	if ((tmp1 = ad_read(mss, 16)) == 0xaa) {	/* Rotten bits? */
       		BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
		goto no;
	}
	/* Verify that some bits of I25 are read only. */
	tmp1 = ad_read(mss, 25);	/* Original bits */
	ad_write(mss, 25, ~tmp1);	/* Invert all bits */
	if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
		int id;

		/* It's at least CS4231 */
		name = "CS4231";
		mss->bd_id = MD_CS42XX;

		/*
		* It could be an AD1845 or CS4231A as well.
		* CS4231 and AD1845 report the same revision info in I25
		* while the CS4231A reports different.
		*/

		id = ad_read(mss, 25) & 0xe7;
		/*
		* b7-b5 = version number;
		*	100 : all CS4231
		*	101 : CS4231A
		*
		* b2-b0 = chip id;
		*/
		switch (id) {

		case 0xa0:
			name = "CS4231A";
			mss->bd_id = MD_CS42XX;
		break;

		case 0xa2:
			name = "CS4232";
			mss->bd_id = MD_CS42XX;
		break;

		case 0xb2:
		/* strange: the 4231 data sheet says b4-b3 are XX
		* so this should be the same as 0xa2
		*/
			name = "CS4232A";
			mss->bd_id = MD_CS42XX;
		break;

		case 0x80:
			/*
			* It must be a CS4231 or AD1845. The register I23
			* of CS4231 is undefined and it appears to be read
			* only. AD1845 uses I23 for setting sample rate.
			* Assume the chip is AD1845 if I23 is changeable.
			*/

			tmp = ad_read(mss, 23);

			ad_write(mss, 23, ~tmp);
			if (ad_read(mss, 23) != tmp) {	/* AD1845 ? */
				name = "AD1845";
				mss->bd_id = MD_AD1845;
			}
			ad_write(mss, 23, tmp);	/* Restore */

			yamaha = ymf_test(dev, mss);
			if (yamaha) {
				mss->bd_id = MD_YM0020;
				name = yamaha;
			}
			break;

		case 0x83:	/* CS4236 */
		case 0x03:      /* CS4236 on Intel PR440FX motherboard XXX */
			name = "CS4236";
			mss->bd_id = MD_CS42XX;
			break;

		default:	/* Assume CS4231 */
	 		BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
			mss->bd_id = MD_CS42XX;
		}
	}
	ad_write(mss, 25, tmp1);	/* Restore bits */
gotit:
    	BVDDB(printf("mss_detect() - Detected %s\n", name));
    	device_set_desc(dev, name);
    	device_set_flags(dev,
			 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
			  ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
    	return 0;
no:
    	return ENXIO;
}

#ifndef PC98
static int
opti_detect(device_t dev, struct mss_info *mss)
{
	int c;
	static const struct opticard {
		int boardid;
		int passwdreg;
		int password;
		int base;
		int indir_reg;
	} cards[] = {
		{ MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e },	/* 930 */
		{ MD_OPTI924, 3, 0xe5, 0xf8c, 0,    },	/* 924 */
		{ 0 },
	};
	mss->conf_rid = 3;
	mss->indir_rid = 4;
	for (c = 0; cards[c].base; c++) {
		mss->optibase = cards[c].base;
		mss->password = cards[c].password;
		mss->passwdreg = cards[c].passwdreg;
		mss->bd_id = cards[c].boardid;

		if (cards[c].indir_reg)
			mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
				&mss->indir_rid, cards[c].indir_reg,
				cards[c].indir_reg+1, 1, RF_ACTIVE);

		mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
			&mss->conf_rid, mss->optibase, mss->optibase+9,
			9, RF_ACTIVE);

		if (opti_read(mss, 1) != 0xff) {
			return 1;
		} else {
			if (mss->indir)
				bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
			mss->indir = NULL;
			if (mss->conf_base)
				bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
			mss->conf_base = NULL;
		}
	}
	return 0;
}
#endif

static char *
ymf_test(device_t dev, struct mss_info *mss)
{
    	static int ports[] = {0x370, 0x310, 0x538};
    	int p, i, j, version;
    	static char *chipset[] = {
		NULL,			/* 0 */
		"OPL3-SA2 (YMF711)",	/* 1 */
		"OPL3-SA3 (YMF715)",	/* 2 */
		"OPL3-SA3 (YMF715)",	/* 3 */
		"OPL3-SAx (YMF719)",	/* 4 */
		"OPL3-SAx (YMF719)",	/* 5 */
		"OPL3-SAx (YMF719)",	/* 6 */
		"OPL3-SAx (YMF719)",	/* 7 */
    	};

    	for (p = 0; p < 3; p++) {
		mss->conf_rid = 1;
		mss->conf_base = bus_alloc_resource(dev,
					  	SYS_RES_IOPORT,
					  	&mss->conf_rid,
					  	ports[p], ports[p] + 1, 2,
					  	RF_ACTIVE);
		if (!mss->conf_base) return 0;

		/* Test the index port of the config registers */
		i = port_rd(mss->conf_base, 0);
		port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
		j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
		port_wr(mss->conf_base, 0, i);
		if (!j) {
	    		bus_release_resource(dev, SYS_RES_IOPORT,
			 		     mss->conf_rid, mss->conf_base);
#ifdef PC98
			/* PC98 need this. I don't know reason why. */
			bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
#endif
	    		mss->conf_base = 0;
	    		continue;
		}
		version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
		return chipset[version];
    	}
    	return NULL;
}

static int
mss_doattach(device_t dev, struct mss_info *mss)
{
    	int pdma, rdma, flags = device_get_flags(dev);
    	char status[SND_STATUSLEN], status2[SND_STATUSLEN];

	mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
	mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
    	if (!mss_alloc_resources(mss, dev)) goto no;
    	mss_init(mss, dev);
	pdma = rman_get_start(mss->drq1);
	rdma = rman_get_start(mss->drq2);
    	if (flags & DV_F_TRUE_MSS) {
		/* has IRQ/DMA registers, set IRQ and DMA addr */
#ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
		static char     interrupt_bits[13] =
	        {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
#else
		static char     interrupt_bits[12] =
	    	{-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
#endif
		static char     pdma_bits[4] =  {1, 2, -1, 3};
		static char	valid_rdma[4] = {1, 0, -1, 0};
		char		bits;

		if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
			goto no;
#ifndef PC98 /* CS423[12] in PC98 don't support this. */
		io_wr(mss, 0, bits | 0x40);	/* config port */
		if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
#endif
		/* Write IRQ+DMA setup */
		if (pdma_bits[pdma] == -1) goto no;
		bits |= pdma_bits[pdma];
		if (pdma != rdma) {
	    		if (rdma == valid_rdma[pdma]) bits |= 4;
	    		else {
				printf("invalid dual dma config %d:%d\n", pdma, rdma);
				goto no;
	    		}
		}
		io_wr(mss, 0, bits);
		printf("drq/irq conf %x\n", io_rd(mss, 0));
    	}
    	mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
    	switch (mss->bd_id) {
    	case MD_OPTI931:
		snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
		break;
    	default:
		snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
    	}
    	if (pdma == rdma)
		pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
    	if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
			/*boundary*/0,
			/*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
			/*highaddr*/BUS_SPACE_MAXADDR,
			/*filter*/NULL, /*filterarg*/NULL,
			/*maxsize*/mss->bufsize, /*nsegments*/1,
			/*maxsegz*/0x3ffff, /*flags*/0,
			/*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant,
			&mss->parent_dmat) != 0) {
		device_printf(dev, "unable to create dma tag\n");
		goto no;
    	}

    	if (pdma != rdma)
		snprintf(status2, SND_STATUSLEN, ":%d", rdma);
	else
		status2[0] = '\0';

    	snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
    	     	rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);

    	if (pcm_register(dev, mss, 1, 1)) goto no;
    	pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
    	pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
    	pcm_setstatus(dev, status);

    	return 0;
no:
    	mss_release_resources(mss, dev);
    	return ENXIO;
}

static int
mss_detach(device_t dev)
{
	int r;
    	struct mss_info *mss;

	r = pcm_unregister(dev);
	if (r)
		return r;

	mss = pcm_getdevinfo(dev);
    	mss_release_resources(mss, dev);

	return 0;
}

static int
mss_attach(device_t dev)
{
    	struct mss_info *mss;
    	int flags = device_get_flags(dev);

    	mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
    	if (!mss) return ENXIO;

    	mss->io_rid = 0;
    	mss->conf_rid = -1;
    	mss->irq_rid = 0;
    	mss->drq1_rid = 0;
    	mss->drq2_rid = -1;
    	if (flags & DV_F_DUAL_DMA) {
        	bus_set_resource(dev, SYS_RES_DRQ, 1,
    		         	 flags & DV_F_DRQ_MASK, 1);
		mss->drq2_rid = 1;
    	}
    	mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
    	if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
    	return mss_doattach(dev, mss);
}

/*
 * mss_resume() is the code to allow a laptop to resume using the sound
 * card.
 *
 * This routine re-sets the state of the board to the state before going
 * to sleep.  According to the yamaha docs this is the right thing to do,
 * but getting DMA restarted appears to be a bit of a trick, so the device
 * has to be closed and re-opened to be re-used, but there is no skipping
 * problem, and volume, bass/treble and most other things are restored
 * properly.
 *
 */

static int
mss_resume(device_t dev)
{
    	/*
     	 * Restore the state taken below.
     	 */
    	struct mss_info *mss;
    	int i;

    	mss = pcm_getdevinfo(dev);

    	if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
		/* This works on a Toshiba Libretto 100CT. */
		for (i = 0; i < MSS_INDEXED_REGS; i++)
    			ad_write(mss, i, mss->mss_indexed_regs[i]);
		for (i = 0; i < OPL_INDEXED_REGS; i++)
    			conf_wr(mss, i, mss->opl_indexed_regs[i]);
		mss_intr(mss);
    	}

	if (mss->bd_id == MD_CS423X) {
		/* Needed on IBM Thinkpad 600E */
		mss_lock(mss);
		mss_format(&mss->pch, mss->pch.channel->format);
		mss_speed(&mss->pch, mss->pch.channel->speed);
		mss_unlock(mss);
	}

    	return 0;

}

/*
 * mss_suspend() is the code that gets called right before a laptop
 * suspends.
 *
 * This code saves the state of the sound card right before shutdown
 * so it can be restored above.
 *
 */

static int
mss_suspend(device_t dev)
{
    	int i;
    	struct mss_info *mss;

    	mss = pcm_getdevinfo(dev);

    	if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
    	{
		/* this stops playback. */
		conf_wr(mss, 0x12, 0x0c);
		for(i = 0; i < MSS_INDEXED_REGS; i++)
    			mss->mss_indexed_regs[i] = ad_read(mss, i);
		for(i = 0; i < OPL_INDEXED_REGS; i++)
    			mss->opl_indexed_regs[i] = conf_rd(mss, i);
		mss->opl_indexed_regs[0x12] = 0x0;
    	}
    	return 0;
}

static device_method_t mss_methods[] = {
	/* Device interface */
	DEVMETHOD(device_probe,		mss_probe),
	DEVMETHOD(device_attach,	mss_attach),
	DEVMETHOD(device_detach,	mss_detach),
	DEVMETHOD(device_suspend,       mss_suspend),
	DEVMETHOD(device_resume,        mss_resume),

	{ 0, 0 }
};

static driver_t mss_driver = {
	"pcm",
	mss_methods,
	PCM_SOFTC_SIZE,
};

DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
MODULE_VERSION(snd_mss, 1);

static int
azt2320_mss_mode(struct mss_info *mss, device_t dev)
{
	struct resource *sbport;
	int		i, ret, rid;

	rid = 0;
	ret = -1;
	sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
	if (sbport) {
		for (i = 0; i < 1000; i++) {
			if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
				DELAY((i > 100) ? 1000 : 10);
			else {
				port_wr(sbport, SBDSP_CMD, 0x09);
				break;
			}
		}
		for (i = 0; i < 1000; i++) {
			if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
				DELAY((i > 100) ? 1000 : 10);
			else {
				port_wr(sbport, SBDSP_CMD, 0x00);
				ret = 0;
				break;
			}
		}
		DELAY(1000);
		bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
	}
	return ret;
}

static struct isa_pnp_id pnpmss_ids[] = {
	{0x0000630e, "CS423x"},				/* CSC0000 */
	{0x0001630e, "CS423x-PCI"},			/* CSC0100 */
    	{0x01000000, "CMI8330"},			/* @@@0001 */
	{0x2100a865, "Yamaha OPL-SAx"},			/* YMH0021 */
	{0x1110d315, "ENSONIQ SoundscapeVIVO"},		/* ENS1011 */
	{0x1093143e, "OPTi931"},			/* OPT9310 */
	{0x5092143e, "OPTi925"},			/* OPT9250 XXX guess */
	{0x0000143e, "OPTi924"},			/* OPT0924 */
	{0x1022b839, "Neomagic 256AV (non-ac97)"},	/* NMX2210 */
	{0x01005407, "Aztech 2320"},			/* AZT0001 */
#if 0
	{0x0000561e, "GusPnP"},				/* GRV0000 */
#endif
	{0},
};

static int
pnpmss_probe(device_t dev)
{
	u_int32_t lid, vid;

	lid = isa_get_logicalid(dev);
	vid = isa_get_vendorid(dev);
	if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
		return ENXIO;
	return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
}

static int
pnpmss_attach(device_t dev)
{
	struct mss_info *mss;

	mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
	mss->io_rid = 0;
	mss->conf_rid = -1;
	mss->irq_rid = 0;
	mss->drq1_rid = 0;
	mss->drq2_rid = 1;
	mss->bd_id = MD_CS42XX;

	switch (isa_get_logicalid(dev)) {
	case 0x0000630e:			/* CSC0000 */
	case 0x0001630e:			/* CSC0100 */
	    mss->bd_flags |= BD_F_MSS_OFFSET;
	    mss->bd_id = MD_CS423X;
	    break;

	case 0x2100a865:			/* YHM0021 */
	    mss->io_rid = 1;
	    mss->conf_rid = 4;
	    mss->bd_id = MD_YM0020;
	    break;

	case 0x1110d315:			/* ENS1011 */
	    mss->io_rid = 1;
	    mss->bd_id = MD_VIVO;
	    break;

	case 0x1093143e:			/* OPT9310 */
            mss->bd_flags |= BD_F_MSS_OFFSET;
    	    mss->conf_rid = 3;
            mss->bd_id = MD_OPTI931;
	    break;

	case 0x5092143e:			/* OPT9250 XXX guess */
            mss->io_rid = 1;
            mss->conf_rid = 3;
	    mss->bd_id = MD_OPTI925;
	    break;

	case 0x0000143e:			/* OPT0924 */
	    mss->password = 0xe5;
	    mss->passwdreg = 3;
	    mss->optibase = 0xf0c;
	    mss->io_rid = 2;
	    mss->conf_rid = 3;
	    mss->bd_id = MD_OPTI924;
	    mss->bd_flags |= BD_F_924PNP;
	    if(opti_init(dev, mss) != 0) {
		    free(mss, M_DEVBUF);
		    return ENXIO;
	    }
	    break;

	case 0x1022b839:			/* NMX2210 */
	    mss->io_rid = 1;
	    break;

	case 0x01005407:			/* AZT0001 */
	    /* put into MSS mode first (snatched from NetBSD) */
	    if (azt2320_mss_mode(mss, dev) == -1) {
		    free(mss, M_DEVBUF);
		    return ENXIO;
	    }

	    mss->bd_flags |= BD_F_MSS_OFFSET;
	    mss->io_rid = 2;
	    break;
	    
#if 0
	case 0x0000561e:			/* GRV0000 */
	    mss->bd_flags |= BD_F_MSS_OFFSET;
            mss->io_rid = 2;
            mss->conf_rid = 1;
	    mss->drq1_rid = 1;
	    mss->drq2_rid = 0;
            mss->bd_id = MD_GUSPNP;
	    break;
#endif
	case 0x01000000:			/* @@@0001 */
	    mss->drq2_rid = -1;
            break;

	/* Unknown MSS default.  We could let the CSC0000 stuff match too */
        default:
	    mss->bd_flags |= BD_F_MSS_OFFSET;
	    break;
	}
    	return mss_doattach(dev, mss);
}

static int
opti_init(device_t dev, struct mss_info *mss)
{
	int flags = device_get_flags(dev);
	int basebits = 0;

	if (!mss->conf_base) {
		bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
			mss->optibase, 0x9);

		mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
			&mss->conf_rid, mss->optibase, mss->optibase+0x9,
			0x9, RF_ACTIVE);
	}

	if (!mss->conf_base)
		return ENXIO;

	if (!mss->io_base)
		mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
			&mss->io_rid, 0, ~0, 8, RF_ACTIVE);

	if (!mss->io_base)	/* No hint specified, use 0x530 */
		mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
			&mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);

	if (!mss->io_base)
		return ENXIO;

	switch (rman_get_start(mss->io_base)) {
		case 0x530:
			basebits = 0x0;
			break;
		case 0xe80:
			basebits = 0x10;
			break;
		case 0xf40:
			basebits = 0x20;
			break;
		case 0x604:
			basebits = 0x30;
			break;
		default:
			printf("opti_init: invalid MSS base address!\n");
			return ENXIO;
	}


	switch (mss->bd_id) {
	case MD_OPTI924:
		opti_write(mss, 1, 0x80 | basebits);	/* MSS mode */
		opti_write(mss, 2, 0x00);	/* Disable CD */
		opti_write(mss, 3, 0xf0);	/* Disable SB IRQ */
		opti_write(mss, 4, 0xf0);
		opti_write(mss, 5, 0x00);
		opti_write(mss, 6, 0x02);	/* MPU stuff */
		break;

	case MD_OPTI930:
		opti_write(mss, 1, 0x00 | basebits);
		opti_write(mss, 3, 0x00);	/* Disable SB IRQ/DMA */
		opti_write(mss, 4, 0x52);	/* Empty FIFO */
		opti_write(mss, 5, 0x3c);	/* Mode 2 */
		opti_write(mss, 6, 0x02);	/* Enable MSS */
		break;
	}

	if (mss->bd_flags & BD_F_924PNP) {
		u_int32_t irq = isa_get_irq(dev);
		u_int32_t drq = isa_get_drq(dev);
		bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
		bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
		if (flags & DV_F_DUAL_DMA) {
			bus_set_resource(dev, SYS_RES_DRQ, 1,
				flags & DV_F_DRQ_MASK, 1);
			mss->drq2_rid = 1;
		}
	}

	/* OPTixxx has I/DRQ registers */

	device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);

	return 0;
}

static void
opti_write(struct mss_info *mss, u_char reg, u_char val)
{
	port_wr(mss->conf_base, mss->passwdreg, mss->password);

	switch(mss->bd_id) {
	case MD_OPTI924:
		if (reg > 7) {		/* Indirect register */
			port_wr(mss->conf_base, mss->passwdreg, reg);
			port_wr(mss->conf_base, mss->passwdreg,
				mss->password);
			port_wr(mss->conf_base, 9, val);
			return;
		}
		port_wr(mss->conf_base, reg, val);
		break;

	case MD_OPTI930:
		port_wr(mss->indir, 0, reg);
		port_wr(mss->conf_base, mss->passwdreg, mss->password);
		port_wr(mss->indir, 1, val);
		break;
	}
}

#ifndef PC98
u_char
opti_read(struct mss_info *mss, u_char reg)
{
	port_wr(mss->conf_base, mss->passwdreg, mss->password);

	switch(mss->bd_id) {
	case MD_OPTI924:
		if (reg > 7) {		/* Indirect register */
			port_wr(mss->conf_base, mss->passwdreg, reg);
			port_wr(mss->conf_base, mss->passwdreg, mss->password);
			return(port_rd(mss->conf_base, 9));
		}
		return(port_rd(mss->conf_base, reg));
		break;

	case MD_OPTI930:
		port_wr(mss->indir, 0, reg);
		port_wr(mss->conf_base, mss->passwdreg, mss->password);
		return port_rd(mss->indir, 1);
		break;
	}
	return -1;
}
#endif

static device_method_t pnpmss_methods[] = {
	/* Device interface */
	DEVMETHOD(device_probe,		pnpmss_probe),
	DEVMETHOD(device_attach,	pnpmss_attach),
	DEVMETHOD(device_detach,	mss_detach),
	DEVMETHOD(device_suspend,       mss_suspend),
	DEVMETHOD(device_resume,        mss_resume),

	{ 0, 0 }
};

static driver_t pnpmss_driver = {
	"pcm",
	pnpmss_methods,
	PCM_SOFTC_SIZE,
};

DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0);
MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
MODULE_VERSION(snd_pnpmss, 1);

static int
guspcm_probe(device_t dev)
{
	struct sndcard_func *func;

	func = device_get_ivars(dev);
	if (func == NULL || func->func != SCF_PCM)
		return ENXIO;

	device_set_desc(dev, "GUS CS4231");
	return 0;
}

static int
guspcm_attach(device_t dev)
{
	device_t parent = device_get_parent(dev);
	struct mss_info *mss;
	int base, flags;
	unsigned char ctl;

	mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
	if (mss == NULL)
		return ENOMEM;

	mss->bd_flags = BD_F_MSS_OFFSET;
	mss->io_rid = 2;
	mss->conf_rid = 1;
	mss->irq_rid = 0;
	mss->drq1_rid = 1;
	mss->drq2_rid = -1;

	if (isa_get_logicalid(parent) == 0)
		mss->bd_id = MD_GUSMAX;
	else {
		mss->bd_id = MD_GUSPNP;
		mss->drq2_rid = 0;
		goto skip_setup;
	}

	flags = device_get_flags(parent);
	if (flags & DV_F_DUAL_DMA)
		mss->drq2_rid = 0;

	mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
					    0, ~0, 8, RF_ACTIVE);

	if (mss->conf_base == NULL) {
		mss_release_resources(mss, dev);
		return ENXIO;
	}

	base = isa_get_port(parent);

	ctl = 0x40;			/* CS4231 enable */
	if (isa_get_drq(dev) > 3)
		ctl |= 0x10;		/* 16-bit dma channel 1 */
	if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
		ctl |= 0x20;		/* 16-bit dma channel 2 */
	ctl |= (base >> 4) & 0x0f;	/* 2X0 -> 3XC */
	port_wr(mss->conf_base, 6, ctl);

skip_setup:
	return mss_doattach(dev, mss);
}

static device_method_t guspcm_methods[] = {
	DEVMETHOD(device_probe,		guspcm_probe),
	DEVMETHOD(device_attach,	guspcm_attach),
	DEVMETHOD(device_detach,	mss_detach),

	{ 0, 0 }
};

static driver_t guspcm_driver = {
	"pcm",
	guspcm_methods,
	PCM_SOFTC_SIZE,
};

DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
MODULE_VERSION(snd_guspcm, 1);


OpenPOWER on IntegriCloud