path: root/sys/dev/bhnd/nvram/nvram_map

#-
# Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
# Copyright (C) 2008-2015, Broadcom Corporation.
# All Rights Reserved.
# 
# The contents of this file (variable names, descriptions, and offsets) were
# extracted or derived from Broadcom's ISC-licensed sources.
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
# 
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#
# $FreeBSD$

#
# NVRAM variable definitions and revision-specific SPROM offsets.
#
# Processed by nvram_map_gen.awk to produce bhnd_nvram_map.h
#
# NOTE: file was originally generated automatically by using libclang
# to analyze and extract format information and descriptions from Broadcom's
# available ISC-licensed CIS and SROM code and associated headers.
#

# Board Info
#

u16 boardvendor	{}			# PCI vendor ID (SoC NVRAM-only)
u16 subvid	{ srom >= 2	0x6 }	# PCI subvendor ID
u16 devid	{ srom >= 8	0x60 }	# PCI device ID 

u32 boardflags {
	srom 1		u16 0x72
	srom 2		u16 0x72 | u16 0x38 (<<16)
	srom 3		u16 0x72 | u16 0x7A (<<16)
	srom 4		0x44
	srom 5-7	0x4A
	srom >= 8	0x84
}
u32 boardflags2 {
	srom 4		0x48
	srom 5-7	0x4E
	srom >= 8	0x88
}
u32 boardflags3 {
	srom >= 11	0x8C
}

# Board serial number, independent of mac addr
u16 boardnum {
	srom 1-2	0x4C
	srom 3		0x4E
	srom 4		0x50
	srom 5-7	0x56
	srom 8-10	0x90
	srom >= 11	0x94
}

# Board revision
u16 boardrev {
	srom 1-3	u8 0x5D
	srom 4-7	0x42
	srom >= 8	0x82
}

# Board type
u16 boardtype {
	srom >= 2	0x4
}

# SROM revision
u8 sromrev {
	srom 1-3	0x74
	srom 4-9	0x1B6
	srom 10		0x1CA
	srom 11		0x1D2
}

# Antennas available
u8 aa2g {
	srom 1-3	0x5C (&0x30, >>4)
	srom 4-7	0x5D
	srom 8-10	0x9D
	srom >= 11	0xA1
}
u8 aa5g {
	srom 1-3	0x5C (&0xC0, >>6)
	srom 4-7	0x5C
	srom 8-10	0x9C
	srom >= 11	0xA0
}

# ACPHY PA trimming parameters: 40
u16[12] pa5gbw40a0 {
	srom >= 11	0x110
}

# ACPHY PA trimming parameters: 80
u16[12] pa5gbw80a0 {
	srom >= 11	0x138
}

# ACPHY PA trimming parameters: 40/80
u16[12] pa5gbw4080a0 {
	srom >= 11	0x138
}
u16[12] pa5gbw4080a1 {
	srom >= 11	u16 0xB6, u16 0xBC, u16 0xCE, u16 0xD4, u16[8] 0x128
}

# ACPHY PA trimming parameters: CCK
u16[3] pa2gccka0 {
	srom >= 11	0x102
}

# ACPHY Power-per-rate 2gpo
u16 dot11agofdmhrbw202gpo {
	srom >= 11	0x15C
}
u16 ofdmlrbw202gpo {
	srom >= 11	0x15E
}

# ACPHY Power-per-rate 5gpo
u32 mcsbw805glpo {
	srom >= 11	0x168
}
u32 mcsbw805gmpo {
	srom >= 11	0x178
}
u32 mcsbw805ghpo {
	srom >= 11	0x188
}
u16 mcslr5glpo {
	srom >= 11	0x190 (&0xFFF)
}
u16 mcslr5gmpo {
	srom >= 11	0x192
}
u16 mcslr5ghpo {
	srom >= 11	0x194
}

# ACPHY Power-per-rate sbpo
u16 sb20in40hrpo {
	srom >= 11	0x196
}
u16 sb20in80and160hr5glpo {
	srom >= 11	0x198
}
u16 sb40and80hr5glpo {
	srom >= 11	0x19A
}
u16 sb20in80and160hr5gmpo {
	srom >= 11	0x19C
}
u16 sb40and80hr5gmpo {
	srom >= 11	0x19E
}
u16 sb20in80and160hr5ghpo {
	srom >= 11	0x1A0
}
u16 sb40and80hr5ghpo {
	srom >= 11	0x1A2
}
u16 sb20in40lrpo {
	srom >= 11	0x1A4
}
u16 sb20in80and160lr5glpo {
	srom >= 11	0x1A6
}
u16 sb40and80lr5glpo {
	srom >= 11	0x1A8
}
u16 sb20in80and160lr5gmpo {
	srom >= 11	0x1AA
}
u16 sb40and80lr5gmpo {
	srom >= 11	0x1AC
}
u16 sb20in80and160lr5ghpo {
	srom >= 11	0x1AE
}
u16 sb40and80lr5ghpo {
	srom >= 11	0x1B0
}
u16 dot11agduphrpo {
	srom >= 11	0x1B2
}
u16 dot11agduplrpo {
	srom >= 11	0x1B4
}

# Antenna gain
u8 ag0 {
	srom 1-3	0x75
	srom 4-7	0x5F
	srom 8-10	0x9F
}
u8 ag1 {
	srom 1-3	0x74
	srom 4-7	0x5E
	srom 8-10	0x9E
}
u8 ag2 {
	srom 4-7	0x61
	srom 8-10	0xA1
}
u8 ag3 {
	srom 4-7	0x60
	srom 8-10	0xA0
}

u8 agbg0 {
	srom >= 11	0xA2
}
u8 agbg1 {
	srom >= 11	0xA3
}
u8 agbg2 {
	srom >= 11	0xA4
}
u8 aga0 {
	srom >= 11	0xA5
}
u8 aga1 {
	srom >= 11	0xA6
}
u8 aga2 {
	srom >= 11	0xA7
}

# Default country code (sromrev == 1)
u8 cc {
	srom 1		0x5C (&0xF)
}

# 2 bytes each
# CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
# cckbw202gpo cckbw20ul2gpo
# 
u16 cckbw202gpo {
	srom 9-10	0x140
	srom >= 11	0x150
}
u16 cckbw20ul2gpo {
	srom 9-10	0x142
	srom >= 11	0x152
}

# Country code (2 bytes ascii + 1 byte cctl)
# in rev 2
# 
char[2] ccode {
	sfmt	ccode
	srom 0-3	0x76
	srom 4		0x52
	srom 5-7	0x44
	srom 8-10	0x92
	srom >= 11	0x96
}

# 2 byte; txchain, rxchain
u8 txchain {
	all1	ignore
	srom 4-7	0x7B (&0xF)
	srom 8-10	0xA3 (&0xF)
	srom >= 11	0xA9 (&0xF)
}
u8 rxchain {
	all1	ignore
	srom 4-7	0x7B (&0xF0, >>4)
	srom 8-10	0xA3 (&0xF0, >>4)
	srom >= 11	0xA9 (&0xF0, >>4)
}
u16 antswitch {
	all1	ignore
	srom 4-7	u8 0x7A
	srom 8-10	u8 0xA2
	srom >= 11	u8 0xA8
}

u8 elna2g {
	srom 8-10	0xBB
}

u8 elna5g {
	srom 8-10	0xBA
}

# 11n front-end specification
u8 antswctl2g {
	srom 8-10	0xAE (&0xF8, >>3)
}
u8 triso2g {
	srom 8-10	0xAE (&0x7)
}
u8 pdetrange2g {
	srom 8-10	0xAF (&0xF8, >>3)
}
u8 extpagain2g {
	srom 8-10	0xAF (&0x6, >>1)
}
u8 tssipos2g {
	srom 8-10	0xAF (&0x1)
}
u8 antswctl5g {
	srom 8-10	0xB0 (&0xF8, >>3)
}
u8 triso5g {
	srom 8-10	0xB0 (&0x7)
}
u8 pdetrange5g {
	srom 8-10	0xB1 (&0xF8, >>3)
}
u8 extpagain5g {
	srom 8-10	0xB1 (&0x6, >>1)
}
u8 tssipos5g {
	srom 8-10	0xB1 (&0x1)
}

# FEM config
u8 femctrl {
	sfmt	decimal
	srom >= 11	0xAA (&0xF8, >>3)
}
u8 papdcap2g {
	sfmt	decimal
	srom >= 11	0xAA (&0x4, >>2)
}
u8 tworangetssi2g {
	sfmt	decimal
	srom >= 11	0xAA (&0x2, >>1)
}
u8 pdgain2g {
	sfmt	decimal
	srom >= 11	u16 0xAA (&0x1F0, >>4)
}
u8 epagain2g {
	sfmt	decimal
	srom >= 11	0xAB (&0xE, >>1)
}
u8 tssiposslope2g {
	sfmt	decimal
	srom >= 11	0xAB (&0x1)
}
u8 gainctrlsph {
	sfmt	decimal
	srom >= 11	0xAC (&0xF8, >>3)
}
u8 papdcap5g {
	sfmt	decimal
	srom >= 11	0xAC (&0x4, >>2)
}
u8 tworangetssi5g {
	sfmt	decimal
	srom >= 11	0xAC (&0x2, >>1)
}
u8 pdgain5g {
	sfmt	decimal
	srom >= 11	u16 0xAC (&0x1F0, >>4)
}
u8 epagain5g {
	sfmt	decimal
	srom >= 11	0xAD (&0xE, >>1)
}
u8 tssiposslope5g {
	sfmt	decimal
	srom >= 11	0xAD (&0x1)
}

# LED duty cycle
u8[2] leddc {
	sfmt	led_dc
	all1	ignore
	srom 3		0x7C
	srom 4		0x5A
	srom 5-7	0x5A
	srom 8-10	0x9A
	srom >= 11	0x9E
}

# LED set
u8 ledbh0 {
	all1	ignore
	srom 1-3	0x65
	srom 4		0x57
	srom 5-7	0x77
	srom 8-10	0x97
	srom >= 11	0x9B
}
u8 ledbh1 {
	all1	ignore
	srom 1-3	0x64
	srom 4		0x56
	srom 5-7	0x76
	srom 8-10	0x96
	srom >= 11	0x9A
}
u8 ledbh2 {
	all1	ignore
	srom 1-3	0x67
	srom 4		0x59
	srom 5-7	0x79
	srom 8-10	0x99
	srom >= 11	0x9D
}
u8 ledbh3 {
	all1	ignore
	srom 1-3	0x66
	srom 4		0x58
	srom 5-7	0x78
	srom 8-10	0x98
	srom >= 11	0x9C
}

# 2 bytes total
# Additional power offset for Legacy Dup40 transmissions.
# Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
# LSB nibble: 2G band, MSB nibble: 5G band high subband.
# leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
# 
u16 legofdm40duppo {
	srom 9-10	0x196
}

# 4 bytes each
# OFDM power offsets for 20 MHz Legacy rates
# (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
# legofdmbw202gpo  legofdmbw20ul2gpo
# 
u32 legofdmbw202gpo {
	srom 9-10	0x144
}
u32 legofdmbw20ul2gpo {
	srom 9-10	0x148
}

# 4 bytes each
# 5G band: OFDM power offsets for 20 MHz Legacy rates
# (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
# low subband : legofdmbw205glpo  legofdmbw20ul2glpo
# mid subband :legofdmbw205gmpo  legofdmbw20ul2gmpo
# high subband :legofdmbw205ghpo  legofdmbw20ul2ghpo
# 
u32 legofdmbw205glpo {
	srom 9-10	0x14C
}
u32 legofdmbw20ul5glpo {
	srom 9-10	0x150
}
u32 legofdmbw205gmpo {
	srom 9-10	0x154
}
u32 legofdmbw20ul5gmpo {
	srom 9-10	0x158
}
u32 legofdmbw205ghpo {
	srom 9-10	0x15C
}
u32 legofdmbw20ul5ghpo {
	srom 9-10	0x160
}

# mac addr override for the standard CIS LAN_NID
u8[6] macaddr {
	sfmt	macaddr
	srom 3		u8 0x4B, u8 0x4A, u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E
	srom 4		u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E, u8 0x51, u8 0x50
	srom 5-7	u8 0x53, u8 0x52, u8 0x55, u8 0x54, u8 0x57, u8 0x56
	srom 8-10	u8 0x8D, u8 0x8C, u8 0x8F, u8 0x8E, u8 0x91, u8 0x90
	srom >= 11	u8 0x91, u8 0x90, u8 0x93, u8 0x92, u8 0x95, u8 0x94
}

# 4 bytes each
# mcs 0-7  power-offset. LSB nibble: m0, MSB nibble: m7
# mcsbw202gpo  mcsbw20ul2gpo mcsbw402gpo
# 
u32 mcsbw202gpo {
	srom 9-10	0x164
	srom >= 11	0x154
}
u32 mcsbw20ul2gpo {
	srom 9-10	0x168
}
u32 mcsbw402gpo {
	srom 9-10	0x16C
	srom >= 11	0x158
}

# 4 bytes each
# 5G high subband mcs 0-7 power-offset.
# LSB nibble: m0, MSB nibble: m7
# mcsbw205ghpo  mcsbw20ul5ghpo mcsbw405ghpo
# 
u32 mcsbw205ghpo {
	srom 9-10	0x188
	srom >= 11	0x180
}
u32 mcsbw20ul5ghpo {
	srom 9-10	0x18C
}
u32 mcsbw405ghpo {
	srom 9-10	0x190
	srom >= 11	0x184
}

# 4 bytes each
# 5G low subband mcs 0-7 power-offset.
# LSB nibble: m0, MSB nibble: m7
# mcsbw205glpo  mcsbw20ul5glpo mcsbw405glpo
# 
u32 mcsbw205glpo {
	srom 9-10	0x170
	srom >= 11	0x160
}
u32 mcsbw20ul5glpo {
	srom 9-10	0x174
}
u32 mcsbw405glpo {
	srom 9-10	0x178
	srom >= 11	0x164
}

# 4 bytes each
# 5G mid subband mcs 0-7 power-offset.
# LSB nibble: m0, MSB nibble: m7
# mcsbw205gmpo  mcsbw20ul5gmpo mcsbw405gmpo
# 
u32 mcsbw205gmpo {
	srom 9-10	0x17C
	srom >= 11	0x170
}
u32 mcsbw20ul5gmpo {
	srom 9-10	0x180
}
u32 mcsbw405gmpo {
	srom 9-10	0x184
	srom >= 11	0x174
}

# 2 bytes total
# mcs-32 power offset for each band/subband.
# LSB nibble: 2G band, MSB nibble:
# mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
# 
u16 mcs32po {
	srom 9-10	0x194
}

u8 measpower {
	srom 8-10	0xB4 (&0xFE, >>1)
	srom >= 11	0xB0 (&0xFE, >>1)
}
u8 measpower1 {
	srom 8-10	0xBF (&0x7F)
	srom >= 11	0xBB (&0x7F)
}
u8 measpower2 {
	srom 8-10	u16 0xBE (&0x3F80, >>7)
	srom >= 11	u16 0xBA (&0x3F80, >>7)
}
u16 rawtempsense {
	srom 8-10	0xB4 (&0x1FF)
	srom >= 11	0xB0 (&0x1FF)
}

u8 noiselvl2ga0 {
	sfmt	decimal
	srom 8-10	0x1AB (&0x1F)
	srom >= 11	0x1BD (&0x1F)
}
u8 noiselvl2ga1 {
	sfmt	decimal
	srom 8-10	u16 0x1AA (&0x3E0, >>5)
	srom >= 11	u16 0x1BC (&0x3E0, >>5)
}
u8 noiselvl2ga2 {
	sfmt	decimal
	srom 8-10	0x1AA (&0x7C, >>2)
	srom >= 11	0x1BC (&0x7C, >>2)
}
u8[4] noiselvl5ga0 {
	sfmt	decimal
	srom >= 11	u8 0x1BF (&0x1F), u8 0x1C1 (&0x1F), u8 0x1C3 (&0x1F), u8 0x1C5 (&0x1F)
}
u8[4] noiselvl5ga1 {
	sfmt	decimal
	srom >= 11	u16[4] 0x1BE (&0x3E0, >>5)
}
u8[4] noiselvl5ga2 {
	sfmt	decimal
	srom >= 11	u8 0x1BE (&0x7C, >>2), u8 0x1C0 (&0x7C, >>2), u8 0x1C2 (&0x7C, >>2), u8 0x1C4 (&0x7C, >>2)
}

# paparambwver
u8 paparambwver {
	sfmt	decimal
	srom >= 11	0x190 (&0xF0, >>4)
}

# PA parameters: 8 (sromrev == 1)
# or 9 (sromrev > 1) bytes
# 
u16 pa0b0 {
	sfmt	decimal
	srom 1-3	0x5E
	srom 8-10	0xC2
}
u16 pa0b1 {
	sfmt	decimal
	srom 1-3	0x60
	srom 8-10	0xC4
}
u16 pa0b2 {
	sfmt	decimal
	srom 1-3	0x62
	srom 8-10	0xC6
}
u8 pa0itssit {
	sfmt	decimal
	srom 1-3	0x71
	srom 8-10	0xC0
}
u8 pa0maxpwr {
	sfmt	decimal
	srom 1-3	0x69
	srom 8-10	0xC1
}
u8 opo {
	srom 2-3	0x79
	srom 8-10	0x143
}

# 5G PA params
u16 pa1b0 {
	sfmt	decimal
	srom 1-3	0x6A
	srom 8-10	0xCC
}
u16 pa1b1 {
	sfmt	decimal
	srom 1-3	0x6C
	srom 8-10	0xCE
}
u16 pa1b2 {
	sfmt	decimal
	srom 1-3	0x6E
	srom 8-10	0xD0
}
u16 pa1lob0 {
	sfmt	decimal
	srom 2-3	0x3C
	srom 8-10	0xD2
}
u16 pa1lob1 {
	sfmt	decimal
	srom 2-3	0x3E
	srom 8-10	0xD4
}
u16 pa1lob2 {
	sfmt	decimal
	srom 2-3	0x40
	srom 8-10	0xD6
}
u16 pa1hib0 {
	sfmt	decimal
	srom 2-3	0x42
	srom 8-10	0xD8
}
u16 pa1hib1 {
	sfmt	decimal
	srom 2-3	0x44
	srom 8-10	0xDA
}
u16 pa1hib2 {
	sfmt	decimal
	srom 2-3	0x46
	srom 8-10	0xDC
}
u8 pa1itssit {
	sfmt	decimal
	srom 1-3	0x70
	srom 8-10	0xC8
}
u8 pa1maxpwr {
	sfmt	decimal
	srom 1-3	0x68
	srom 8-10	0xC9
}
u8 pa1lomaxpwr {
	sfmt	decimal
	srom 2-3	0x3A
	srom 8-10	0xCA
}
u8 pa1himaxpwr {
	sfmt	decimal
	srom 2-3	0x3B
	srom 8-10	0xCB
}

u16 pdoffset40ma0 {
	srom >= 11	0xCA
}
u16 pdoffset40ma1 {
	srom >= 11	0xCC
}
u16 pdoffset40ma2 {
	srom >= 11	0xCE
}
u16 pdoffset80ma0 {
	srom >= 11	0xD0
}
u16 pdoffset80ma1 {
	srom >= 11	0xD2
}
u16 pdoffset80ma2 {
	srom >= 11	0xD4
}

u8 pdoffset2g40ma0 {
	srom >= 11	0xC9 (&0xF)
}
u8 pdoffset2g40ma1 {
	srom >= 11	0xC9 (&0xF0, >>4)
}
u8 pdoffset2g40ma2 {
	srom >= 11	0xC8 (&0xF)
}
u8 pdoffset2g40mvalid {
	srom >= 11	0xC8 (&0x80, >>7)
}

# 40Mhz channel 2g/5g power offset
u16 bw40po {
	srom 4-7	0x18E
	srom 8	0x196
}

# 40Mhz channel dup 2g/5g power offset
u16 bwduppo {
	srom 4-7	0x190
	srom 8	0x198
}

# cck2g/ofdm2g/ofdm5g power offset
u16 cck2gpo {
	srom 4-7	0x138
	srom 8		0x140
}
u32 ofdm2gpo {
	srom 4-7	0x13A
	srom 8		0x142
}
u32 ofdm5gpo {
	srom 4-7	0x13E
	srom 8		0x146
}
u32 ofdm5glpo {
	srom 4-7	0x142
	srom 8		0x14A
}
u32 ofdm5ghpo {
	srom 4-7	0x146
	srom 8		0x14E
}

# cdd2g/5g power offset
u16 cddpo {
	srom 4-7	0x18A
	srom 8		0x192
}

# mcs2g power offset
u16 mcs2gpo0 {
	srom 4-7	0x14A
	srom 8		0x152
}
u16 mcs2gpo1 {
	srom 4-7	0x14C
	srom 8		0x154
}
u16 mcs2gpo2 {
	srom 4-7	0x14E
	srom 8		0x156
}
u16 mcs2gpo3 {
	srom 4-7	0x150
	srom 8		0x158
}
u16 mcs2gpo4 {
	srom 4-7	0x152
	srom 8		0x15A
}
u16 mcs2gpo5 {
	srom 4-7	0x154
	srom 8		0x15C
}
u16 mcs2gpo6 {
	srom 4-7	0x156
	srom 8		0x15E
}
u16 mcs2gpo7 {
	srom 4-7	0x158
	srom 8		0x160
}

# mcs5g low-high band power offset
u16 mcs5glpo0 {
	srom 4-7	0x16A
	srom 8		0x172
}
u16 mcs5glpo1 {
	srom 4-7	0x16C
	srom 8		0x174
}
u16 mcs5glpo2 {
	srom 4-7	0x16E
	srom 8		0x176
}
u16 mcs5glpo3 {
	srom 4-7	0x170
	srom 8		0x178
}
u16 mcs5glpo4 {
	srom 4-7	0x172
	srom 8		0x17A
}
u16 mcs5glpo5 {
	srom 4-7	0x174
	srom 8		0x17C
}
u16 mcs5glpo6 {
	srom 4-7	0x176
	srom 8		0x17E
}
u16 mcs5glpo7 {
	srom 4-7	0x178
	srom 8		0x180
}
u16 mcs5ghpo0 {
	srom 4-7	0x17A
	srom 8		0x182
}
u16 mcs5ghpo1 {
	srom 4-7	0x17C
	srom 8		0x184
}
u16 mcs5ghpo2 {
	srom 4-7	0x17E
	srom 8		0x186
}
u16 mcs5ghpo3 {
	srom 4-7	0x180
	srom 8		0x188
}
u16 mcs5ghpo4 {
	srom 4-7	0x182
	srom 8		0x18A
}
u16 mcs5ghpo5 {
	srom 4-7	0x184
	srom 8		0x18C
}
u16 mcs5ghpo6 {
	srom 4-7	0x186
	srom 8		0x18E
}
u16 mcs5ghpo7 {
	srom 4-7	0x188
	srom 8		0x190
}

# mcs5g mid band power offset
u16 mcs5gpo0 {
	srom 4-7	0x15A
	srom 8		0x162
}
u16 mcs5gpo1 {
	srom 4-7	0x15C
	srom 8		0x164
}
u16 mcs5gpo2 {
	srom 4-7	0x15E
	srom 8		0x166
}
u16 mcs5gpo3 {
	srom 4-7	0x160
	srom 8		0x168
}
u16 mcs5gpo4 {
	srom 4-7	0x162
	srom 8		0x16A
}
u16 mcs5gpo5 {
	srom 4-7	0x164
	srom 8		0x16C
}
u16 mcs5gpo6 {
	srom 4-7	0x166
	srom 8		0x16E
}
u16 mcs5gpo7 {
	srom 4-7	0x168
	srom 8		0x170
}

# stbc2g/5g power offset
u16 stbcpo {
	srom 4-7	0x18C
	srom 8		0x194
}

u8 regrev {
	srom 3		0x78
	srom 4		0x55
	srom 5-7	0x47
	srom 8-10	0x95
	srom >= 11	0x99
}

# 4328 2G RSSI mid pt sel & board switch arch,
# 2 bytes, rev 3.
# 
u8 rssismf2g {
	srom 3		0x51 (&0xF)
	srom 8-10	0xA5 (&0xF)
}
u8 rssismc2g {
	srom 3		0x51 (&0xF0, >>4)
	srom 8-10	0xA5 (&0xF0, >>4)
}
u8 rssisav2g {
	srom 3		0x50 (&0x7)
	srom 8-10	0xA4 (&0x7)
}
u8 bxa2g {
	srom 3		0x50 (&0x18, >>3)
	srom 8-10	0xA4 (&0x18, >>3)
}

# 4328 5G RSSI mid pt sel & board switch arch,
# 2 bytes, rev 3.
# 
u8 rssismf5g {
	srom 3		0x53 (&0xF)
	srom 8-10	0xA7 (&0xF)
}
u8 rssismc5g {
	srom 3		0x53 (&0xF0, >>4)
	srom 8-10	0xA7 (&0xF0, >>4)
}
u8 rssisav5g {
	srom 3		0x52 (&0x7)
	srom 8-10	0xA6 (&0x7)
}
u8 bxa5g {
	srom 3		0x52 (&0x18, >>3)
	srom 8-10	0xA6 (&0x18, >>3)
}

u8 rxgainerr2ga0 {
	srom 8-10	0x19B (&0x3F)
	srom >= 11	0x1C7 (&0x3F)
}
u8 rxgainerr2ga1 {
	srom 8-10	u16 0x19A (&0x7C0, >>6)
	srom >= 11	u16 0x1C6 (&0x7C0, >>6)
}
u8 rxgainerr2ga2 {
	srom 8-10	0x19A (&0xF8, >>3)
	srom >= 11	0x1C6 (&0xF8, >>3)
}
u8[4] rxgainerr5ga0 {
	srom >= 11	u8 0x1C9 (&0x3F), u8 0x1CB (&0x3F), u8 0x1CD (&0x3F), u8 0x1CF (&0x3F)
}
u8[4] rxgainerr5ga1 {
	srom >= 11	u16[4] 0x1C8 (&0x7C0, >>6)
}
u8[4] rxgainerr5ga2 {
	srom >= 11	u8 0x1C8 (&0xF8, >>3), u8 0x1CA (&0xF8, >>3), u8 0x1CC (&0xF8, >>3), u8 0x1CE (&0xF8, >>3)
}
u8 rxgainerr5gha0 {
	srom 8-10	0x1A1 (&0x3F)
}
u8 rxgainerr5gha1 {
	srom 8-10	u16 0x1A0 (&0x7C0, >>6)
}
u8 rxgainerr5gha2 {
	srom 8-10	0x1A0 (&0xF8, >>3)
}
u8 rxgainerr5gla0 {
	srom 8-10	0x19D (&0x3F)
}
u8 rxgainerr5gla1 {
	srom 8-10	u16 0x19C (&0x7C0, >>6)
}
u8 rxgainerr5gla2 {
	srom 8-10	0x19C (&0xF8, >>3)
}
u8 rxgainerr5gma0 {
	srom 8-10	0x19F (&0x3F)
}
u8 rxgainerr5gma1 {
	srom 8-10	u16 0x19E (&0x7C0, >>6)
}
u8 rxgainerr5gma2 {
	srom 8-10	0x19E (&0xF8, >>3)
}
u8 rxgainerr5gua0 {
	srom 8-10	0x1A3 (&0x3F)
}
u8 rxgainerr5gua1 {
	srom 8-10	u16 0x1A2 (&0x7C0, >>6)
}
u8 rxgainerr5gua2 {
	srom 8-10	0x1A2 (&0xF8, >>3)
}

# 4328 2G RX power offset
i8 rxpo2g {
	sfmt	decimal
	srom 3		0x5B
	srom 8-10	0xAD
}

# 4328 5G RX power offset
i8 rxpo5g {
	sfmt	decimal
	srom 3		0x5A
	srom 8-10	0xAC
}

u16 subband5gver {
	srom 8-10	u8 0x1A5 (&0x7)
	srom >= 11	0xD6
}

# 2 bytes
# byte1 tempthresh
# byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
# 
u8 tempthresh {
	srom 8-10	0xB2
	srom >= 11	0xAE
}
u8 temps_period {
	sfmt	decimal
	srom 8-10	0xBC (&0xF)
	srom >= 11	0xB8 (&0xF)
}
u8 temps_hysteresis {
	sfmt	decimal
	srom 8-10	0xBC (&0xF0, >>4)
	srom >= 11	0xB8 (&0xF0, >>4)
}
u8 tempoffset {
	sfmt	decimal
	srom 8-10	0xB3
	srom >= 11	0xAF
}
u8 tempsense_slope {
	srom 8-10	0xB7
	srom >= 11	0xB3
}
u8 tempcorrx {
	srom 8-10	0xB6 (&0xFC, >>2)
	srom >= 11	0xB2 (&0xFC, >>2)
}
u8 tempsense_option {
	srom 8-10	0xB6 (&0x3)
	srom >= 11	0xB2 (&0x3)
}
u8 phycal_tempdelta {
	sfmt	decimal
	srom 8-10	0xBD
	srom >= 11	0xB9
}

# 4328 2G TR isolation, 1 byte
u8 tri2g {
	srom 3		0x55
	srom 8-10	0xA9
}

# 4328 5G TR isolation, 3 bytes
u8 tri5gl {
	srom 3		0x57
	srom 8-10	0xAB
}
u8 tri5g {
	srom 3		0x54
	srom 8-10	0xA8
}
u8 tri5gh {
	srom 3		0x56
	srom 8-10	0xAA
}

# phy txbf rpcalvars
u16 rpcal2g {
	srom >= 11	0x16C
}
u16 rpcal5gb0 {
	srom >= 11	0x16E
}
u16 rpcal5gb1 {
	srom >= 11	0x17C
}
u16 rpcal5gb2 {
	srom >= 11	0x17E
}
u16 rpcal5gb3 {
	srom >= 11	0x18C
}

# Crystal frequency in kilohertz
u32 xtalfreq {
	sfmt	decimal
	srom >= 11	u16 0xB4
}

# N-PHY tx power workaround
u8 txpid2ga0 {
	srom 4-7	0x63
}
u8 txpid2ga1 {
	srom 4-7	0x62
}
u8 txpid2ga2 {
	srom 4-7	0x65
}
u8 txpid2ga3 {
	srom 4-7	0x64
}
u8 txpid5ga0 {
	srom 4-7	0x67
}
u8 txpid5ga1 {
	srom 4-7	0x66
}
u8 txpid5ga2 {
	srom 4-7	0x69
}
u8 txpid5ga3 {
	srom 4-7	0x68
}
u8 txpid5gha0 {
	srom 4-7	0x6F
}
u8 txpid5gha1 {
	srom 4-7	0x6E
}
u8 txpid5gha2 {
	srom 4-7	0x71
}
u8 txpid5gha3 {
	srom 4-7	0x70
}
u8 txpid5gla0 {
	srom 4-7	0x6B
}
u8 txpid5gla1 {
	srom 4-7	0x6A
}
u8 txpid5gla2 {
	srom 4-7	0x6D
}
u8 txpid5gla3 {
	srom 4-7	0x6C
}

u16 cckPwrOffset {
	srom 10	0x1B4
}
u8[6] et1macaddr {
	sfmt	macaddr
	srom 0-2	u8 0x55, u8 0x54, u8 0x57, u8 0x56, u8 0x59, u8 0x58
}
u8 eu_edthresh2g {
	srom 8		0x1A9
	srom 9		0x199
	srom 10		0x199
	srom 11		0x1D1
}
u8 eu_edthresh5g {
	srom 8		0x1A8
	srom 9		0x198
	srom 10		0x198
	srom 11		0x1D0
}
u8 freqoffset_corr {
	srom 8-10	0xB9 (&0xF)
}
u8 hw_iqcal_en {
	srom 8-10	0xB9 (&0x20, >>5)
}
u8[6] il0macaddr {
	sfmt	macaddr
	srom 0-2	u8 0x49, u8 0x48, u8 0x51, u8 0x50, u8 0x53, u8 0x52
}
u8 iqcal_swp_dis {
	srom 8-10	0xB9 (&0x10, >>4)
}

u8 noisecaloffset {
	srom 8-9	0x1B5
}
u8 noisecaloffset5g {
	srom 8-9	0x1B4
}
u8 noiselvl5gha0 {
	srom 8-10	0x1B1 (&0x1F)
}
u8 noiselvl5gha1 {
	srom 8-10	u16 0x1B0 (&0x3E0, >>5)
}
u8 noiselvl5gha2 {
	srom 8-10	0x1B0 (&0x7C, >>2)
}
u8 noiselvl5gla0 {
	srom 8-10	0x1AD (&0x1F)
}
u8 noiselvl5gla1 {
	srom 8-10	u16 0x1AC (&0x3E0, >>5)
}
u8 noiselvl5gla2 {
	srom 8-10	0x1AC (&0x7C, >>2)
}
u8 noiselvl5gma0 {
	srom 8-10	0x1AF (&0x1F)
}
u8 noiselvl5gma1 {
	srom 8-10	u16 0x1AE (&0x3E0, >>5)
}
u8 noiselvl5gma2 {
	srom 8-10	0x1AE (&0x7C, >>2)
}
u8 noiselvl5gua0 {
	srom 8-10	0x1B3 (&0x1F)
}
u8 noiselvl5gua1 {
	srom 8-10	u16 0x1B2 (&0x3E0, >>5)
}
u8 noiselvl5gua2 {
	srom 8-10	0x1B2 (&0x7C, >>2)
}

u8 pcieingress_war {
	srom 8-10	0x1A7 (&0xF)
}

u8 pdoffsetcckma0 {
	srom >= 11	0x18F (&0xF)
}
u8 pdoffsetcckma1 {
	srom >= 11	0x18F (&0xF0, >>4)
}
u8 pdoffsetcckma2 {
	srom >= 11	0x18E (&0xF)
}

u8 sar2g {
	srom 9-10	0x1A9
	srom >= 11	0x1BB
}
u8 sar5g {
	srom 9-10	0x1A8
	srom >= 11	0x1BA
}

u32[5] swctrlmap_2g {
	srom 10	u32[4] 0x1B8, u16 0x1C8
}

u16 tssifloor2g {
	srom >= 11	0xBE (&0x3FF)
}
u16[4] tssifloor5g {
	srom >= 11	0xC0 (&0x3FF)
}

u8 txidxcap2g {
	srom >= 11	u16 0x1A8 (&0xFF0, >>4)
}
u8 txidxcap5g {
	srom >= 11	u16 0x1AC (&0xFF0, >>4)
}

#
# Any variables defined within a `struct` block will be interpreted relative to
# the provided array of SPROM base addresses; this is used to define
# a common layout defined at the given base addresses.
#
# To produce SPROM variable names matching those used in the Broadcom HND
# ASCII 'key=value\0' NVRAM, the index number of the variable's
# struct instance will be appended (e.g., given a variable of noiselvl5ga, the
# generated variable instances will be named noiselvl5ga0, noiselvl5ga1,
# noiselvl5ga2, noiselvl5ga3 ...)
#

# PHY chain[0-4] parameters
struct phy_chains[] {
	srom 4-7	[0x080, 0x0AE, 0x0DC, 0x10A]
	srom 8-10	[0x0C0, 0x0E0, 0x100, 0x120]
	srom >= 11	[0x0D8, 0x100, 0x128]

	# AC-PHY PA parameters
	u8[4] maxp5ga {
		srom 4-7	u8 0xB
		srom 8-10	u8 0x9
		srom >= 11	u8 0xD, u8 0xC, u8 0xF, u8 0xE
	}
	u16[3] pa2ga {
		srom >= 11	0x2
	}
	u8 maxp2ga {
		srom 4-7	0x1
		srom 8-10	0x1
		srom >= 11	0x1
	}
	u16[12] pa5ga {
		srom >= 11	0x10
	}	

	# AC-PHY rxgains
	u8 rxgains5ghtrelnabypa {
		srom >= 11	0x8 (&0x80, >>7)
	}
	u8 rxgains5ghelnagaina {
		srom >= 11	0x8 (&0x7)
	}
	u8 rxgains5gelnagaina {
		srom >= 11	0xA (&0x7)
	}
	u8 rxgains5gmtrelnabypa {
		srom >= 11	0x9 (&0x80, >>7)
	}
	u8 rxgains2gtrelnabypa {
		srom >= 11	0xB (&0x80, >>7)
	}
	u8 rxgains5gmtrisoa {
		srom >= 11	0x9 (&0x78, >>3)
	}
	u8 rxgains5gmelnagaina {
		srom >= 11	0x9 (&0x7)
	}
	u8 rxgains2gelnagaina {
		srom >= 11	0xB (&0x7)
	}
	u8 rxgains5gtrisoa {
		srom >= 11	0xA (&0x78, >>3)
	}
	u8 rxgains5gtrelnabypa {
		srom >= 11	0xA (&0x80, >>7)
	}
	u8 rxgains2gtrisoa {
		srom >= 11	0xB (&0x78, >>3)
	}
	u8 rxgains5ghtrisoa {
		srom >= 11	0x8 (&0x78, >>3)
	}

	# 11n PA parameters
	u16 pa5gw2a {
		srom 4-7	0x12
		srom 8-10	0x10
	}
	u16 pa5ghw1a {
		srom 4-7	0x20
		srom 8-10	0x1A
	}
	u16 pa5glw3a {
		srom 4-7	0x1C
	}
	u16 pa5glw1a {
		srom 4-7	0x18
		srom 8-10	0x14
	}
	u16 pa5gw1a {
		srom 4-7	0x10
		srom 8-10	0xE
	}
	u16 pa5glw0a {
		srom 4-7	0x16
		srom 8-10	0x12
	}
	u16 pa5gw3a {
		srom 4-7	0x14
	}
	u16 pa5glw2a {
		srom 4-7	0x1A
		srom 8-10	0x16
	}
	u16 pa5ghw3a {
		srom 4-7	0x24
	}
	u16 pa5gw0a {
		srom 4-7	0xE
		srom 8-10	0xC
	}
	u8 maxp5gha {
		srom 4-7	0xD
		srom 8-10	0xB
	}
	u16 pa5ghw2a {
		srom 4-7	0x22
		srom 8-10	0x1C
	}
	u16 pa5ghw0a {
		srom 4-7	0x1E
		srom 8-10	0x18
	}
	u16 pa2gw3a {
		srom 4-7	0x8
	}
	u16 pa2gw2a {
		srom 4-7	0x6
		srom 8-10	0x6
	}
	u16 pa2gw1a {
		srom 4-7	0x4
		srom 8-10	0x4
	}
	u16 pa2gw0a {
		srom 4-7	0x2
		srom 8-10	0x2
	}
	u8 maxp5gla {
		srom 4-7	0xC
		srom 8-10	0xA
	}
	u8 itt5ga {
		srom 4-7	0xA
		srom 8-10	0x8
	}
	u8 itt2ga {
		srom 4-7	0x0
		srom 8-10	0x0
	}
}