1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
/*-
* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
* provided that the following conditions are met:
* 1. The materials contained herein are unmodified and are used
* unmodified.
* 2. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following NO
* ''WARRANTY'' disclaimer below (''Disclaimer''), without
* modification.
* 3. Redistributions in binary form must reproduce at minimum a
* disclaimer similar to the Disclaimer below and any redistribution
* must be conditioned upon including a substantially similar
* Disclaimer requirement for further binary redistribution.
* 4. Neither the names of the above-listed copyright holders nor the
* names of any contributors may be used to endorse or promote
* product derived from this software without specific prior written
* permission.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
* $Id: ah_osdep.h,v 1.10 2003/11/01 01:21:31 sam Exp $
*/
#ifndef _ATH_AH_OSDEP_H_
#define _ATH_AH_OSDEP_H_
/*
* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/endian.h>
#include <machine/bus.h>
typedef void* HAL_SOFTC;
typedef bus_space_tag_t HAL_BUS_TAG;
typedef bus_space_handle_t HAL_BUS_HANDLE;
typedef bus_addr_t HAL_BUS_ADDR;
/*
* Delay n microseconds.
*/
extern void ath_hal_delay(int);
#define OS_DELAY(_n) ath_hal_delay(_n)
#define OS_INLINE __inline
#define OS_MEMZERO(_a, _size) bzero((_a), (_size))
#define OS_MEMCPY(_dst, _src, _size) bcopy((_src), (_dst), (_size))
#define OS_MACEQU(_a, _b) \
(bcmp((_a), (_b), IEEE80211_ADDR_LEN) == 0)
struct ath_hal;
extern u_int32_t ath_hal_getuptime(struct ath_hal *);
#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
/*
* Register read/write; we assume the registers will always
* be memory-mapped. Note that register accesses are done
* using target-specific functions when debugging is enabled
* (AH_DEBUG) or we are explicitly configured this way. The
* latter is used on some platforms where the full i/o space
* cannot be directly mapped.
*/
#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
#else
/*
* The hardware registers are native little-endian byte order.
* Big-endian hosts are handled by enabling hardware byte-swap
* of register reads and writes at reset. But the PCI clock
* domain registers are not byte swapped! Thus, on big-endian
* platforms we have to byte-swap thoese registers specifically.
* Most of this code is collapsed at compile time because the
* register values are constants.
*/
#define AH_LITTLE_ENDIAN 1234
#define AH_BIG_ENDIAN 4321
#if _BYTE_ORDER == _BIG_ENDIAN
#define OS_REG_WRITE(_ah, _reg, _val) do { \
if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
(_reg), htole32(_val)); \
else \
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
(_reg), (_val)); \
} while (0)
#define OS_REG_READ(_ah, _reg) \
(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
(_reg))) : \
bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
#define OS_REG_WRITE(_ah, _reg, _val) \
bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
#define OS_REG_READ(_ah, _reg) \
((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
#endif /* _BYTE_ORDER */
#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
#ifdef AH_DEBUG_ALQ
extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
#else
#define OS_MARK(_ah, _id, _v)
#endif
#endif /* _ATH_AH_OSDEP_H_ */
|
