1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/*-
* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
* All rights reserved.
*
* Based on OMAP3 INTC code by Ben Gray
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#define INTC_REVISION 0x00
#define INTC_SYSCONFIG 0x10
#define INTC_SYSSTATUS 0x14
#define INTC_SIR_IRQ 0x40
#define INTC_CONTROL 0x48
#define INTC_THRESHOLD 0x68
#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))
struct ti_aintc_softc {
device_t sc_dev;
struct resource * aintc_res[3];
bus_space_tag_t aintc_bst;
bus_space_handle_t aintc_bsh;
uint8_t ver;
};
static struct resource_spec ti_aintc_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
};
static struct ti_aintc_softc *ti_aintc_sc = NULL;
#define aintc_read_4(reg) \
bus_space_read_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg)
#define aintc_write_4(reg, val) \
bus_space_write_4(ti_aintc_sc->aintc_bst, ti_aintc_sc->aintc_bsh, reg, val)
static int
ti_aintc_probe(device_t dev)
{
if (!ofw_bus_is_compatible(dev, "ti,aintc"))
return (ENXIO);
device_set_desc(dev, "TI AINTC Interrupt Controller");
return (BUS_PROBE_DEFAULT);
}
static int
ti_aintc_attach(device_t dev)
{
struct ti_aintc_softc *sc = device_get_softc(dev);
uint32_t x;
sc->sc_dev = dev;
if (ti_aintc_sc)
return (ENXIO);
if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
ti_aintc_sc = sc;
x = aintc_read_4(INTC_REVISION);
device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
/* SoftReset */
aintc_write_4(INTC_SYSCONFIG, 2);
/* Wait for reset to complete */
while(!(aintc_read_4(INTC_SYSSTATUS) & 1));
/*Set Priority Threshold */
aintc_write_4(INTC_THRESHOLD, 0xFF);
return (0);
}
static device_method_t ti_aintc_methods[] = {
DEVMETHOD(device_probe, ti_aintc_probe),
DEVMETHOD(device_attach, ti_aintc_attach),
{ 0, 0 }
};
static driver_t ti_aintc_driver = {
"aintc",
ti_aintc_methods,
sizeof(struct ti_aintc_softc),
};
static devclass_t ti_aintc_devclass;
DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 0, 0);
int
arm_get_next_irq(int last_irq)
{
uint32_t active_irq;
if (last_irq != -1) {
aintc_write_4(INTC_ISR_CLEAR(last_irq >> 5),
1UL << (last_irq & 0x1F));
aintc_write_4(INTC_CONTROL,1);
}
/* Get the next active interrupt */
active_irq = aintc_read_4(INTC_SIR_IRQ);
/* Check for spurious interrupt */
if ((active_irq & 0xffffff80)) {
device_printf(ti_aintc_sc->sc_dev,
"Spurious interrupt detected (0x%08x)\n", active_irq);
return -1;
}
if (active_irq != last_irq)
return active_irq;
else
return -1;
}
void
arm_mask_irq(uintptr_t nb)
{
aintc_write_4(INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
}
void
arm_unmask_irq(uintptr_t nb)
{
aintc_write_4(INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));
}
|
