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/*-
* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _A31_CLK_H_
#define _A31_CLK_H_
#define A31_CCM_PLL1_CFG 0x0000
#define A31_CCM_PLL2_CFG 0x0008
#define A31_CCM_PLL3_CFG 0x0010
#define A31_CCM_PLL4_CFG 0x0018
#define A31_CCM_PLL5_CFG 0x0020
#define A31_CCM_PLL6_CFG 0x0028
#define A31_CCM_PLL7_CFG 0x0030
#define A31_CCM_PLL8_CFG 0x0038
#define A31_CCM_MIPI_PLL_CFG 0x0040
#define A31_CCM_PLL9_CFG 0x0044
#define A31_CCM_PLL10_CFG 0x0048
#define A31_CCM_AXI_CFG_REG 0x0050
#define A31_CCM_AHB1_APB1_CFG 0x0054
#define A31_CCM_APB2_CLK_DIV 0x0058
#define A31_CCM_AHB_GATING0 0x0060
#define A31_CCM_AHB_GATING1 0x0064
#define A31_CCM_APB1_GATING 0x0068
#define A31_CCM_APB2_GATING 0x006c
#define A31_CCM_NAND0_SCLK_CFG 0x0080
#define A31_CCM_NAND1_SCLK_CFG 0x0084
#define A31_CCM_MMC0_SCLK_CFG 0x0088
#define A31_CCM_MMC1_SCLK_CFG 0x008c
#define A31_CCM_MMC2_SCLK_CFG 0x0090
#define A31_CCM_MMC3_SCLK_CFG 0x0094
#define A31_CCM_TS_CLK 0x0098
#define A31_CCM_SS_CLK 0x009c
#define A31_CCM_SPI0_CLK 0x00a0
#define A31_CCM_SPI1_CLK 0x00a4
#define A31_CCM_SPI2_CLK 0x00a8
#define A31_CCM_SPI3_CLK 0x00ac
#define A31_CCM_DAUDIO0_CLK 0x00b0
#define A31_CCM_DAUDIO1_CLK 0x00b4
#define A31_CCM_USBPHY_CLK 0x00cc
#define A31_CCM_GMAC_CLK 0x00d0
#define A31_CCM_MDFS_CLK 0x00f0
#define A31_CCM_DRAM_CLK 0x00f4
#define A31_CCM_DRAM_GATING 0x0100
#define A31_CCM_BE0_SCLK 0x0104
#define A31_CCM_BE1_SCLK 0x0108
#define A31_CCM_FE0_CLK 0x010c
#define A31_CCM_FE1_CLK 0x0110
#define A31_CCM_MP_CLK 0x0114
#define A31_CCM_LCD0_CH0_CLK 0x0118
#define A31_CCM_LCD1_CH0_CLK 0x011c
#define A31_CCM_LCD0_CH1_CLK 0x012c
#define A31_CCM_LCD1_CH1_CLK 0x0130
#define A31_CCM_CSI0_CLK 0x0134
#define A31_CCM_CSI1_CLK 0x0138
#define A31_CCM_VE_CLK 0x013c
#define A31_CCM_AUDIO_CODEC_CLK 0x0140
#define A31_CCM_AVS_CLK 0x0144
#define A31_CCM_DIGITAL_MIC_CLK 0x0148
#define A31_CCM_HDMI_CLK 0x0150
#define A31_CCM_PS_CLK 0x0154
#define A31_CCM_MBUS_SCLK_CFG0 0x015c
#define A31_CCM_MBUS_SCLK_CFG1 0x0160
#define A31_CCM_MIPI_DSI_CLK 0x0168
#define A31_CCM_MIPI_CSI0_CLK 0x016c
#define A31_CCM_DRC0_SCLK_CFG 0x0180
#define A31_CCM_DRC1_SCLK_CFG 0x0184
#define A31_CCM_DEU0_SCLK_CFG 0x0188
#define A31_CCM_DEU1_SCLK_CFG 0x018c
#define A31_CCM_GPU_CORE_CLK 0x01a0
#define A31_CCM_GPU_MEM_CLK 0x01a4
#define A31_CCM_GPU_HYD_CLK 0x01a8
#define A31_CCM_ATS_CLK 0x01b0
#define A31_CCM_TRACE_CLK 0x01b4
#define A31_CCM_PLL_LOCK_CFG 0x0200
#define A31_CCM_PLL1_LOCK_CFG 0x0204
#define A31_CCM_PLL1_BIAS 0x0220
#define A31_CCM_PLL2_BIAS 0x0224
#define A31_CCM_PLL3_BIAS 0x0228
#define A31_CCM_PLL4_BIAS 0x022c
#define A31_CCM_PLL5_BIAS 0x0230
#define A31_CCM_PLL6_BIAS 0x0234
#define A31_CCM_PLL7_BIAS 0x0238
#define A31_CCM_PLL8_BIAS 0x023c
#define A31_CCM_PLL9_BIAS 0x0240
#define A31_CCM_MIPI_PLL_BIAS 0x0244
#define A31_CCM_PLL10_BIAS 0x0248
#define A31_CCM_PLL1_PAT_CFG 0x0280
#define A31_CCM_PLL2_PAT_CFG 0x0284
#define A31_CCM_PLL3_PAT_CFG 0x0288
#define A31_CCM_PLL4_PAT_CFG 0x028c
#define A31_CCM_PLL5_PAT_CFG 0x0290
#define A31_CCM_PLL6_PAT_CFG 0x0294
#define A31_CCM_PLL7_PAT_CFG 0x0298
#define A31_CCM_PLL8_PAT_CFG 0x029c
#define A31_CCM_MIPI_PLL_PAT_CFG 0x02a0
#define A31_CCM_PLL9_PAT_CFG 0x02a4
#define A31_CCM_PLL10_PAT_CFG 0x02a8
#define A31_CCM_AHB1_RST_REG0 0x02c0
#define A31_CCM_AHB1_RST_REG1 0x02c4
#define A31_CCM_AHB1_RST_REG2 0x02c8
#define A31_CCM_APB1_RST 0x02d0
#define A31_CCM_APB2_RST 0x02d8
#define A31_CCM_CLK_OUTA 0x0300
#define A31_CCM_CLK_OUTB 0x0304
#define A31_CCM_CLK_OUTC 0x0308
/* PLL6_CFG_REG */
#define A31_CCM_PLL6_CFG_REG_LOCK (1 << 28)
/* AHB_GATING_REG0 */
#define A31_CCM_AHB_GATING_OHCI2 (1 << 31)
#define A31_CCM_AHB_GATING_OHCI1 (1 << 30)
#define A31_CCM_AHB_GATING_OHCI0 (1 << 29)
#define A31_CCM_AHB_GATING_EHCI1 (1 << 27)
#define A31_CCM_AHB_GATING_EHCI0 (1 << 26)
#define A31_CCM_AHB_GATING_USBDRD (1 << 24)
#define A31_CCM_AHB_GATING_GMAC (1 << 17)
#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8)
#define A31_CCM_PLL_CFG_ENABLE (1U << 31)
#define A31_CCM_PLL_CFG_BYPASS (1U << 30)
#define A31_CCM_PLL_CFG_PLL5 (1U << 25)
#define A31_CCM_PLL_CFG_PLL6 (1U << 24)
#define A31_CCM_PLL_CFG_FACTOR_N 0x1f00
#define A31_CCM_PLL_CFG_FACTOR_N_SHIFT 8
#define A31_CCM_PLL_CFG_FACTOR_K 0x30
#define A31_CCM_PLL_CFG_FACTOR_K_SHIFT 4
#define A31_CCM_PLL_CFG_FACTOR_M 0x3
/* APB2_GATING */
#define A31_CCM_APB2_GATING_TWI (1 << 0)
/* AHB1_RST_REG0 */
#define A31_CCM_AHB1_RST_REG0_OHCI2 (1 << 31)
#define A31_CCM_AHB1_RST_REG0_OHCI1 (1 << 30)
#define A31_CCM_AHB1_RST_REG0_OHCI0 (1 << 29)
#define A31_CCM_AHB1_RST_REG0_EHCI1 (1 << 27)
#define A31_CCM_AHB1_RST_REG0_EHCI0 (1 << 26)
#define A31_CCM_AHB1_RST_REG0_GMAC (1 << 17)
#define A31_CCM_AHB1_RST_REG0_SDMMC (1 << 8)
/* APB2_RST_REG */
#define A31_CCM_APB2_RST_TWI (1 << 0)
/* GMAC */
#define A31_CCM_GMAC_CLK_DELAY_SHIFT 10
#define A31_CCM_GMAC_CLK_MODE_MASK 0x7
#define A31_CCM_GMAC_MODE_RGMII (1 << 2)
#define A31_CCM_GMAC_CLK_MII 0x0
#define A31_CCM_GMAC_CLK_EXT_RGMII 0x1
#define A31_CCM_GMAC_CLK_RGMII 0x2
/* SD/MMC */
#define A31_CCM_SD_CLK_SRC_SEL 0x3000000
#define A31_CCM_SD_CLK_SRC_SEL_SHIFT 24
#define A31_CCM_SD_CLK_SRC_SEL_OSC24M 0
#define A31_CCM_SD_CLK_SRC_SEL_PLL6 1
#define A31_CCM_SD_CLK_PHASE_CTR 0x700000
#define A31_CCM_SD_CLK_PHASE_CTR_SHIFT 20
#define A31_CCM_SD_CLK_DIV_RATIO_N 0x30000
#define A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT 16
#define A31_CCM_SD_CLK_OPHASE_CTR 0x700
#define A31_CCM_SD_CLK_OPHASE_CTR_SHIFT 8
#define A31_CCM_SD_CLK_DIV_RATIO_M 0xf
/* USB */
#define A31_CCM_USBPHY_CLK_GATING_OHCI2 (1 << 18)
#define A31_CCM_USBPHY_CLK_GATING_OHCI1 (1 << 17)
#define A31_CCM_USBPHY_CLK_GATING_OHCI0 (1 << 16)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY2 (1 << 10)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY1 (1 << 9)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY0 (1 << 8)
#define A31_CCM_USBPHY_CLK_USBPHY2_RST (1 << 2)
#define A31_CCM_USBPHY_CLK_USBPHY1_RST (1 << 1)
#define A31_CCM_USBPHY_CLK_USBPHY0_RST (1 << 0)
#define A31_CCM_CLK_REF_FREQ 24000000U
int a31_clk_gmac_activate(phandle_t);
int a31_clk_mmc_activate(int);
int a31_clk_mmc_cfg(int, int);
int a31_clk_i2c_activate(int);
int a31_clk_ehci_activate(void);
int a31_clk_ehci_deactivate(void);
#endif /* _A31_CLK_H_ */
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