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.\" ========================================================================
.\"
.IX Title "OPENSSL_ia32cap 3"
.TH OPENSSL_ia32cap 3 "2009-06-14" "0.9.8k" "OpenSSL"
.SH "NAME"
OPENSSL_ia32cap \- finding the IA\-32 processor capabilities
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 2
\& unsigned long *OPENSSL_ia32cap_loc(void);
\& #define OPENSSL_ia32cap (*(OPENSSL_ia32cap_loc()))
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
Value returned by \fIOPENSSL_ia32cap_loc()\fR is address of a variable
containing \s-1IA\-32\s0 processor capabilities bit vector as it appears in \s-1EDX\s0
register after executing \s-1CPUID\s0 instruction with EAX=1 input value (see
Intel Application Note #241618). Naturally it's meaningful on IA\-32[E]
platforms only. The variable is normally set up automatically upon
toolkit initialization, but can be manipulated afterwards to modify
crypto library behaviour. For the moment of this writing six bits are
significant, namely:
.PP
1. bit #28 denoting Hyperthreading, which is used to distiguish
cores with shared cache;
2. bit #26 denoting \s-1SSE2\s0 support;
3. bit #25 denoting \s-1SSE\s0 support;
4. bit #23 denoting \s-1MMX\s0 support;
5. bit #20, reserved by Intel, is used to choose between \s-1RC4\s0 code
pathes;
6. bit #4 denoting presence of Time-Stamp Counter.
.PP
For example, clearing bit #26 at run-time disables high-performance
\&\s-1SSE2\s0 code present in the crypto library. You might have to do this if
target OpenSSL application is executed on \s-1SSE2\s0 capable \s-1CPU\s0, but under
control of \s-1OS\s0 which does not support \s-1SSE2\s0 extentions. Even though you
can manipulate the value programmatically, you most likely will find it
more appropriate to set up an environment variable with the same name
prior starting target application, e.g. on Intel P4 processor 'env
OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
without modifying the application source code. Alternatively you can
reconfigure the toolkit with no\-sse2 option and recompile.
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