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//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//
// These instruction format definitions are structured to match the
// description in the RISC-V User-Level ISA specification as closely as
// possible. For instance, the specification describes instructions with the
// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
// reflected in the order of parameters to each instruction class.
//
// One area of divergence is in the description of immediates. The
// specification describes immediate encoding in terms of bit-slicing
// operations on the logical value represented. The immediate argument to
// these instruction formats instead represents the bit sequence that will be
// inserted into the instruction. e.g. although JAL's immediate is logically
// a 21-bit value (where the LSB is always zero), we describe it as an imm20
// to match how it is encoded.
//
//===----------------------------------------------------------------------===//
class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
field bits<32> Inst;
let Size = 4;
bits<7> Opcode = 0;
let Inst{6-0} = Opcode;
let Namespace = "RISCV";
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
}
// Pseudo instructions
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern> {
let isPseudo = 1;
}
class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern>
{
bits<5> rs2;
bits<5> rs1;
bits<5> rd;
let Inst{31-25} = funct7;
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode;
}
class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<12> imm12;
bits<5> rs1;
bits<5> rd;
let Inst{31-20} = imm12;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode;
}
class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<5> shamt;
bits<5> rs1;
bits<5> rd;
let Inst{31} = 0;
let Inst{30} = arithshift;
let Inst{29-25} = 0;
let Inst{24-20} = shamt;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode;
}
class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<12> imm12;
bits<5> rs2;
bits<5> rs1;
let Inst{31-25} = imm12{11-5};
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = imm12{4-0};
let Opcode = opcode;
}
class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<12> imm12;
bits<5> rs2;
bits<5> rs1;
let Inst{31} = imm12{11};
let Inst{30-25} = imm12{9-4};
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-8} = imm12{3-0};
let Inst{7} = imm12{10};
let Opcode = opcode;
}
class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<20> imm20;
bits<5> rd;
let Inst{31-12} = imm20;
let Inst{11-7} = rd;
let Opcode = opcode;
}
class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
: RISCVInst<outs, ins, asmstr, pattern>
{
bits<20> imm20;
bits<5> rd;
let Inst{31} = imm20{19};
let Inst{30-21} = imm20{9-0};
let Inst{20} = imm20{10};
let Inst{19-12} = imm20{18-11};
let Inst{11-7} = rd;
let Opcode = opcode;
}
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