1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
//===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the AVRMCCodeEmitter class.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_AVR_CODE_EMITTER_H
#define LLVM_AVR_CODE_EMITTER_H
#include "AVRFixupKinds.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/Support/DataTypes.h"
#define GET_INSTRINFO_OPERAND_TYPES_ENUM
#include "AVRGenInstrInfo.inc"
namespace llvm {
class MCContext;
class MCExpr;
class MCFixup;
class MCInst;
class MCInstrInfo;
class MCOperand;
class MCSubtargetInfo;
class raw_ostream;
/// Writes AVR machine code to a stream.
class AVRMCCodeEmitter : public MCCodeEmitter {
public:
AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
: MCII(MCII), Ctx(Ctx) {}
private:
/// Finishes up encoding an LD/ST instruction.
/// The purpose of this function is to set an bit in the instruction
/// which follows no logical pattern. See the implementation for details.
unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
/// Gets the encoding for a conditional branch target.
template <AVR::Fixups Fixup>
unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Encodes the `PTRREGS` operand to a load or store instruction.
unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Encodes a `register+immediate` operand for `LDD`/`STD`.
unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Takes the compliment of a number (~0 - val).
unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Encodes an immediate value with a given fixup.
template <AVR::Fixups Fixup>
unsigned encodeImm(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Gets the encoding of the target for the `CALL k` instruction.
unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// TableGen'ed function to get the binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Returns the binary encoding of operand.
///
/// If the machine operand requires relocation, the relocation is recorded
/// and zero is returned.
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
raw_ostream &OS) const;
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
AVRMCCodeEmitter(const AVRMCCodeEmitter &) = delete;
void operator=(const AVRMCCodeEmitter &) = delete;
const MCInstrInfo &MCII;
MCContext &Ctx;
};
} // end namespace of llvm.
#endif // LLVM_AVR_CODE_EMITTER_H
|
