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* If an interrupt on an I/O APIC is moved to a different CPU after it hasjhb2011-01-131-2/+0
* Revert to using bus_size_t for the bounce_zone's alignment member.mdf2011-01-131-3/+10
* Fix a brain fart. Since this file is shared between i386 and amd64, amdf2011-01-121-3/+3
* sysctl(9) cleanup checkpoint: amd64 GENERIC builds cleanly.mdf2011-01-121-2/+2
* Remove unneeded includes of <sys/linker_set.h>. Other headers that usejhb2011-01-111-1/+0
* Copy powerpc/include/_inttypes.h to x86 and replace i386/amd64/pc98tijl2011-01-081-0/+221
* Drop the icu_lock spinlock while pausing briefly after masking thejhb2010-12-231-0/+2
* Merge amd64 and i386 bus.h and move the resulting header to x86. Replacetijl2010-12-202-12/+1102
* Small style fixes:jhb2010-12-161-10/+10
* Remove AMD Family 0Fh, Model 6Bh, Stepping 2 from the list of P-statejkim2010-12-091-1/+1
* Replace i386/i386/busdma_machdep.c and amd64/amd64/busdma_machdep.ccperciva2010-12-091-0/+1222
* Merge sys/amd64/amd64/tsc.c and sys/i386/i386/tsc.c and move to sys/x86/x86.jkim2010-12-081-0/+281
* Merge amd64/i386 _align.h by aligning on the size of register_t (copiedtijl2010-11-261-0/+52
* x86/local_apic: use newly added ARAT bit definitionavg2010-11-231-1/+1
* hwpstate: use CPU_FOREACH when binding to all available processorsavg2010-11-161-12/+8
* Move identical copies of apm_bios.h to sys/x86/include, replace them withjkim2010-11-111-0/+264
* make it possible to actually enable hwpstate_verboseavg2010-11-111-1/+2
* Make APM emulation look more closer to its origin. Use device_get_softc(9)jkim2010-11-101-7/+6
* Refactor acpi_machdep.c for amd64 and i386, move APM emulation into a newjkim2010-11-101-0/+490
* Move the mptable.h under x86/include/.attilio2010-11-093-2/+148
* Now OsdEnvironment.c is identical on amd64 and i386. Move it to a new home.jkim2010-11-091-0/+91
* Move the MADT parser for amd64 and i386 to sys/x86/acpica now that it isjhb2010-11-081-0/+572
* Sync the APIC startup sequence with amd64:jhb2010-11-082-12/+6
* Only dump the values of the PMC and CMCI local vector table entries on ajhb2010-11-081-4/+9
* Cosmetic change to revert one of my earlier ones.jhb2010-11-021-1/+1
* Further tweaks to the ram_attach() routine:jhb2010-11-021-9/+8
* Skip SMAP regions above 4GB on i386 since they will not fit into a long.jhb2010-11-021-12/+19
* Move <machine/apicreg.h> to <x86/apicreg.h>.jhb2010-11-015-4/+449
* Move the <machine/mca.h> header to <x86/mca.h>.jhb2010-11-013-2/+58
* - Merge ram_attach() implementation for i386 and amd64attilio2010-10-291-42/+39
* Merge nexus.c from amd64 and i386 to x86 subtree.attilio2010-10-281-0/+814
* Merge the mptable support from MD bits to x86 subtree.attilio2010-10-282-0/+1232
* Style fix.attilio2010-10-261-2/+2
* Remove usage of PRI* macro for style compliancy.attilio2010-10-261-4/+3
* Merge dump_machdep.c i386/amd64 under the x86 subtree.attilio2010-10-261-0/+374
* Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returnedjhb2010-10-251-6/+6
* atrtc: remove (pre-)historic check of RTC NVRAM at address 0x0eavg2010-10-161-4/+1
* Restore pre-r212778 optimization, skipping timer reprogramming when it ismav2010-09-181-19/+27
* Add one-shot mode support to attimer (i8254) event timer.mav2010-09-171-44/+71
* Few whitespace cleanups and comments tunings.mav2010-09-161-10/+12
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+1
* Each processor socket in a QPI system has a special PCI bus for thejhb2010-09-071-13/+45
* When DTrace is enabled, make sure we don't overwrite the IDT_DTRACE_RETrpaulo2010-08-301-0/+25
* Correctly ensure that the CPU family is 0x6, not non-zero.jhb2010-08-251-1/+2
* Intel QPI chipsets actually provide two extra "non-core" PCI buses thatjhb2010-08-251-0/+286
* Enable timer interrupt before starting timer. This allows to handle verymav2010-08-241-8/+7
* When performing a sanity check on the SRAT table to ensure that eachjhb2010-07-291-1/+2
* The corrected error count field is dependent on CMCI, not TES.jhb2010-07-281-1/+1
* Add a parser for the ACPI SRAT table for amd64 and i386. It setsjhb2010-07-271-0/+329
* Increment td->td_intr_nesting_level for LAPIC timer interrupts. Among othermav2010-07-241-0/+2
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