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* MFC r293045, r293046:ian2016-01-241-1/+2
* MFC r283479:dchagin2016-01-091-4/+0
* MFC: r291121marius2015-12-271-5/+5
* MFC: r285839marius2015-07-301-1/+1
* MFC r278001:kib2015-02-071-1/+1
* MFC 259016,259019,259049,259071,259102,259110,259129,259130,259178,259179,jhb2014-03-061-7/+11
* Prefix the alias macros for members of struct __mcontext with an underscoremarius2013-07-121-20/+20
* Fix other architectures and ZFS.attilio2013-02-211-0/+1
* Reverts r234074,234105,234564,234723,234989,235231-235232 and part ofattilio2012-10-091-5/+0
* Clean up the intr* MD KPI from the SMP dependency, removing a cause ofattilio2012-04-261-2/+0
* Merge from x86:marius2012-04-131-0/+7
* Now that we have a working OF_printf() since r230631 and a OF_panic()marius2012-01-271-31/+18
* Add a comment about why contrary to what once would think running all ofmarius2011-09-301-0/+4
* It is safe to initialize locks even on early boot (and it is the sameattilio2011-09-191-5/+0
* In order to maximize the re-usability of kernel code in user space thiskmacy2011-09-161-1/+1
* - For Cheetah- and Zeus-class CPUs don't flush all unlocked entries frommarius2011-07-021-2/+3
* Correct spelling in comments.marius2011-04-221-1/+1
* Mostly revert r219468, as I had misremembered the C standard regardingmdf2011-03-111-1/+1
* Use MAXPATHLEN rather than the size of an extern array when copying themdf2011-03-101-1/+1
* Set td_kstack_pages for thread0.marius2011-02-081-0/+1
* Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.pluknet2011-01-211-2/+1
* Adjust the order of operations in spinlock_enter() and spinlock_exit() tojhb2010-11-051-3/+6
* Explicitly lower the PIL to 0 as part of enabling interrupts, similar tomarius2010-10-141-0/+1
* Remove accidentally committed test code which effectively prevented themarius2010-09-161-2/+0
* Add a VIS-based block copy function for SPARC64 V and later, whichmarius2010-09-151-1/+6
* Remove redundant raising of the PIL to PIL_TICK as the respective locoremarius2010-09-141-1/+0
* Sparc64 uses dummy cpu_idle() method. It's CPUs never sleeping. Tellmav2010-09-111-1/+1
* Move prototypes for kern_sigtimedwait() and kern_sigprocmask() tojhb2010-06-301-0/+1
* Add support for SPARC64 V (and where it already makes sense for othermarius2010-05-021-1/+5
* Don't bother enabling interrupts before we're ready to handle them. Thismarius2010-04-261-1/+15
* Change the arguments of exec_setregs() so that it receives a pointernwhitehorn2010-03-251-3/+3
* - The firmware of Sun Fire V1280 has a misfeature of setting %wstate tomarius2010-03-211-1/+2
* Some machines can not only consist of CPUs running at different speedsmarius2010-02-201-14/+16
* - Search the whole OFW device tree instead of only the children of themarius2010-02-131-22/+89
* - Demapping unused kernel TLB slots has proven to work reliably so movemarius2010-01-021-11/+3
* Unroll copying of the registers in {g,s}et_mcontext() and limit itmarius2009-11-171-6/+56
* In r197963, a race with thread being selected for signal deliverykib2009-10-271-5/+1
* - Work around the broken loader behavior of not demapping no longermarius2009-06-281-8/+19
* Implement a facility for dynamic per-cpu variables.jeff2009-06-231-1/+4
* Add cpu_flush_dcache() for use after non-DMA based I/O so that amarcel2009-05-181-0/+10
* Revert r190105 so that removing options KDB but DDB or GDB beingmarius2009-03-201-0/+2
* There's no need to wrap kdb_enter() in #ifdef KDB as it's always available.marius2009-03-191-2/+0
* - Currently the PMAP code is laid out to let the kernel TSB cover themarius2009-01-011-1/+16
* Modularize the Open Firmware client interface to allow run-time switchingnwhitehorn2008-12-201-11/+10
* Use the spitfire VIS block copy/zero functions also with cheetah-marius2008-11-161-1/+7
* Use the PROM provided SUNW,set-trap-table to take over the trapmarius2008-09-041-0/+10
* Ensure the caches have the desired configuration (see especiallymarius2008-09-041-0/+1
* Flesh out MMU and cache handling of cheetah-class CPUs.marius2008-09-041-0/+6
* - USIII-based machines can consist of CPUs running at differentmarius2008-09-031-44/+39
* - USIII-based machines can consist of CPUs having different cachemarius2008-09-021-19/+34
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