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* Add support for SPARC64 V (and where it already makes sense for othermarius2010-05-021-0/+4
| | | | | | | | | HAL/Fujitsu) CPUs. For the most part this consists of fleshing out the MMU and cache handling, it doesn't add pmap optimizations possible with these CPU, yet, though. With these changes FreeBSD runs stable on Fujitsu Siemens PRIMEPOWER 250 and likely also other models based on SPARC64 V like 450, 650 and 850. Thanks go to Michael Moll for providing access to a PRIMEPOWER 250.
* Some machines can not only consist of CPUs running at different speedsmarius2010-02-201-1/+1
| | | | | | | | | but also of different types, f.e. Sun Fire V890 can be equipped with a mix of UltraSPARC IV and IV+ CPUs, requiring different MMU initialization and different workarounds for model specific errata. Therefore move the CPU implementation number from a global variable to the per-CPU data. Functions which are called before the latter is available are passed the implementation number as a parameter now.
* - USIII-based machines can consist of CPUs having different cachemarius2008-09-021-13/+3
| | | | | | | | sizes (and running at different frequencies) so move the cacheinfo to the PCPU data. While at it, remove some redundant and/or unused members from struct cacheinfo. - In sparc64_init don't assume the first CPU node we find in the OFW device tree is the BSP.
* cosmetic changes and style fixesmarius2008-08-131-10/+10
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* Convert the remainder of the low hanging fruits regarding includingmarius2007-01-191-2/+8
| | | | | | | | headers in .S directly rather than getting to their macros through genassym.c/assym.s so there are less headers genassym.c has to be kept in sync with. While at it fix some stytle(9) bugs (indentation, prototype format, sort headers, etc) and remove trailing whitespace.
* /* -> /*- for license, minor formatting changesimp2005-01-071-1/+1
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* Remove advertising clause from University of California Regent'simp2004-04-071-2/+0
| | | | | | | license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson. Approved by: core, peter, alc, rwatson
* Fix a bug in the data access error recorvery. Before re-enabling the datajake2003-11-111-0/+9
| | | | | | | | | | | | cache after a data access error we must discard all cache lines. When disabled existing cache lines are not invalidated by stores to memory, so we risk reading stale data that was cached before the data access error if we don't flush them. This is especially fatal when the memory involved is the active part of the kernel or user stack. For good measure we also flush the instruction cache. This fixes random crashes when the X server probes the PCI bus through /dev/pci.
* Avoid exposing declarations for kernel variables to userland.jake2003-07-171-0/+4
| | | | PR: 54528
* Use vm_paddr_t for physical addresses.jake2003-04-081-6/+6
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* - Remove unused cache flushing routines. These will not necessary workjake2003-03-191-57/+19
| | | | | | | | | | | | | | | | | | | on future UltraSPARC cpus for which the data cache is not direct mapped. - Move UltraSPARC I and II (spitfire, blackbird, sapphire, sabre) specific functions to spitfire.c, and add cheetah.c for UltraSPARC III specific functions. Initially just cache flushing, but there are a few other functions that will need to move here. - Add an ipi handler for data cache flushing on UltraSPARC III. - Use function pointers to select the right cache flushing functions based on cpu_impl. With this it is possible to boot single user from an mfs root on UltraSPARC III systems, including spinning up secondary processors. There is currently no support for the host to pci bridge, and no documentation for it is publically available. Thanks to Oleg Derevenetz for providing access to a system with UltraSPARC III+ cpus.
* Add SMP aware cache flushing functions, which operate on a single physicaljake2002-05-201-15/+38
| | | | | page. These send IPIs if necessary in order to keep the caches in sync on all cpus.
* Remove __P.alfred2002-03-211-9/+9
| | | | | | profile.h and bus.h were excluded because there is currently WIP. Reviewed by: tmm
* Use stxa_sync() when accessing the diagnostic registers to invalidatetmm2002-02-131-1/+2
| | | | | caches; this is needed to avoid undefined behaviour. Clean up a bit.
* Prototype dcache_inval_phys.jake2001-12-291-0/+1
| | | | Submitted by: tmm
* Add cache handling code for sparc64.tmm2001-11-091-0/+126
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