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* Remove bogus __unused attribute from hrowpic_eoi().rpaulo2012-07-011-1/+1
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* Fix the interrupt code, broken 7 months ago. The interrupt frameworkmarcel2011-01-291-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process. OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken. This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN. Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning. Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work. No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months... Sponsored by: Juniper Networks
* Move the EOI logic when starting ithreads into intr_machdep instead ofnwhitehorn2010-07-061-3/+0
| | | | | relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
* Remove the unneeded header <machine/intr.h>.marcel2010-07-021-1/+0
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* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-181-0/+11
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Allow Heathrow-based machines to boot a kernel containing option SMPnwhitehorn2009-10-241-1/+7
| | | | without panicing.
* Convert PowerPC AIM PCI and nexus busses to standard OFW bus interface. Thisnwhitehorn2008-10-141-1/+0
| | | | | | | | | | | simplifies certain device attachments (Kauai ATA, for instance), and makes possible others on new hardware. On G5 systems, there are several otherwise standard PCI devices (Serverworks SATA) that will not allow their interrupt properties to be written, so this information must be supplied directly from Open Firmware. Obtained from: sparc64
* Add PIC support for IPIs. When registering an interrupt handler,marcel2008-02-121-1/+9
| | | | | | the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
* Revamp the interrupt handling in support of INTR_FILTER. This includes:marcel2007-08-111-328/+108
| | | | | | | | | | | | | | | | | | | | | | | o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-4/+5
| | | | | | | | | | | | | bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
* Set the rid for any resource obtained from rman_resource_reserve.imp2006-04-201-0/+1
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* /* -> /*- for license, minor formatting changesimp2005-01-071-1/+1
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* Instead of "OpenFirmware", "openfirmware", etc. use the official spellingmarius2004-08-161-1/+1
| | | | | | "Open Firmware" from IEEE 1275 and OpenFirmware.org (no pun intended). Ok'ed by: tmm
* - Introduce an ofw_bus kobj-interface for retrieving the OFW node and amarius2004-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit. Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
* - Use the rman_get_* functions instead of reaching into struct resource.marius2004-08-111-7/+8
| | | | | | | | - Remove __RMAN_RESORUCE_VISIBLE again. It's no longer required either because of the above change or because struct rman is no longer hidden. Reviewed by: grehan Tested by: cross-compile on i386
* Catch up with __RMAN_RESOURCE_VISIBLE changegrehan2004-07-011-0/+1
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* Catchup to now-required <sys/module.h> for PowerPCgrehan2004-06-251-0/+1
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* Convert callers to the new bus_alloc_resource_any(9) API.njl2004-03-171-1/+1
| | | | | Submitted by: Mark Santcroos <marks@ripe.net> Reviewed by: imp, dfr, bde
* Use a device identify entry point to attach to nexus, since thegrehan2004-01-131-9/+27
| | | | nexus code no longer searches for interrupt controllers.
* Widen the enable/disable helper function's argument in line with thepeter2003-11-171-4/+4
| | | | ithread_create() changes etc. This should be mostly a NOP.
* A module to handle the interrupt controller on Heathrow/Paddingtongrehan2003-06-281-0/+468
MacIO chips, found on older Mac G3's.
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