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* MFC r261423, r261424, r261516, r261513, r261562, r261563, r261564, r261565,ian2014-05-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | r261596, r261606 Add the imx sdhci controller. Move Open Firmware device root on PowerPC, ARM, and MIPS systems to a sub-node of nexus (ofwbus) rather than direct attach under nexus. This fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier. SPARC is unchanged. Add the missing ')' at end of sentence. Reword it to use a more common idiom. Pass the kernel physical address to initarm through the boot param struct. Make functions only used in vfp.c static, and remove vfp_enable. Fix __syscall on armeb EABI. As it returns a 64-bit value it needs to place 32-bit data in r1, not r0. 64-bit data is already packed correctly. Use abp_physaddr for the physical address over KERNPHYSADDR. This helps us remove the need to load the kernel at a fixed address. Remove references to PHYSADDR where it's used only in debugging output. Dynamically generate the page table. This will allow us to detect the physical address we are loaded at to change the mapping.
* MFC r258800, r258802, r258805, r258806, r258807, r258851, r258857,ian2014-05-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r259199, r259484, r259513, r259514, r259516 The kernel stack guard pages are only below the stack pointer, not above. Remove unnecessary double-setting of the thread's onfault state in copyinstr(). Open Firmware mandates that certain cross-references, in particular those in /chosen, be ihandles. The ePAPR spec makes those cross-reference phandles, since FDT has no concept of ihandles. Have the OF FDT CI module interpret queries about ihandles as cross-reference phandles. Real OF systems have an ihandle under /chosen/stdout, not a phandle. Use the right type. Rearchitect platform memory map parsing to make it less Open Firmware-centric. Remove fdtbus_bs_tag definition, which is now obsolete. The remainder of this file is also slated for future demolition. Return the correct IEEE 1275 code for "nextprop". Use the common Open Firmware PCI interrupt routing code instead of the duplicate version in dev/fdt. Configure interrupt sense based on device tree information. Simplify the ofw_bus_lookup_imap() API slightly: make it allocate maskbuf internally instead of requiring the caller to allocate it.
* MFC r257995, r258244, r258246,ian2014-05-142-1/+411
| | | | | | | | | Rename the "bare" platform "mpc85xx" Also turn "bare" into a truly bare platform Move CCSR discovery into the platform module There is no reason Book-E needs to save XER and CTR on context switches.
* MFC r257702, r257745, r257746, r257747, r257751, r257791, r257793,ian2014-05-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r257794, r257795, r257992 Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiring fdtbus in most cases. Make OF_nextprop() work correctly for FDT by using the libfdt fdt_next_property_offset() API. Do not panic if pmap_mincore() is called. An addendum: it is possible, though of questionable utility, for a node to have no properties at all. Add definition for the Atheros 8021 gigabit PHY. Consolidate Apple firmware hacks and improve them by switching on the presence of mac-io devices in the tree, which uniquely identifies Apple hardware. Allow OF_decode_addr() to also be able to map resources on big-endian devices. Make tsec work with the device tree present on the RB800. Be more flexible about which compatible strings to accept. This brings up the PCI Express bus on the RB800 using the firmware device tree. Rename the "bare" platform "mpc85xx", which is what it actually is, and add actual platform probing based on PVR.
* MFC r257161, r257169, r257178, r257190, r257191ian2014-05-142-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Add pmap_mapdev_attr() and pmap_kenter_attr() interfaces. Fix concurrency issues with TLB1 updates and make pmap_kextract() search TLB1 mappings as well Interrelated improvements to early boot mappings: - Remove explicit requirement that the SOC registers be found except as an optimization (although the MPC85XX LAW drivers still require they be found externally, which should change). - Remove magic CCSRBAR_VA value. - Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and systems not in real-mode or global 1:1 maps in early boot. - Allow pmap_mapdev() on Book-E to reissue previous addresses if the area is already mapped. Additionally have it check all mappings, not just the CCSR area. Add some extra sanity checking and checks to printf format specifiers. Bump initial TLB size. The kernel is not necessarily less than 16 MB Handle (in a slightly ugly way) ePAPR-type loaders that just place a device tree into r3.
* MFC r257115, r257116, r257117ian2014-05-131-274/+75
| | | | Remove dead and duplicated code.
* MFC r256994, r257016, r257055, r257059, r257060, r257075ian2014-05-131-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two new interfaces to ofw_bus: - ofw_bus_map_intr() Maps an (iparent, IRQ) tuple to a system-global interrupt number in some platform dependent way. This is meant to be implemented as a replacement for [FDT_]MAP_IRQ() that is an MI interface that knows about the bus hierarchy. - ofw_bus_config_intr() Configures an interrupt (previously mapped) based on firmware sense flags. This replaces manual interpretation of the sense field in bus drivers and will, in a follow-up, allow that interpretation to be redirected to the PIC drivers where it belongs. This will eventually replace the tables in /sys/dev/fdt/fdt_ARCH.c The PowerPC/AIM code has been converted to use these globally, with an implementation in terms of MAP_IRQ() and powerpc_config_intr(), assuming OpenPIC, at the bus root in nexus(4). The ofw_bus_config_intr() will shortly be integrated into pic_if.m and bounced through nexus into the PIC tree. Factor out MI portions of the PowerPC nexus device into /sys/dev/ofw. The sparc64 driver will be modified to use this shortly. Allow PIC drivers to translate firmware sense codes for themselves. This is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not happen quite yet. Do not map IRQs twice. This fixes PowerPC/FDT systems with multiple PICs, which would try to treat the previously-mapped interrupts from fdt_decode_intr() as interrupt line numbers on the same parent PIC. Remove some of the code required for supporting ssm(4) on SPARC in favor of a more PowerPC/FDT-focused design. Whenever SPARC64 is integrated into this rework, this should be (trivially) revisited.
* MFC r256792, r256793, r256799 (by nwhitehorn): Unify AIM and booke code.ian2014-05-131-201/+0
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* MFC r257127:loos2014-01-231-2/+0
| | | | | | | Remove all the instances of '#undef DEBUG' from kernel. Suggested by: rpaulo Approved by: adrian (mentor)
* Align the PCI Express #defines with the style used for the PCI-Xgavin2012-09-181-6/+6
| | | | | | | | | | | | | | | | | #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
* Support lbc interrupts:marcel2012-07-032-34/+108
| | | | | | | | | | | | | | | | | o Save and clear the LTESR register in the interrupt handler. o In lbc_read_reg(), return the saved LTESR register value if applicable (i.e. when the saved value is not invalid (read: ~0U)). o In lbc_write_reg(), clear the bits in the saved register when when it's written to and when the asved value is not invalid. o Also in lbc_write_reg(), the LTESR register is unlocked (in H/W) when bit 1 of LTEATR is cleared. We use this to invalidate our saved LTESR register value. Subsequent reads and write go to H/W directly. While here: o In lbc_read_reg() & lbc_write_reg(), add some belts and suspenders to catch when register offsets are out of range. o In lbc_attach(), initialize completely and don't leave something left for lbc_banks_enable().
* Properly implement the bus_config_intr, bus_setup_intr and bus_teardown_intrmarcel2012-07-021-2/+58
| | | | | | methods so that MI drvers can depend on us doing the right thing instead of having to go around us and call MD code directly. See the FDT code for example (not for long though).
* Import eSDHC driver for Freescale integrated controller.raj2012-05-262-0/+1603
| | | | | Obtained from: Freescale, Semihalf Written by: Michal Dubiel
* Move OpenPIC FDT bus glue to a shared location, so that other PowerPCraj2012-05-261-93/+0
| | | | | | platforms can use it, not only MPC85XX. This is just reorg, no functional changes.
* A few improvements:marcel2012-05-242-64/+179
| | | | | | | | | | | | | | | | | | | | | | | 1. Define all registers. These definitions are needed to support the FCM driver for direct-connect NAND. 2. Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus attached device drivers. Use bus_space functions directly in the lbc driver itself. 3. Be smarter about programming LAWs and mapping memory. The ranges defined in the FDT are per bank (= chip select) and since we can have up to 8 banks, we could easily use more than 8 LAWs or TLB enrties when per-bank memory ranges need multiple LAWs or TLBs due to alignment or size constraints. We now combine all memory ranges into the fewest possible set of contiguous regions and program the hardware for that. Thus, a cleverly written FDT with 8 devices may still only need 1 LAW or 1 TLB entry. Note that the memory ranges can be assigned randomly to the banks. We sort as we build to handle that. 4. Support the FCM when programming the OR register. This is mostly for documention purposes as we do not have a way to define the mode for a bank. 5. Remove Semihalf-ism: do not define DEBUG (only to undefine it again).
* Remove Semihakf-ism. DEBUG is a kernel configuration option. Itmarcel2012-05-241-3/+0
| | | | should not be defined in source files.
* Just return if the size of the window is 0. This can happen when themarcel2012-05-241-1/+7
| | | | | | | FDT does not define all ranges possible for a particular node (e.g. PCI). While here, only update the trgt_mem and trgt_io pointers if there's no error. This avoids that we knowingly write an invalid target (= -1).
* Either the I/O port range or the memory mapped I/O range may not bemarcel2012-05-241-2/+7
| | | | defined in the FDT. The range will have a zero size in that case.
* Fix missing header for powerpc_iomb().nwhitehorn2012-04-231-0/+1
| | | | Pointy hat to: me
* Replace eieio; sync for creating bus-space memory barriers with sync.nwhitehorn2012-04-221-1/+1
| | | | | | | | | | | | sync performs a strict superset of the functions of eieio, so using both is redundant. While here, expand bus barriers to all bus_space operations, since many drivers do not correctly use bus_space_barrier(). In principle, we can also replace sync just with eieio, for a significant performance increase, but it remains to be seen whether any poorly-written drivers currently depend on the side effects of sync to properly function. MFC after: 1 week
* - There's no need to overwrite the default device method with the defaultmarius2011-11-222-4/+2
| | | | | | | | | | one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
* Fix r222813: we need to include sys/cpuset.h. because the PIC interfacemarcel2011-07-311-2/+2
| | | | | | | uses cpuset_t. While here, fix the redundant inclusion of sys/bus.h and order the includes. Approved by: re (blanket)
* MFCattilio2011-05-292-12/+14
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| * o Determine the number of LAWs in a way the is future proof. Only themarcel2011-05-281-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | MPC8555(E) has 8 LAWs, so don't make that the default case. Current processors have 12 LAWs so use that as the default instead. o Determine the target ID of the PCI/PCI-X and PCI-E controllers in a way that's more future proof. There's almost a perfect mapping from HC register offset to target ID, so use that as the default. Handle the MPC8548(E) specially, since it has a non-standard target ID for the PCI-E controller. Don't worry about whether the processor implements the target ID here, because we should not get called for PCI/PCI-X or PCI-E host controllers that don't exist.
| * Remove unused defines. They're distracting...marcel2011-05-281-5/+0
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| * Retire isa_setup_intr() and isa_teardown_intr() and use the generic busjhb2011-05-061-17/+0
| | | | | | | | | | | | versions instead. They were never needed as bus_generic_intr() and bus_teardown_intr() had been changed to pass the original child device up in 42734, but the ISA bus was not converted to new-bus until 45720.
* | Fix compilation.attilio2011-05-181-1/+2
| | | | | | | | Submitted by: andreast
* | MFCattilio2011-05-061-17/+0
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* Rename INTR_VEC to MAP_IRQ. From the OFW or FDT we obtain amarcel2011-02-021-3/+3
| | | | | PIC handle with interrupt pin. This we map to the resource called SYS_RES_IRQ.
* Fix the interrupt code, broken 7 months ago. The interrupt frameworkmarcel2011-01-294-103/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | already supported nested PICs, but was limited to having a nested AT-PIC only. With G5 support the need for nested OpenPIC controllers needed to be added. This was done the wrong way and broke the MPC8555 eval system in the process. OFW, as well as FDT, describe the interrupt routing in terms of a controller and an interrupt pin on it. This needs to be mapped to a flat and global resource: the IRQ. The IRQ is the same as the PCI intline and as such needs to be representable in 8 bits. Secondly, ISA support pretty much dictates that IRQ 0-15 should be reserved for ISA interrupts, because of the internal workins of south bridges. Both were broken. This change reverts revision 209298 for a big part and re-implements it simpler. In particular: o The id() method of the PIC I/F is removed again. It's not needed. o The openpic_attach() function has been changed to take the OFW or FDT phandle of the controller as a second argument. All bus attachments that previously used openpic_attach() as the attach method of the device I/F now implement as bus-specific method and pass the phandle_t to the renamed openpic_attach(). o Change powerpc_register_pic() to take a few more arguments. In particular: - Pass the number of IPIs specificly. The number of IRQs carved out for a PIC is the sum of the number of int. pins and IPIs. - Pass a flag indicating whether the PIC is an AT-PIC or not. This tells the interrupt framework whether to assign IRQ 0-15 or some other range. o Until we implement proper multi-pass bus enumeration, we have to handle the case where we need to map from PIC+pin to IRQ *before* the PIC gets registered. This is done in a similar way as before, but rather than carving out 256 IRQs per PIC, we carve out 128 IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case, but should really be fixed properly using multiple passes. o Have the interrupt framework set root_pic in most cases and not put that burden in PIC drivers (for the most part). o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq(). Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN. Related to the above, fix the Freescale PCI controller driver, broken by the FDT code. Besides not attaching properly, bus numbers were assigned improperly and enumeration was broken in general. This prevented the AT PIC from being discovered and interrupt routing to work properly. Consequently, the ata(4) controller stopped functioning. Fix the driver, and FDT PCI support, enough to get the MPC8555CDS going again. The FDT PCI code needs a whole lot more work. No breakages are expected, but lackiong G5 hardware, it's possible that there are unpleasant side-effects. At least MPC85xx support is back to where it was 7 months ago -- it's amazing how badly support can be broken in just 7 months... Sponsored by: Juniper Networks
* Have nexus behave the same as the one on ARM (marvell SoCs), so as tomarcel2011-01-291-8/+17
| | | | prevent warnings during boot WRT to the fdtbus attachment.
* Restructure how reset and poweroff are handled on PowerPC systems, sincenwhitehorn2010-08-311-25/+0
| | | | | | | | | | | | | | | | | the existing code was very platform specific, and broken for SMP systems trying to reboot from KDB. - Add a new PLATFORM_RESET() method to the platform KOBJ interface, and migrate existing reset functions into platform modules. - Modify the OF_reboot() routine to submit the request by hand to avoid the IPIs involved in the regular openfirmware() routine. This fixes reboot from KDB on SMP machines. - Move non-KDB reset and poweroff functions on the Powermac platform into the relevant power control drivers (cuda, pmu, smu), instead of using them through the Open Firmware backdoor. - Rename platform_chrp to platform_powermac since it has become increasingly Powermac specific. When we gain support for IBM systems, we will grow a new platform_chrp.
* Convert Freescale PowerPC platforms to FDT convention.raj2010-07-1114-1990/+1694
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are affected: - MPC8555CDS - MPC8572DS This overhaul covers the following major changes: - All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI. - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data. Note that world for these platforms has to be built WITH_FDT. Reviewed by: imp Sponsored by: The FreeBSD Foundation
* Move the EOI logic when starting ithreads into intr_machdep instead ofnwhitehorn2010-07-061-2/+0
| | | | | relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
* Remove the unneeded header <machine/intr.h>.marcel2010-07-022-2/+0
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* Assign PCI intline values for ISA interrupts using the new INTR_VEC()marcel2010-06-241-3/+3
| | | | macro.
* Pass the device_t of the AT PIC driver to atpic_intr() so thatmarcel2010-06-241-5/+2
| | | | | we don't have to use a global variable. Pass a NULL frame pointer to the dispatch function just like openpic(4).
* With openpic(4) using active-low as the default polarity, reconfiguremarcel2010-06-231-2/+9
| | | | | | | | | | the internal interrupt sources as active-high. The internal interrupt sources are disabled when programmed as active-low. Note that the internal interrupts have no sense bit like the external interrupts. We program them as edge-triggered to make sure we write a 0 value to a reserved register. It does not in any way say anything about the sense of internal interrupt.
* Configure interrupts on SMP systems to be distributed among all onlinenwhitehorn2010-06-231-0/+1
| | | | | | CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-186-29/+58
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Fix an off-by-one bug for the number of slots on a PCI/PCI-X bus.marcel2010-03-231-7/+8
| | | | | We failed to setup PCI devices on slot 31 and that's where the SATA controller is for the P2020 eval board.
* Add definitions for a 4th PCI host controller. No Freescale processormarcel2010-03-232-1/+16
| | | | | | has all 4 implemented, but across the processors we now support all the combinations. For example, the MPC8533 doesn't have a PCI controller at 0xA0000, but does at 0xB0000.
* Make PCI Express host controllers functional, by:marcel2010-02-011-0/+26
| | | | | | | | 1. checking whether there's a link before initializing devices on the bus. When there's no link any access onto the bus will wedge the CPU. 2. synthesizing the class & subclass so that the host controller appears as a standard PCI bridge, rather than a PowerPC CPU.
* Use the capability pointer to indicate whether the host controller ismarcel2010-02-011-12/+13
| | | | | | PCI Express, rather than a bit-field (boolean). Saving the capability pointer this way makes access to capability-specific configuration registers easy and efficient.
* Don't check the device ID. Instead, check the class, subclass andmarcel2010-01-291-28/+13
| | | | | | | | | | | | | programming I/F. New SoC designs have different device IDs, but don't need special treatment. Consequently, we fail to probe and attach for no other reason than not having added the device ID to the code. Bank on Freescale's sense of backward compatibility and assume that if we find a host controller, we know how work with it. This fixes detection of the PCI Express host controllers on Freescale's QorIQ family of processors (P1, P2 and P4).
* Always allocate PCI/ISA interrupts as shareable so that sharedmarcel2009-11-201-0/+1
| | | | interrupts don't cause driver attach failures.
* Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX.raj2009-07-211-4/+4
| | | | | | | | | | | | | | It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized. Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf
* More precise description of the DS1553 driver.raj2009-06-241-1/+1
| | | | Pointed out by: stas
* DS1553 RTC module driver. On the MPC8555CDS system it hangs off of the LBC bus.raj2009-06-223-0/+435
| | | | Obtained from: Semihalf
* Integrated I2C controller driver (found in MPC85xx and other SOC parts).raj2009-06-221-0/+440
| | | | Obtained from: Freescale, Semihalf
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