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* Only manipulate the PGA_EXECUTABLE flag on managed pages. This is a proxynwhitehorn2012-04-111-14/+10
* Fix error in r233949. Synchronizing icaches on uncacheable pages turns outnwhitehorn2012-04-111-2/+4
* Execute an initial ptesync if and only if the PTE is actually beingnwhitehorn2012-04-061-14/+7
* Substantially reduce the scope of the locks held in pmap_enter(), whichnwhitehorn2012-04-061-34/+8
* Reduce the frequency that the PowerPC/AIM pmaps invalidate instructionnwhitehorn2012-04-063-57/+29
* More PMAP performance improvements: skip 256 MB segments entirely if theynwhitehorn2012-03-282-11/+26
* Make sure to call vm_page_dirty() before the pmap lock is released tonwhitehorn2012-03-271-2/+2
* More PMAP concurrency improvements: replace the table lock and (almost) allnwhitehorn2012-03-271-86/+100
* More PMAP performance improvements: on powerpc64, when TLBIE can be runnwhitehorn2012-03-251-4/+11
* Only call vm_page_dirty() on pages that are writable in order not tonwhitehorn2012-03-241-4/+12
* Following suggestions from alc, skip wired mappings in pmap_remove_pages()nwhitehorn2012-03-241-51/+29
* Remove acquisition of VM page queues lock from pmap_protect(). Any actualnwhitehorn2012-03-181-2/+0
* Implement pmap_remove_pages(). This will be added later to the 32-bit MMUnwhitehorn2012-03-151-0/+18
* Improve algorithm for deciding whether to loop through all process pagesnwhitehorn2012-03-151-40/+58
* Use LIST_FOREACH_SAFE() instead of LIST_FOREACH() in pmap_remove(), sincenwhitehorn2012-03-142-4/+4
* Revert the _NOPROF entries on cpu_throw, cpu_switch and savectx. They can beandreast2012-02-051-3/+3
* Fix build for the case of powerpc64 kernel without COMPAT_FREEBSD32.kib2012-01-301-0/+3
* Finally, try to enable the nxstacks on amd64 and powerpc64 for both 64bitkib2012-01-301-0/+4
* This commit adds profiling support for powerpc64. Now we can do applicationandreast2012-01-203-7/+8
* Rework SLB trap handling so that double-faults into an SLB trap handler arenwhitehorn2012-01-154-57/+229
* Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).jhibbits2011-12-242-0/+16
* Allow this to work on embedded systems without Open Firmware by makingnwhitehorn2011-12-161-35/+67
* Zero BSS on start, in case the ELF loader that started the kernel did notnwhitehorn2011-12-161-0/+11
* Eliminate vestiges of page coloring.alc2011-12-152-4/+2
* Keep track of PVO entries in each pmap, which allows much fasternwhitehorn2011-12-112-9/+41
* - There's no need to overwrite the default device method with the defaultmarius2011-11-221-4/+4
* Use a global __pure2 function instead of a global register variable fornwhitehorn2011-11-172-2/+12
* Add an extra invariant here which was useful on 64-bit CPUs.nwhitehorn2011-11-171-0/+2
* Refactor the code that performs physically contiguous memory allocation,alc2011-11-161-7/+9
* Fix a bug where the pmap_cpu_bootstrap() ap argument could be clobbered.nwhitehorn2011-11-092-2/+4
* Inline the syscallenter() and syscallret(). This reduces the time measuredkib2011-09-111-0/+2
* Split the vm_page flags PG_WRITEABLE and PG_REFERENCED into atomickib2011-09-062-26/+26
* - Move the PG_UNMANAGED flag from m->flags to m->oflags, renaming the flagkib2011-08-092-39/+29
* This a follow up commit from r224216 for powerpc 32-bit. Increaseandreast2011-07-251-2/+2
* On 64 bit architectures size_t is 8 bytes, thus it should use an 8 bytesattilio2011-07-191-2/+2
* - Remove the eintrcnt/eintrnames usage and introduce the concept ofattilio2011-07-182-4/+10
* With retirement of cpumask_t and usage of cpuset_t for representing aattilio2011-07-042-12/+4
* Revert r223479. It is unnecessary and served only to slightly amelioratenwhitehorn2011-06-262-4/+0
* Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)nwhitehorn2011-06-2310-49/+54
* Clear any outstanding atomic reservations when traps are taken. This fixesnwhitehorn2011-06-232-0/+4
* Fix merge typo.andreast2011-06-231-1/+1
* MFCattilio2011-06-041-2/+2
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| * Fix a typo derived from a mismerge from mmu_oea that would causenwhitehorn2011-06-041-2/+2
* | MFCattilio2011-06-0311-309/+68
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| * Quantities stored on the stack on ppc64 tend to be twice as large as onnwhitehorn2011-06-031-1/+1
| * The POWER7 has only 32 SLB slots instead of 64, like other supportednwhitehorn2011-06-023-43/+51
| * If running under a hypervisor, don't yell at the user about startingnwhitehorn2011-06-021-1/+4
| * Explicitly initialize the first thread's MSR to PSL_KERNSET.nwhitehorn2011-06-021-1/+1
| * Include the modules area in the mapped kernel code. This fixes the kernel'snwhitehorn2011-06-021-3/+2
| * Remove some dead code: unnecessary isyncs and memory sorting, which arenwhitehorn2011-06-024-47/+9
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