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* When user_frac in the polling subsystem is low it is going to busy theattilio2009-05-301-10/+17
| | | | | | | | | | | | | | | | | | | | | CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
* For RTL8139C+ controllers, have controller handle padding shortyongari2009-04-201-0/+1
| | | | | | | | | | | | | checksum offload frames. Software workaround used for broken controllers(RTL8169, RTL8168, RTL8168B) seem to cause watchdog timeouts on RTL8139C+. Introduce a new flag RL_FLAG_AUTOPAD to mark automatic padding feature of controller and set it for RTL8139C+ and controllers that use new descriptor format. This fixes watchdog timeouts seen on RTL8139C+. Reported by: Dimitri Rodis < DimitriR <> integritasystems dot com > Tested by: Dimitri Rodis < DimitriR <> integritasystems dot com >
* intpm: minor enhancementsavg2009-03-161-8/+8
| | | | | | | | | | | 1. fix nointr check in intsmb_start, matters only if ENABLE_ALART is defined (by default, it is not); 2. drop unnecessary inspection/reporting of power-management io registers base address; 3. in verbose mode report errors from SMBus host controller and their mapping to smbus(4) errors; Approved by: jhb (mentor)
* The callback takes a void *, not a caddr_t * (sic).imp2009-03-031-2/+2
| | | | Except for the bb callback, which takes a caddr_t and not a caddr_t *.
* Allocating 2 MSI messages do not seem to work on certain controllersyongari2009-02-111-1/+1
| | | | | | | so use just 1 MSI message. This fixes regression introduced in r188381. Tested by: many
* Destroy TX tag outside of loop scope.fjoe2009-02-091-1/+1
| | | | | Found with: Coverity Prevent(tm) CID: 3886
* - Add support for 8110SCe part. Some magic registers were taken fromjkim2009-01-201-4/+4
| | | | | | | Linux driver. - Swap hardware revisions for 8110S and 8169S as Linux driver claims. Reviewed by: yongari (early version)
* Retire RL_FLAG_INVMAR bit to match its comment and reality.jkim2009-01-201-1/+0
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* Sometimes RTL8168B seems to take long time to access GMII registersyongari2009-01-191-0/+1
| | | | | | | | in device attach phase. Double GMII register access timeout value to fix the issue. Reported by: wkoszek Tested by: wkoszek
* Since we don't request reset for rlphy(4), the link state 'UP'yongari2008-12-221-0/+2
| | | | | | | | | event from mii(4) may not be delivered if valid link was already established. To address the issue, check current link state after driving MII_TICK. This should fix a regression introduced in r184245. PR: kern/129647
* It seems that RealTek PCIe controllers require an explicit Tx pollyongari2008-12-171-0/+1
| | | | | | | | | | | | | | | | | | | command whenever Tx completion interrupt is raised. The Tx poll bit is cleared when all packets waiting to be transferred have been processed. This means the second Tx poll command can be silently ignored as the Tx poll bit could be still active while processing of previous Tx poll command is in progress. To address the issue re(4) used to invoke the Tx poll command in Tx completion handler whenever it detects there are pending packets in TxQ. However that still does not seem to completely eliminate watchdog timeouts seen on RealTek PCIe controllers. To fix the issue kick Tx poll command only after Tx completion interrupt is raised as this would indicate Tx is now idle state such that it can accept new Tx poll command again. While here apply this workaround for PCIe based controllers as other controllers does not seem to have this limitation. Tested by: Victor Balada Diaz < victor <> bsdes DOT net >
* For RTL8168C SPIN2 controllers, make sure to take the controlleryongari2008-12-171-0/+3
| | | | | | | | out of sleep mode prior to accessing to PHY. This should fix device attach failure seen on these controllers. Also enable the sleep mode when device is put into sleep state. PR: kern/123123, kern/123053
* By default assume a 8139 chip if the EEPROM contents prove inconclusive. Thewilko2008-12-151-3/+9
| | | | | | | | | | | same LOM hardware with goofed-up EEPROM programming also needed reading the Ethernet address from the chips registers as the EEPROM did not have a sensible address programmed. Patch developed by: pyun@ Funky hardware on loan: www.id-it.nl MFC after: 2 weeks
* Make WOL work on RTL8168B. This controller seems to requireyongari2008-12-111-0/+1
| | | | | | explicit command to enable Rx MAC prior to entering D3. Tested by: Cyrus Rahman <crahman <> gmail DOT com>
* Don't access undocumented register 0x82 on controllers thatyongari2008-12-111-0/+2
| | | | | | | have no such register. While here clear undocumented PHY register 0x0B for RTL8110S. Obtained from: RealTek FreeBSD driver
* Newer RealTek controllers requires setting stop request bit toyongari2008-12-111-0/+2
| | | | terminate active Tx/Rx operation.
* o Implemented miibus_statchg handler. It detects whether re(4)yongari2008-12-081-0/+1
| | | | | | | | | | | | | | | | established a valid link or not. In miibus_statchg handler add a check for established link is valid one for the controller(e.g. 1000baseT is not a valid link for fastethernet controllers.) o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers. o Added additional check to know whether we've really encountered watchdog timeouts or missed Tx completion interrupts. This change may help to track down the cause of watchdog timeouts. o In interrupt handler, removed a check for link state change interrupt. Not all controllers have the bit and re(4) did not rely on the event for a long time. In addition, re(4) didn't request the interrupt in RL_IMR register. Tested by: rpaulo
* Update if_iqdrops instead of if_ierrors when m_devget(9) fails.yongari2008-12-031-7/+4
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* Add 8168D support.yongari2008-12-021-0/+1
| | | | Submitted by: Andrew < andrewwtulloch <> gmail DOT com >
* Move mn over. One of the last stragglers in sys/pci. There's noimp2008-11-021-1450/+0
| | | | module built for this hardware, so no changes needed.
* Make RL_TWISTER_ENABLE a tunable/sysctl. Eliminate it as an option.imp2008-11-022-26/+33
| | | | | | Fix module build. Submitted by: Kostik Belousov
* Fix a few typos/spelling errors in my comments from the last commit,imp2008-11-011-7/+7
| | | | | | plus a few others that had lingered in this driver... Submitted by: "b." bf2006a att yahoo KIBO com
* Add RL_TWISTER_ENABLE option. This enables the magic bits to do longimp2008-10-312-2/+165
| | | | | | | | | cable tuning. This has helped in some installations for hardware deployed by a former employer. Made optional because the lists aren't full of complaints about these cards... even when they were wildly popular. Reviewed by: attilio@, jhb@, trhodes@ (all an older version of the patch)
* Implement miibus_statchg handler. It detects whether rl(4)yongari2008-10-251-0/+34
| | | | | | | | established a valid link or not. In rl_start_locked, don't try to send packets unless we have valid link. While I'm here add a check that verifies whether driver can accept Tx requests by inspecting IFF_DRV_OACTIVE/IFF_DRV_RUNNING flag.
* After sending stop command to MAC, give hardware chance to drainyongari2008-10-251-0/+8
| | | | active DMA operation.
* Make rl_init_locked() call rl_reset. This will put hardware intoyongari2008-10-251-7/+4
| | | | sane state after resume/watchdog timeouts.
* Don't rearm watchdog timer in rl_txeof(). The watchdog timer wasyongari2008-10-251-2/+0
| | | | | already set in rl_start_locked(). Touching the watchdog timer in other places will hide the root cause of watchdog timeouts.
* Various bus_dma(9) fixes.yongari2008-10-252-120/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The hardware does not support DAC so limit DMA address space to 4GB. - Removed BUS_DMA_ALLOC_NOW flag. - Created separated Tx buffer and Rx buffer DMA tags. Previously it used to single DMA tag and it was not possible to specify different DMA restrictions. - Apply 4 bytes alignment limitation of Tx buffer. - Apply 8 bytes alignment limitation of Rx buffer. - Tx side bus_dmamap_load_mbuf_sg(9) support. - Preallocate Tx DMA maps as creating DMA maps take very long time on architectures that require real DMA maps. - Adjust guard buffer size to 1522 + 8 as it should include VLAN and additional reserved bytes in Rx buffer. - Plug memory leak in device detach. Previously wrong buffer address was used to free allocated memory. - Added rl_list_rx_init() to clear Rx buffer and cleared the buffer. - Don't destroy DMA maps in rl_txeof() as the DMA map should be reused. There is no reason to destroy/recreate the DMA maps in this driver. - Removed rl_dma_map_rxbuf()/rl_dma_map_txbuf() callbacks. - The hardware does not support descriptor based DMA on Tx side and the Tx buffer address should be aligned on 4 bytes boundary as well as manual padding for short frames. Because of this hardware limitation rl(4) always used to invoke m_defrag(9) to get a 4 bytes aligned single buffer. However m_defrag(9) takes a lot of CPU cycles on slow machines and not all packets need the help of m_defrag(9). Armed with the information, don't invoke m_defrag(9) if the following conditions are true. 1. Buffer is not fragmented. 2. Buffer is aligned on 4 bytes boundary. 3. Manual padding is not necessary. 4. Or padding is necessary but upper stack passed a writable buffer and the space needed for padding is satisfied. This change combined with preallocated DMA maps greatly increased Tx performance of driver on sparc64. - Moved bus_dmamap_sync(9) in rl_start_locked() to rl_encap() and corrected memory synchronization operation specifier of bus_dmamap_sync(9). - Removed bus_dmamap_unload(9) in rl_stop(). There is no need to reload/unload Rx buffer as rl(4) always have to copy from the buffer. It just needs proper bus_dmamap_sync(9) calls before copying the received frame. With this change rl(4) should work on systems with more than 4GB memory. PR: kern/128143
* Move wb driver from sys/pci to sys/dev/wb.imp2008-08-142-2312/+0
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* Move pcn driver from sys/pci to sys/dev/pcn.imp2008-08-142-2057/+0
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* Move the ste driver from sys/pci to sys/dev/ste.imp2008-08-142-2302/+0
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* Move the tl driver form sys/pci to sys/dev/tl.imp2008-08-142-2955/+0
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* Move sis to sys/dev/sis for consistency.imp2008-08-102-2802/+0
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* Move the xl driver form sys/pci to sys/dev/xl for consistency.imp2008-08-102-4112/+0
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* Add locking to the various iicbus(4) bridge drivers:jhb2008-08-041-0/+1
| | | | | | | | | | | | | | | | | | | | | - Just grab Giant in the ixp425_iic(4) driver since this driver uses a shared address/data register window pair to access the actual I2C registers. None of the other ixp425 drivers lock access to these shared address/data registers yet and that would need to be done before this could use any meaningful locking. - Add locking to the interrupt handler and 'iicbus_reset' methods of the at91_twi(4) driver. - Add locking to the pcf(4) driver. Other pcf(4) fixes include: - Don't needlessly zero the softc. - Use bus_foo rather than bus_space_foo and remove bus space tag and handle from softc. - The lpbb(4) driver just grabs Giant for now. This will be refined later when ppbus(4) is locked. - As was done with smbus earlier, move the DRIVER_MODULE() lines to match the bus driver (either iicbus or iicbb) to the bridge driver into the bridge drivers. Tested by: sam (arm/ixp425)
* The number of bits reserved for MSS in RealTek controllers isyongari2008-08-041-0/+8
| | | | | | | 11bits. This limits the maximum interface MTU size in TSO case as upper stack should not generate TCP segments with MSS greater than the limit. Armed with this information, disable TSO if interface MTU is greater than the limit.
* Set all of the "optimum performance" PHY registers for the 15D parts asjhb2008-07-301-10/+8
| | | | | | | | | well as the 15C since it seems to be required in practice. The Linux natsemi.c driver mostly does this as well. PR: kern/112179 Submitted by: Mark Willson mark - hydrus org uk MFC after: 1 week
* SIS_SETBIT() already does a read/modify/write operation, so there isn'tjhb2008-07-301-2/+1
| | | | | | a reason to read the register twice. MFC after: 1 week
* Add driver support for RTL8102E and RTL8102EL which is the secondyongari2008-07-091-0/+2
| | | | | | | | | generation of RTL810x PCIe fast ethernet controller. Note, Tx/Rx descriptor format is different from that of first generation of RTL8101E series. Jumbo frame is not supported for RTL810x family. Tested by: NAGATA Shinya ( maya AT negeta DOT com )
* Add a new RTL8169 variant, 8169SB(L)/8110SB(L).yongari2008-07-021-0/+1
| | | | | Reported by: nork Tested by: nork
* Add basic support for RTL8168C, RTL8168CP, RTL8111C and RTL8111CP.yongari2008-07-021-0/+24
| | | | | | | | | | | | | | | | ATM Tx/Rx checksum offload is supported but TSO and jumbo frame is not yet supported. Because these newer controllers use different descriptor formats, a flag RL_FLAG_DESCV2 flag was introduced to handle that case in Tx/Rx handler. Also newer controllers seems to require to not touch 'enable Tx/Rx bit' in RL_CPLUS_CMD register so don't blindly try to set that bits. Note, it seems that there is still power-saving related issue where driver fails to attach PHY. Rebooting seems to fix that issue but number of required reboots varys. Many thanks to users that helped during developement. I really appreciate their patient and test/feedbacks.
* Instead of allocating variables for each events/hardware flags, useyongari2008-07-021-2/+6
| | | | | | | | | a dedicated flag that represents controller capabilities/events. This will simplify many part of code that requires different workaround for each controller revisions and will enhance readability. While I'm here move PHY wakeup code up before mii_phy_probe() which seems to help to wake PHY in some cases.
* Switch to memory space register mapping over IO space. If thatyongari2008-07-021-0/+2
| | | | mapping fails fall back to traditional IO space access.
* Add support for VT8237 ISA bridge.gonzo2008-06-221-0/+7
| | | | | PR: kern/120714 Event: Bugathon#5
* Add the SMB functionality for the MCP65 chipset I happen tojoerg2008-06-181-0/+3
| | | | have in my new motherboard.
* Add another 8139D variant.remko2008-06-162-0/+3
| | | | | | | PR: 124622 Submitted by: Evgeny Zhirnov <jirnov at gmail dot com> Approved by: imp (mentor, implicit) MFC after: 3 days
* - Use bus_foo() rather than bus_space_foo() and remove bus space tag/handlejhb2008-06-065-33/+13
| | | | | | from softc. - Mark interrupt handlers MPSAFE as these drivers have been locked for a while.
* Remove unused 'xl_unit' member from softc.jhb2008-05-282-2/+0
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* - Set sc->dev to the new-bus device_t so all the device_printf()s work.jhb2008-05-121-1/+3
| | | | | | | - Add a missing newline to a printf. MFC after: 1 week Submitted by: Andriy Gapon avg <> icyb.net.ua
* It seems that RealTek 8129/8139 chip reports invalid length ofyongari2008-04-101-3/+5
| | | | | | | | | | | | | | | | received frame under certain conditions. wpaul said the length 0xfff0 is special meaning that indicates hardware is in the process of copying a packet into host memory. But it seems there are other cases that hardware is busy or stuck in bad situation even if the received frame length is not 0xfff0. To work-around this condition, add a check that verifys that recevied frame length is in valid range. If received length is out of range reinitialize hardware to recover from stuck condition. Reported by: Mike Tancsa ( mike AT sentex DOT net ) Tested by: Mike Tancsa Obtained from: OpenBSD MFC after: 1 week
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