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* Fix Sibyte SMP kernel breakage caused by r208249.neel2010-05-181-0/+2
* Adds JC's cleanup patches that fix it sorrs2010-05-181-0/+14
* o) Remove default MAXMEM on SWARM; pmap can readily use lmem for >512Mjmallett2010-04-231-0/+11
* Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.neel2010-03-262-52/+9
* Sibyte provides a 64-bit read-only counter that counts at half the processorneel2010-03-203-0/+40
* Make sure that the registers 'v0' and 'v1' are properly sign-extendedneel2010-03-201-4/+4
* Add support for CPUs with cache coherent DMA. The two main changes are:neel2010-03-041-0/+7
* Various fixes to get the SWARM config working on a big-endian Sibyte CPU.neel2010-02-173-8/+197
* Remove the PCI_IOSPACE_SIZE and PCI_IOSPACE_ADDR hack from nexus.c. Implementneel2010-02-121-6/+126
* SMP support for the mips port.neel2010-02-095-7/+212
* Initialize interrupt controller early on.neel2010-02-051-0/+18
* Reimplement all functions to access the system control unit in C.neel2010-02-054-126/+145
* style: don't need to use braces for single line control statements.neel2010-02-051-10/+5
* Install the XTLB exception handler for Sibyte processors.neel2010-01-261-0/+24
* - Call post-boot fixup function in order to get proper staticgonzo2010-01-251-4/+2
* Remove Sibyte specific code from locore.S that sets the k0seg coherency.neel2010-01-231-0/+17
* Remove redundant interrupt mapper code. We don't need to disable theimp2010-01-111-113/+8
* Get sb_zbpci.c compiling again after the macros PCI_BUSMAX,imp2010-01-111-0/+1
* Rename mips_pcpu_init to mips_pcpu0_init since it applies only to theimp2010-01-091-1/+1
* Centralize initialization of pcpu, and set curthread early...imp2010-01-081-0/+3
* Remove all CFE-specific code from locore.S. The CFE entrypoint initializationneel2010-01-061-13/+9
* With this commit our friend RMI will now compile. I haverrs2009-10-302-0/+7
* Does 4 things:rrs2009-10-151-1/+1
* Add sibyte device support.imp2009-07-048-0/+1575
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