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* Sibyte provides a 64-bit read-only counter that counts at half the processorneel2010-03-201-0/+1
| | | | | | | | | frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync.
* SMP support for the mips port.neel2010-02-091-0/+6
| | | | | | | The platform that supports SMP currently is a SWARM with a dual-core Sibyte processor. The kernel config file to use is SWARM_SMP. Reviewed by: imp, rrs
* Reimplement all functions to access the system control unit in C.neel2010-02-051-9/+8
| | | | | | | | | The only reason we need to have the sb_load64() and sb_store64() functions in assembly is to cheat the compiler and generate the 'ld' and 'sd' instructions which it otherwise will not do when compiling for a 32-bit architecture. There are some 64-bit registers in the SCD unit that must be accessed using 64-bit load and store instructions.
* Add sibyte device support.imp2009-07-041-0/+46
Submitted by: Neelkanth Natu
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