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| author | neel <neel@FreeBSD.org> | 2010-03-20 05:49:06 +0000 |
|---|---|---|
| committer | neel <neel@FreeBSD.org> | 2010-03-20 05:49:06 +0000 |
| commit | e17e52b7e2dffab4f1200b2f010c3ef8cb1132d7 (patch) | |
| tree | cacc3b5710d157a71c058bde1ec018801c05c21d /sys/mips/sibyte/sb_scd.h | |
| parent | acca987bde60a7b3b11dabcb24b9870f71e22546 (diff) | |
| download | FreeBSD-src-e17e52b7e2dffab4f1200b2f010c3ef8cb1132d7.zip FreeBSD-src-e17e52b7e2dffab4f1200b2f010c3ef8cb1132d7.tar.gz | |
Sibyte provides a 64-bit read-only counter that counts at half the processor
frequency. This counter can be accessed coherently from both cores.
Use this as the preferred timecounter for the SWARM kernels.
The CP0 COUNT register is unusable as the timecounter on SMP platforms because
the COUNT registers on different CPUs are not guaranteed to be in sync.
Diffstat (limited to 'sys/mips/sibyte/sb_scd.h')
| -rw-r--r-- | sys/mips/sibyte/sb_scd.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/mips/sibyte/sb_scd.h b/sys/mips/sibyte/sb_scd.h index 03d2681..f8bb6e4 100644 --- a/sys/mips/sibyte/sb_scd.h +++ b/sys/mips/sibyte/sb_scd.h @@ -31,6 +31,7 @@ #define NUM_INTSRC 64 /* total number of interrupt sources */ +uint64_t sb_zbbus_cycle_count(void); uint64_t sb_cpu_speed(void); void sb_system_reset(void); |
