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* MFC efivar(8) (by imp):kib2017-05-201-0/+14
* MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,mjg2017-03-161-2/+101
* MFC r313194:kib2017-02-111-2/+0
* MFC r304459,r305527:mmel2016-11-051-0/+2
* Garbage collect unused prototype for clockintr().rwatson2016-05-201-2/+0
* When attempting to satisfy mmap() requests for superpage alignment onrwatson2016-04-301-0/+2
* Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machineandrew2016-04-152-3/+3
* Make NIRQ configurable for MIPSsgalabov2016-04-151-2/+6
* Define PCI_RES_BUS for MIPS.sgalabov2016-04-121-0/+3
* POSIX states that #include <signal.h> shall make both mcontext_t andkib2016-02-121-5/+5
* Missing commit - remove MIPS fdt bus space.adrian2016-02-111-1/+0
* Remove bus space fdt for MIPS.adrian2016-02-111-1/+1
* Begin the MIPS_INTRNG support.adrian2016-02-112-0/+72
* Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction foradrian2016-02-021-5/+27
* Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx optionsadrian2016-02-023-5/+5
* Shift saved floating point registers up in jmp_buf.brooks2016-01-201-14/+15
* Begin the initial support for the mips1004kc core.adrian2015-12-242-2/+14
* [mips] Add TLB pagemask probing code, and print out the allowable page sizes.adrian2015-12-222-0/+14
* Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.hian2015-12-201-3/+0
* Introduce a new mechanism for relocating virtual pages to a new physicalalc2015-12-191-1/+0
* Correct the CONFIG0_VI value. According toimp2015-12-111-1/+1
* mips74k: use cache-writeback for memory, not writethrough.adrian2015-10-311-1/+1
* Switch from a stub to a real implementation of pmap_page_set_attr() for mips,ian2015-10-211-1/+2
* Rationalize BSD license on sys/*/include/in_cksum.hemaste2015-08-051-1/+1
* Rationalize BSD license on sys/*/include/float.hemaste2015-08-051-1/+1
* Add the atomic_thread_fence() family of functions with intent tokib2015-07-081-0/+28
* Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.alc2015-06-081-3/+2
* Similarly to other architecture, add the include for cpufunc.h which isbz2015-05-281-0/+1
* Increment the vm stats "v_intr" counter so the global system interruptadrian2015-05-161-0/+1
* Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h>jhb2015-04-081-1/+3
* Add 64 byte linesize cache flushing routines for L1 instruction, L1 databr2015-03-262-11/+75
* Add 128-byte cache flushing routines.br2015-01-201-2/+0
* Factor out duplicated code from dumpsys() on each architecture into genericmarkj2015-01-072-0/+77
* Update ELF headers to include additional definesemaste2015-01-021-29/+0
* The physical memory allocator supports the use of distinct free lists foralc2014-12-311-11/+9
* Correct the functions declaration.br2014-11-231-8/+8
* Add FPU support for MIPS setjmp(3)/longjmp(3).brooks2014-11-211-0/+14
* Add L2-cache writeback/flush operations. Supported 32,128-byte line-size,br2014-11-203-0/+23
* Add fueword(9) and casueword(9) functions. They are like fuword(9)kib2014-10-281-0/+4
* Pass up the error status of minidumpsys() to its callers.markj2014-10-081-1/+1
* style(9)glebius2014-09-071-4/+3
* Implement local sfbuf_map and sfbuf_unmap for MIPS32.adrian2014-09-062-0/+20
* Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.cglebius2014-08-052-51/+7
* Add missing definition of ELF_MACHINE_OK, now used by gcore(1).marcel2014-07-261-0/+2
* Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4tijl2014-04-011-1/+1
* Update NetBSD Foundation copyrights to 2-clause BSDemaste2014-03-181-7/+0
* Update MIPS bootinfo.h to reflect the actual MIPS boot2/loader boot-timerwatson2014-02-191-87/+30
* Retire machine/fdt.h as a header used by MI code, as its function is nownwhitehorn2014-01-051-11/+0
* As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In otheralc2013-11-081-9/+10
* MFP4:brooks2013-10-231-9/+23
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