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* Add acpi_find_table() -- a convenience function for looking up anmarcel2010-07-071-0/+1
| | | | ACPI table given the signature.
* Bump MAX_BPAGES from 256 to 1024. It seems that a few drivers, bge(4)marcel2010-06-111-0/+1
| | | | | | | | | | | | | | | in particular, do not handle deferred DMA map load operations at all. Any error, and especially EINPROGRESS, is treated as a hard error and typically abort the current operation. The fact that the busdma code queues the load operation for when resources (i.e. bounce buffers in this particular case) are available makes this especially problematic. Bounce buffering, unlike what the PR synopsis would suggest, works fine. While on the subject, properly implement swi_vm(). PR: 147502 MFC after: 1 week
* Some code churn:marcel2010-02-141-8/+8
| | | | | | | | | | | | | | | | | | | | | o Eliminate IA64_PHYS_TO_RR6 and change all places where the macro is used by calling either bus_space_map() or pmap_mapdev(). o Implement bus_space_map() in terms of pmap_mapdev() and implement bus_space_unmap() in terms of pmap_unmapdev(). o Have ia64_pib hold the uncached virtual address of the processor interrupt block throughout the kernel's life and access the elements of the PIB through this structure pointer. This is a non-functional change with the exception of using ia64_ld1() and ia64_st8() to write to the PIB. We were still using assignments, for which the compiler generates semaphore reads -- which cause undefined behaviour for uncacheable memory. Note also that the memory barriers in ipi_send() are critical for proper functioning. With all the mapping of uncached memory done by pmap_mapdev(), we can keep track of the translations and wire them in the CPU. This then eliminates the need to reserve a whole region for uncached I/O and it eliminates translation traps for device I/O accesses.
* Export the bus, cpu and itc frequencies under the hw.freq sysctl node.marcel2009-12-231-0/+1
| | | | | | | | | | | | The frequencies are in MHz (i.e. a value of 1000 represents 1GHz). The frequencies are rounded to the nearest whole MHz. While here, rename and re-type bus_frequency, processor_frequency and itc_frequency to bus_freq, cpu_freq and itc_freq and make them static. As unsigned integers, the hw.freq.cpu sysctl can more easily be made generic (across all architectures) making porting easier. MFC after: 3 days
* Reimplement the lazy FP context switching:marcel2009-10-311-0/+2
| | | | | | | | | | | | | | | | | | | o Move all code into a single file for easier maintenance. o Use a single global lock to avoid having to handle either multiple locks or race conditions. o Make sure to disable the high FP registers after saving or dropping them. o use msleep() to wait for the other CPU to save the high FP registers. This change fixes the high FP inconsistency panics. A single global lock typically serializes too much, which may be noticable when a lot of threads use the high FP registers, but in that case it's probably better to switch the high FP context synchronuously. Put differently: cpu_switch() should switch the high FP registers if the incoming and outgoing threads both use the high FP registers.
* Rename ia64_invalidate_icache() to ia64_sync_icache(). We'remarcel2009-05-181-1/+1
| | | | not invalidating anything.
* Better implement I-cache invalidation. The previous implementationmarcel2008-03-301-0/+1
| | | | | | | | | was a kluge. This implementation matches the behaviour on powerpc and sparc64. While on the subject, make sure to invalidate the I-cache after loading a kernel module. MFC after: 2 weeks
* Allocate a stack for thread0 and switch to it before callingmarcel2008-02-041-1/+6
| | | | | mi_startup(). This frees up kstack for static PAL/SAL calls and double-fault handling.
* Keep interrupts disabled while handling external interrupts.marcel2007-08-061-1/+1
| | | | | | | | | | | | There's no advantage in allowing nested external interrupts. In fact, it leads to a potential stack overrun. While here, put the interrupt vector in the trapframe, so as to compensate for the 36 cycle latency of reading cr.ivr. Further simplify assembly code by dealing with ASTs from C. Approved by: re (blanket)
* Rework the interrupt code and add support for interrupt filteringmarcel2007-07-301-1/+1
| | | | | | | | | | | | | | | | | | | | (INTR_FILTER). This includes: o Save a pointer to the sapic structure and IRQ for every vector, so that we can quickly EOI, mask and unmask the interrupt. o Add locking to the sapic code now that we can reprogram a sapic on multiple CPUs at the same time. o Use u_int for the vector and IRQ. We only have 256 vectors, so using a 64-bit type for it is rather excessive. o Properly handle concurrent registration of a handler for the same vector. Since vectors have a corresponding priority, we should not map IRQs to vectors in a linear fashion, but rather pick a vector that has a priority in line with the interrupt type. This is left for later. The vector/IRQ interchange has been untangled as much as possible to make this easier. Approved by: re (blacket)
* Explicitly map the VHPT on all processors. Previously we weremarcel2007-07-301-0/+1
| | | | | | | | merely lucky that the VHPT was mapped as a side-effect of mapping the kernel, but when there's enough physical memory, this may not at all be the case. Approved by: re (blanket)
* Partial support for branch long emulation. This only emulates themarcel2006-06-291-0/+1
| | | | | branch long jump and not the branch long call. Support for that is forthcoming.
* Enhance ia64_flush_dirty() to handle the case in which td != curthread.marcel2005-07-051-1/+1
| | | | | | | | This case is triggered with ptrace(2) and the PT_SETREGS function. Change the return type of the function to int so that errors can be passed on to the caller. Approved by: re (scottl)
* Further enhance the handling of misaligned loads and stores:marcel2005-01-021-1/+0
| | | | | | | | | | | | | | | | | | | | o implement double-extended and single precision loads and stores, o implement double precision stores, o replace the machdep.unaligned_print sysctl with debug.unaligned_print and change the default value to 0, o replace the machdep.unaligned_sigbus sysctl with debug.unaligned_test, o Remmove the fillfd() function. The function is trvial enough for inline assembly. The debug.unaligned_test sysctl is used to test the emulation of misaligned loads and stores. When PSR.ac is 0, the CPU will handle misaligned memory accesses itselfi and we don't get an exception for it. When PSR.ac is 1, the process needs to be signalled and we should not emulate. The sysctl takes effect when PSR.ac is 1 and tells us that we should emulate and not send a signal. PR: 72268 MFC after: 1 week
* Don't obtain the HCDP address directly from the bootinfo structure.marcel2004-12-081-0/+1
| | | | Use a function to keep the details at arms length from uart(4).
* Move the IA-32 trap handling from trap() to ia32_trap(). Move themarcel2004-09-251-0/+2
| | | | | ia32_syscall() function along with it to ia32_trap.c. When COMPAT_IA32 is not defined, we'll raise SIGEMT instead.
* Add __elfN(dump_thread). This function is called from __elfN(coredump)marcel2004-08-111-0/+2
| | | | | | | | | to allow dumping per-thread machine specific notes. On ia64 we use this function to flush the dirty registers onto the backingstore before we write out the PRSTATUS notes. Tested on: alpha, amd64, i386, ia64 & sparc64 Not tested on: arm, powerpc
* Update for the KDB framework:marcel2004-07-101-8/+29
| | | | | | | | | | | | | | | | | | | | | o ksym_start and ksym_end changed type to vm_offset_t. o Make debugging support conditional upon KDB instead of DDB. o Call kdb_enter() instead of breakpoint(). o Remove implementation of Debugger(). o Call kdb_trap() according to the new world order. unwinder: o s/db_active/kdb_active/g o Various s/ddb/kdb/g o Add support for unwinding from the PCB as well as the trapframe. Abuse a spare field in the special register set to flag whether the PCB was actually constructed from a trapframe so that we can make the necessary adjustments. md_var.h: o Add RSE convenience macros. o Add ia64_bsp_adjust() to add or subtract from BSP while taking NaT collections into account.
* Do not pre-map the I/O port space. On the Intel Tiger 4 this conflictsmarcel2004-02-221-1/+0
| | | | | | | | | with a memory mapped I/O range that's immediately before it and is not 256MB aligned. As a result, when an address is accessed in the memory mapped range and a direct mapping is added for it, it overlaps with the pre-mapped I/O port space and causes a machine check. Based on a patch from: arun@
* Remove ia64_highfp_load() now that it's unused.marcel2003-11-121-1/+0
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* Add prototypes for spillfd() and unaligned_fixup().marcel2003-10-231-0/+2
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* Fix a place where I forgot to change the code that checks whethermarcel2003-09-051-1/+1
| | | | | | | | | | | | | | | | | we return to kernel or userland. This triggered a panic in a KSE application when TDF_USTATCLOCK was set in the case userland was interrupted, but we never called ast() on our way out. As such, we called ast() at some other time. Unfortunately, TDF_USTATCLOCK handling assumes running in the interrupt thread. This was not the case anymore. To avoid making the same mistake later, interrupt() now returns to its caller whether we interrupted userland or not. This avoids that we have to duplicate the check in assembly, where it's bound to fall off the scope. Now we simply check the return value and call ast() if appropriate. Run into this: davidxu
* Further cleanup <machine/cpu.h> and <machine/md_var.h>: move the MImarcel2003-08-161-5/+17
| | | | | | | | | | | | | | | | | | | prototypes of cpu_halt(), cpu_reset() and swi_vm() from md_var.h to cpu.h. This affects db_command.c and kern_shutdown.c. ia64: move all MD prototypes from cpu.h to md_var.h. This affects madt.c, interrupt.c and mp_machdep.c. Remove is_physical_memory(). It's not used (vm_machdep.c). alpha: the MD prototypes have been left in cpu.h with a comment that they should be there. Moving them is left for later. It was expected that the impact would be significant enough to be done in a seperate commit. powerpc: MD prototypes left in cpu.h. Comment added. Suggested by: bde Tested with: make universe (pc98 incomplete)
* Remove special casing for running in the simulator from the kernelmarcel2003-02-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and instead add platform, firmware and EFI stubs to the loader. The net effect of this change is that besides a special console and disk driver, the kernel has no knowledge of the simulator. This has the following advantages: o Simulator support is much harder to break, o It's easier to make use of more feature complete simulators. This would only need a change in the simulator specific loader, o Running SMP kernels within the simulator. Note that ski at this time does not simulate IPIs, so there's no way to start APs. The platform, firmware and EFI stubs describe the following hardware: o 4 CPU Itanium, o 128 MB RAM within the 4GB address space, o 64 MB RAM above the 4GB address space. NOTE: The stubs in the skiloader describe a machine that should in parts be defined by the simulator. Things like processor interrupt block and AP wakeup vector cannot be choosen at random because they require interpretation by the simulator. Currently the simulator is ignorant of this. This change introduces an unofficial SSC call SSC_SAL_SET_VECTORS which is ignored by the simulator. Tested with: ski (version 0.943 for linux)
* Change hw.physmem and hw.usermem to unsigned long like they used to bepeter2002-08-301-1/+1
| | | | | | | | | | | | | in the original hardwired sysctl implementation. The buf size calculator still overflows an integer on machines with large KVA (eg: ia64) where the number of pages does not fit into an int. Use 'long' there. Change Maxmem and physmem and related variables to 'long', mostly for completeness. Machines are not likely to overflow 'int' pages in the near term, but then again, 640K ought to be enough for anybody. This comes for free on 32 bit machines, so why not?
* o Move definition of struct ia64_fdesc here to remove duplication.marcel2002-05-051-1/+11
| | | | o Add prototype of os_boot_rendez.
* Remove __P.alfred2002-03-201-6/+6
| | | | Reviewd by: peter
* [partially forced commit due to pilot error in earlier commit attempt]des2001-10-211-4/+0
| | | | | | | | | | | | | | | | | {set,fill}_{,fp,db}regs() fixup: - Add dummy {set,fill}_dbregs() on architectures that don't have them. - KSEfy the powerpc versions (struct proc -> struct thread). - Some architectures had the prototypes in md_var.h, some in reg.h, and some in both; for consistency, move them to reg.h on all platforms. These functions aren't really MD (the implementation is MD, but the interface is MI), so they should move to an MI header, but I haven't figured out which one yet. Run-tested on i386, build-tested on Alpha, untested on other platforms.
* Add declaration of ia64_running_in_simulator().dfr2001-09-221-0/+1
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* KSE Milestone 2julian2001-09-121-5/+5
| | | | | | | | | | | | | | Note ALL MODULES MUST BE RECOMPILED make the kernel aware that there are smaller units of scheduling than the process. (but only allow one thread per process at this time). This is functionally equivalent to teh previousl -current except that there is a thread associated with each process. Sorry john! (your next MFC will be a doosie!) Reviewed by: peter@freebsd.org, dillon@freebsd.org X-MFC after: ha ha ha ha
* vm_page_zero_idle() is no longer MD.peter2001-08-251-1/+0
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* Remove the last of the MD netisr code. It is now all MI. Removejake2000-12-051-1/+0
| | | | | | | | spending, which was unused now that all software interrupts have their own thread. Make the legacy schednetisr use an atomic op for setting bits in the netisr mask. Reviewed by: jhb
* - Overhaul the software interrupt code to use interrupt threads for eachjhb2000-10-251-1/+1
| | | | | | | | | | | | | | | | | | | type of software interrupt. Roughly, what used to be a bit in spending now maps to a swi thread. Each thread can have multiple handlers, just like a hardware interrupt thread. - Instead of using a bitmask of pending interrupts, we schedule the specific software interrupt thread to run, so spending, NSWI, and the shandlers array are no longer needed. We can now have an arbitrary number of software interrupt threads. When you register a software interrupt thread via sinthand_add(), you get back a struct intrhand that you pass to sched_swi() when you wish to schedule your swi thread to run. - Convert the name of 'struct intrec' to 'struct intrhand' as it is a bit more intuitive. Also, prefix all the members of struct intrhand with 'ih_'. - Make swi_net() a MI function since there is now no point in it being MD. Submitted by: cp
* This is the first snapshot of the FreeBSD/ia64 kernel. This kernel willdfr2000-09-291-0/+57
not work on any real hardware (or fully work on any simulator). Much more needs to happen before this is actually functional but its nice to see the FreeBSD copyright message appear in the ia64 simulator.
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