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* If an interrupt on an I/O APIC is moved to a different CPU after it hasjhb2011-01-131-6/+4
* Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.kib2011-01-091-12/+0
* Copy powerpc/include/_inttypes.h to x86 and replace i386/amd64/pc98tijl2011-01-081-210/+3
* On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather thantijl2011-01-081-2/+2
* On 32 bit architectures define (u)int64_t as (unsigned) long long insteadtijl2011-01-081-11/+6
* Fix types of some values in machine/_limits.h.tijl2011-01-081-7/+2
* Remove unused support for 64 bit long on 32 bit architectures.tijl2011-01-071-11/+0
* Add AT_STACKPROT elf aux vector. Will be used to inform rtld about thekib2011-01-071-1/+2
* Remove bogus usage of INTR_FAST. "Fast" interrupts are now indicated byjhb2011-01-062-4/+4
* Spell CRITICAL_ASSERT correctly.cperciva2011-01-041-2/+1
* Add hamfisted locking to the Xen/PV pmap code: Only allow one thread tocperciva2011-01-041-0/+35
* Make "options XENHVM" compile for i386, not just amd64 -- a largelyrwatson2011-01-046-5/+51
* Adjust the critical section protecting _xen_flush_queue to cover thecperciva2011-01-041-4/+11
* Make i386_set_ldt work on i386/XEN, step 5/5.cperciva2010-12-312-0/+6
* Make i386_set_ldt work on i386/XEN, step 4/5.cperciva2010-12-311-4/+8
* Make i386_set_ldt work on i386/XEN, step 3/5.cperciva2010-12-311-0/+3
* Make i386_set_ldt work on i386/XEN, step 2/5.cperciva2010-12-311-1/+0
* Make i386_set_ldt work on i386/XEN, step 1/5.cperciva2010-12-311-0/+4
* Add driver for DM&P Vortex86 RDC R6040 Fast Ethernet.yongari2010-12-311-0/+1
* Revert r216777, per jhb@imp2010-12-281-4/+2
* Comment out npx and isa from NOTES file. We don't need them hereimp2010-12-281-2/+4
* Remove mem, io, isa and npx since they are duplicative of the entriesimp2010-12-281-7/+0
* Remove a "not strictly correct" (and panic-inducing) workaround for a bugcperciva2010-12-281-15/+2
* Build the modules which can be built. The excluded modules fall into twocperciva2010-12-271-1/+1
* Lock the vm page queue mutex in pmap_pte_release around the callcperciva2010-12-261-0/+2
* Merge amd64 and i386 bus.h and move the resulting header to x86. Replacetijl2010-12-201-1161/+3
* Redo some parts of r216333, specifically, the locking changes toalc2010-12-191-39/+60
* Inform a compiler which asm statements in the x86 implementation ofkib2010-12-181-6/+7
* In pmap_extract(), unlock pmap lock earlier. The calculation does not needkib2010-12-181-1/+1
* Stop lying about supporting cpu_est_clockrate() when TSC is invariant. Thisjkim2010-12-142-3/+18
* In fpudna()/npxdna(), mark FPU context initialized and optionallykib2010-12-121-1/+3
* Reduce the Xen timecounter from 1GHz to 2^-9 GHz, thereby increasing thecperciva2010-12-111-2/+3
* Make the machdep.independent_wallclock sysctl do what it says on the box.cperciva2010-12-111-1/+2
* When r207410 eliminated the acquisition and release of the page queuesalc2010-12-091-61/+40
* Replace i386/i386/busdma_machdep.c and amd64/amd64/busdma_machdep.ccperciva2010-12-091-1222/+0
* Do not subtract 0.5% from estimated frequency if DELAY(9) is driven by TSC.jkim2010-12-081-3/+7
* On amd64, we have (since r1.72, in December 2005) MAX_BPAGES=8192,cperciva2010-12-081-0/+4
* Merge sys/amd64/amd64/tsc.c and sys/i386/i386/tsc.c and move to sys/x86/x86.jkim2010-12-081-281/+0
* Use int for 'tsc_present' instead of u_int. It is just a boolean.jkim2010-12-072-2/+2
* Remove stale comments about P-state invariant TSC and fix style(9) nits.jkim2010-12-072-8/+4
* Do not register a event handler for CPU freqency changes when it is foundjkim2010-12-071-4/+16
* Now the P-state invariant TSC is probed early enough, do not register eventjkim2010-12-071-10/+8
* Probe P-state invariant TSC from rightful place.jkim2010-12-072-22/+23
* MFamd64 r204214: Enforce stronger alignment semantics (require that thecperciva2010-12-051-12/+18
* Remove gratuitous i386/amd64 inconsistency in favour of the less verbosecperciva2010-12-041-2/+1
* Remove unnecessary #includes which seem to have been accidentally addedcperciva2010-12-041-3/+0
* Revert r216161. It is not necessary because we zero-fill BSS anyway.jkim2010-12-031-1/+1
* Explicitly initialize TSC frequency. To calibrate TSC frequency, we usejkim2010-12-031-1/+1
* Do not change CPU ticker frequency if TSC is P-state invariant. Note thisjkim2010-12-031-0/+3
* Revert r216134. This checkin broke platforms where bus_space are macros:brucec2010-12-031-24/+12
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