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* Migrate many bus_alloc_resource() calls to bus_alloc_resource_anywhere().jhibbits2016-02-271-2/+2
* Adjust i386 comment to match amd64 one after r294311.kib2016-01-191-5/+6
* Convert between abridged (from FXSAVE) and unabridged (from FSAVE)kib2015-07-101-6/+13
* Now that aesni won't reuse fpu contexts (D3016), add seatbelts to thejmg2015-07-081-2/+10
* Provide npx_get_fsave(9) and npx_set_fsave(9) functions to obtain andkib2015-06-291-0/+96
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsjhb2015-04-301-9/+0
* Remove write-only variable.kib2015-03-121-2/+0
* Improve support for XSAVE with debuggers.jhb2014-11-211-0/+7
* Lock spic(4) and mark it MPSAFE:jhb2014-11-201-31/+39
* Move all of the XSAVE support under #ifdef I686_CPU and fix the buildjhb2014-11-031-3/+34
* MFamd64: Add support for extended FPU states on i386. This includesjhb2014-11-021-158/+361
* MFamd64: Explicitly initialize the mxcsr during npxinit().jhb2014-11-021-0/+9
* Save and restore FPU state across suspend and resume. In earlier revisionsjhb2014-08-301-0/+37
* Add FPU_KERN_KTHR flag to fpu_kern_enter(9), which avoids saving FPUkib2014-06-231-0/+7
* Implement vector callback for PVHVM and unify event channel implementationsgibbs2013-08-291-1/+1
* - Correct spelling in commentsgabor2013-04-171-1/+1
* - Correct mispellings of word miscellaneousgabor2013-04-171-1/+1
* Locking for todr got pushed down into inittodr and the clientimp2013-02-211-10/+2
* Revert previous commit...kevlo2012-10-101-1/+1
* Prefer NULL over 0 for pointerskevlo2012-10-091-1/+1
* Change (unused) prototype for stmxcsr() to match reality.kib2012-07-301-1/+1
* MFamd64 r238623:kib2012-07-261-15/+14
* MFCamd64 r238598:kib2012-07-211-2/+25
* MFamd64 r238668:kib2012-07-211-16/+13
* MFamd64 r238597:kib2012-07-211-0/+2
* Add a clts() wrapper around the 'clts' instruction to <machine/cpufunc.h>jhb2012-07-091-11/+8
* Add support for the extended FPU states on amd64, both for nativekib2012-01-211-1/+45
* Use atomic load & store for TSC frequency. It may be overkill for amd64 butjkim2011-04-071-11/+17
* Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq becausejkim2011-03-101-1/+1
* In fpudna()/npxdna(), mark FPU context initialized and optionallykib2010-12-121-1/+3
* Remove npxgetregs(), npxsetregs(), fpugetregs() and fpusetregs()kib2010-11-261-72/+22
* Use unambiguous inline assembly to load a float variable. GNU asdim2010-11-251-1/+1
* Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returnedjhb2010-10-251-3/+3
* Simplify fldcw() macro. There is no reason to use pointer here. No objectjkim2010-07-261-5/+5
* Remove an unused macro since r189418.jkim2010-07-261-1/+0
* Reduce diff against fenv.h:jkim2010-07-261-12/+14
* FNSTSW instruction can use AX register as an operand.jkim2010-07-261-1/+1
* After the FPU use requires #MF working due to INT13 FPU exception handlingkib2010-06-231-35/+27
* Remove the support for int13 FPU exception reporting on i386. It iskib2010-06-231-132/+31
* Remove unused i586 optimized bcopy/bzero/etc implementations that utilizekib2010-06-231-54/+1
* Introduce the x86 kernel interfaces to allow kernel code to usekib2010-06-051-19/+158
* Introduce the new kernel sub-tree x86 which should contain all the codeattilio2010-02-259-2735/+0
* - Allow clock subsystem to be compiled without the apic support [0]attilio2010-01-171-2/+0
* Handling all the three clocks (hardclock, softclock, profclock) with theattilio2010-01-151-7/+8
* Make isa_dma functions MPSAFE by introducing its own private lock. Theserdivacky2009-11-091-27/+83
* - Teach vesa(4) and dpms(4) about x86emu. [1]delphij2009-09-092-1926/+0
* Partially revert 196524: this part of change should not be committed asdelphij2009-08-311-20/+25
* Fix build broken in r196524.glebius2009-08-251-8/+0
* Fix VESA modes and allow 8bit depth modes.delphij2009-08-241-21/+24
* Improve the handling of cpuset with interrupts.jhb2009-07-011-2/+2
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