| Commit message (Expand) | Author | Age | Files | Lines |
* | Add a driver for the on-die digital thermal sensor found on Intel Core | des | 2007-08-15 | 1 | -0/+1 |
* | Add CPUID2_PDCM | des | 2007-05-31 | 1 | -0/+1 |
* | Add the PG_NX support for i386/PAE. | ru | 2007-04-06 | 1 | -0/+8 |
* | - Add macros for newly added CPUID bits in the corresponding header files. | jkim | 2007-03-20 | 1 | -0/+2 |
* | Add another CPUID for AMD CPUs and fix style(9) while I am here. | jkim | 2007-03-12 | 1 | -112/+113 |
* | Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors. | jkim | 2007-01-09 | 1 | -1/+2 |
* | Sync specialreg.h changes between amd64 and i386 with few fixes. | jkim | 2006-07-13 | 1 | -14/+21 |
* | fix typo in identcpu.c and add one define to specialreg.h. | mr | 2006-07-12 | 1 | -1/+4 |
* | First step to identify and initialize the newer VIA C7 CPU | mr | 2006-07-12 | 1 | -0/+32 |
* | Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register. | jkim | 2006-07-12 | 1 | -0/+2 |
* | Style fix, use low-case. | davidxu | 2006-06-19 | 1 | -1/+1 |
* | Clear bit 22 in MSR IA32_MISC_ENABLE, according to Intel document, | davidxu | 2006-06-19 | 1 | -0/+1 |
* | Add various constants for the PAT MSR and the PAT PTE and PDE flags. | jhb | 2006-05-01 | 1 | -0/+13 |
* | - Print number of physical/logical cores and more CPUID info. | jkim | 2005-10-14 | 1 | -0/+22 |
* | Remove advertising clause from University of California Regent's | imp | 2004-04-07 | 1 | -4/+0 |
* | Add new CPU_ENABLE_TCC option, from NOTES: | sobomax | 2004-01-18 | 1 | -0/+3 |
* | - Add macros describing some new MSR's in the Pentium 4 and some older | jhb | 2003-08-15 | 1 | -0/+25 |
* | <b30> is 'IA64' - ie: you're running on an ia64 in 32 bit mode. | peter | 2003-05-01 | 1 | -1/+1 |
* | Bah, add in a missing space char I noticed when MFC'ing this. | jhb | 2003-01-22 | 1 | -1/+1 |
* | - Fix the name of the hyperthreading cpuid feature flag to be HTT instead | jhb | 2003-01-08 | 1 | -1/+9 |
* | Add additional cpuid feature flags and put into a canonical format. | mp | 2002-06-22 | 1 | -18/+33 |
* | Activate SSE/SIMD. This is the extra context switching support that | peter | 2001-07-12 | 1 | -0/+2 |
* | Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that | peter | 1999-09-10 | 1 | -0/+2 |
* | $Id$ -> $FreeBSD$ | peter | 1999-08-28 | 1 | -1/+1 |
* | Add defines for the P6 model-specific registers. | msmith | 1999-04-07 | 1 | -1/+58 |
* | - Implement enabling write allocate on AMD K5/K6/K6-2 cpus. | kato | 1998-10-06 | 1 | -1/+6 |
* | Defined CCR6 and CCR7 (configuration registers of M2 CPU.) | kato | 1998-03-04 | 1 | -1/+5 |
* | Enabled the FPU emilaute bit define: CR0_EM | fsmp | 1997-07-21 | 1 | -3/+1 |
* | Improved CPU identification and initialization routines. This | kato | 1997-03-22 | 1 | -44/+172 |
* | Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not | peter | 1997-02-22 | 1 | -1/+1 |
* | Make the long-awaited change from $Id$ to $FreeBSD$ | jkh | 1997-01-14 | 1 | -1/+1 |
* | Support the PG_G flag on Pentium-Pro processors. This pretty | dyson | 1996-11-11 | 1 | -1/+34 |
* | Added missing CR0_NW define for Cyrix 486DLC support. It's still not | sos | 1996-06-03 | 1 | -1/+3 |
* | Fix a bunch of spelling errors in the comment fields of | mpp | 1996-01-30 | 1 | -3/+3 |
* | Remove trailing whitespace. | rgrimes | 1995-05-30 | 1 | -2/+2 |
* | Enable define of CR0_AM to prepare for implementing alignment checking. | bde | 1995-01-14 | 1 | -7/+3 |
* | Improved some comments. | dg | 1994-09-04 | 1 | -2/+2 |
* | Detect if we're running on a Cyrix 486DLC and enable automatic cache | pst | 1994-09-04 | 1 | -1/+54 |
* | Made all header files idempotent and moved incorrect common data from | wollman | 1993-11-07 | 1 | -1/+5 |
* | Removed all patch kit headers, sccsid and rcsid strings, put $Id$ in, some | rgrimes | 1993-10-16 | 1 | -9/+2 |
* | Initial import, 0.1 + pk 0.2.4-B1 | rgrimes | 1993-06-12 | 1 | -0/+67 |