| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | MFC 260557,271076,271077,271082,271083,271098: | jhb | 2014-12-22 | 1 | -1596/+0 |
| * | MFC r257856: | kib | 2013-11-15 | 1 | -6/+6 |
| * | x86: detect mwait capabilities and extensions, when present | avg | 2013-07-28 | 1 | -0/+7 |
| * | After r205013, amd64 and i386 CPU family and model IDs were printed out | dim | 2012-09-21 | 1 | -2/+2 |
| * | Recognize the RDRAND instruction feature. | jhb | 2012-04-09 | 1 | -1/+1 |
| * | Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. | jkim | 2011-05-17 | 1 | -27/+25 |
| * | Define "Hypervisor Present" bit. This bit is used by several hypervisors to | jkim | 2011-04-28 | 1 | -1/+1 |
| * | Probe capability to find effective frequency. When the TSC is P-state | jkim | 2011-04-12 | 1 | -1/+4 |
| * | Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta | jkim | 2011-03-26 | 1 | -21/+19 |
| * | Detect NSC/AMD Geode SC1100 properly, not just Stepping 0. Although it is | jkim | 2011-03-10 | 1 | -2/+3 |
| * | Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because | jkim | 2011-03-10 | 1 | -11/+15 |
| * | Remove stale comments about P-state invariant TSC and fix style(9) nits. | jkim | 2010-12-07 | 1 | -4/+2 |
| * | Do not register a event handler for CPU freqency changes when it is found | jkim | 2010-12-07 | 1 | -4/+16 |
| * | Probe P-state invariant TSC from rightful place. | jkim | 2010-12-07 | 1 | -22/+0 |
| * | Use intr_disable() and intr_restore() instead of frobbing the flags register | jhb | 2010-10-25 | 1 | -4/+3 |
| * | Display PCID capability of CPU and add CPUID define for it. | kib | 2010-10-05 | 1 | -1/+1 |
| * | Remove unused i586 optimized bcopy/bzero/etc implementations that utilize | kib | 2010-06-23 | 1 | -1/+0 |
| * | Add definitions for Intel AESNI CPUID bits and print the capabilities | kib | 2010-05-05 | 1 | -2/+2 |
| * | Print out the family and model from the cpu_id. This is especially useful | jhb | 2010-03-11 | 1 | -2/+4 |
| * | x86 cpu features: add MOVBE reporting and flag | avg | 2009-11-30 | 1 | -1/+1 |
| * | Fix cpu model for PODP5V83. It is P24T, not P54T. | nyan | 2009-11-12 | 1 | -1/+1 |
| * | Strip from messages for users external URLs the project cannot directly | attilio | 2009-11-05 | 1 | -4/+1 |
| * | Opteron rev E family of processor expose a bug where, in very rare | attilio | 2009-11-04 | 1 | -0/+18 |
| * | Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce | jkim | 2009-09-10 | 1 | -9/+9 |
| * | Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386 and | jkim | 2009-05-04 | 1 | -11/+18 |
| * | - Add support for cpuid leaf 0xb. This allows us to determine the | jeff | 2009-04-29 | 1 | -26/+0 |
| * | VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine | jkim | 2009-01-22 | 1 | -1/+2 |
| * | Add basic i386 support for VIA Nano processors. | jkim | 2009-01-12 | 1 | -2/+12 |
| * | Add more CPUID bits from AMD CPUID Specification Rev. 2.28. | jkim | 2008-12-12 | 1 | -8/+8 |
| * | According to "Intel 64 and IA-32 Architectures Software Developer's Manual | mav | 2008-11-30 | 1 | -1/+5 |
| * | Use newly introduced cpu_vendor_id to make invariant TSC detection more | jkim | 2008-11-26 | 1 | -8/+13 |
| * | Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). | jkim | 2008-11-26 | 1 | -37/+70 |
| * | Core i7 supports invaliant TSC and the presense is presented on | takawata | 2008-11-25 | 1 | -1/+2 |
| * | Really fix i386 test this time. | jkim | 2008-10-22 | 1 | -1/+1 |
| * | Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs | jkim | 2008-10-22 | 1 | -4/+9 |
| * | Fix compiler error with missing/unneded ')' | ache | 2008-10-22 | 1 | -3/+3 |
| * | Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher | jkim | 2008-10-22 | 1 | -1/+3 |
| * | Turn off CPU frequency change notifiers when the TSC is P-state invariant | jkim | 2008-10-21 | 1 | -2/+11 |
| * | Detect Advanced Power Management Information for AMD CPUs. | jkim | 2008-10-21 | 1 | -0/+4 |
| * | - Recognize SAVE and OSXSAVE extended processor features. | stas | 2008-09-18 | 1 | -2/+2 |
| * | MFamd64: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB | jhb | 2008-09-17 | 1 | -6/+6 |
| * | The VM system no longer uses setPQL2(). Remove it and its helpers. | alc | 2008-05-23 | 1 | -298/+0 |
| * | - Remove the old smp cpu topology specification with a new, more flexible | jeff | 2008-03-02 | 1 | -1/+6 |
| * | With the recent change to enable CPU brands from the VIA chips, the | jhb | 2008-02-29 | 1 | -24/+41 |
| * | - Check for the extended CPUID registers on VIA CPUs so we can get the | jhb | 2008-02-28 | 1 | -2/+2 |
| * | Support the VIA C7 Eden CPU and treat it just like a C7 Esther. We may | jhb | 2008-02-25 | 1 | -0/+3 |
| * | Add descriptive comment to PDCM entry. | des | 2007-05-29 | 1 | -1/+1 |
| * | Remove a pointless bootverbose message. | des | 2007-05-29 | 1 | -6/+1 |
| * | Add feature name for features2 bit 15. | des | 2007-05-29 | 1 | -1/+1 |
| * | On AMD's Geode LX: Force the TSC to run through core-suspension so we can | phk | 2007-04-18 | 1 | -0/+8 |
