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path: root/sys/dev/pci/pci.c
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* Properly handle I/O windows in bridges with the ISA enable bit set. Thesejhb2013-07-181-4/+42
* - As it turns out, not only MSI-X is broken for devices passed through bymarius2013-07-091-34/+70
* Make detaching drivers from PCI devices more robust. While here, fix ajhb2013-06-271-1/+30
* Disable hw.pci.realloc_bars by default. It wasn't needed for the originaljhb2013-06-241-1/+1
* Revision 233677 broke certain machines. Specifically, if the firmware/BIOSjhb2013-05-091-2/+29
* - Complete r231621 by also blacklisting the bridge used by VMware for PCIemarius2013-03-021-10/+11
* Remove the quirk to allow use of MSI when the guest is running inside bhyve.neel2013-02-281-1/+0
* Add quirk to indicate that the bhyve hostbridge is capable of supportingneel2013-01-051-0/+1
* Remove duplicate const specifiers in many drivers (I hope I got all ofdim2012-11-051-1/+1
* The correct generic term for PCIS_STORAGE_NVM is "NVM" not "NVM Express".gavin2012-09-201-1/+1
* Recognise NVM Express devices and pretty-print their name.gavin2012-09-191-0/+1
* Align the PCI Express #defines with the style used for the PCI-Xgavin2012-09-181-40/+40
* Only check to see if a memory resource is a PCI ROM BAR when activatingjhb2012-05-231-2/+2
* Fix couple of style nits.jkim2012-03-291-2/+2
* Revert r233662 and generalize the hack. Writing zero to BAR actually doesjkim2012-03-291-41/+6
* Use a more proper fix for enabling HT MSI mapping windows on Host-PCIjhb2012-03-291-1/+1
* Fix for boot issue: Don't disable BARs on AGP devices. In general:hselasky2012-03-291-0/+21
* Add a PCI quirk to ignore PCI map registers from configuration space.jkim2012-03-141-8/+36
* Save more of config space for PCI Express and PCI-X devices.kan2012-03-081-0/+103
* Remove the PAE-specific 2GB DMA boundary since HEAD now supports a proper 4Gjhb2012-03-071-11/+0
* Simplify the PCI bus dma tag code a bit. First, don't create a tag atjhb2012-03-071-7/+15
* Expand the set of APIs available for locating PCI capabilities:jhb2012-03-031-6/+95
* Fix a typo.jhb2012-03-031-1/+1
* - Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge.jhb2012-03-021-5/+58
* Add pci_save_state() and pci_restore_state() wrappers aroundjhb2012-03-011-0/+19
* Use pci_printf() instead of a home-rolled version in the VPD parsing code.jhb2012-02-291-17/+9
* - As it turns out, MSI-X is broken for at least LSI SAS1068E when passedmarius2012-02-141-10/+11
* Properly return success once a matching VPD entry is found injhb2012-01-191-3/+1
* Add missing XHCI early takeover code. The XHCI takeover codehselasky2011-07-221-1/+66
* PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCImarius2011-07-131-1/+4
* Implement pci_find_class(9), the function to find a pci device by its class.kib2011-07-091-0/+15
* Minor whitespace and style fixes.jhb2011-06-211-3/+4
* More properly handle Cardbus cards that that store their CIS in a BAR afterjhb2011-06-061-0/+11
* Reimplement how PCI-PCI bridges manage their I/O windows. Previously thejhb2011-05-031-0/+20
* Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver,jhb2011-05-021-0/+1
* Only align MSI message groups based on the number of messages beingjhb2011-04-271-1/+1
* Explicitly track the state of all known BARs for each PCI device. The PCIjhb2011-03-311-49/+153
* Rename pci_find_extcap() to pci_find_cap(). PCI now uses the termjhb2011-03-221-5/+5
* Partially revert previous change. Drop the quirk to disable MSI for HTjhb2011-03-181-19/+2
* Fix a few issues with HyperTransport devices and MSI interrupts:jhb2011-03-181-4/+43
* Properly handle BARs bigger than 4G. The '1' was treated as an intjhb2011-02-231-3/+3
* Use the preload_fetch_addr() and preload_fetch_size() conveniencemarcel2011-02-131-9/+14
* Resume critical PCI devices (and their children) first, then everything elsejkim2010-11-221-1/+28
* The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registersnwhitehorn2010-10-251-1/+1
* - Add a new PCI quirk to whitelist an old chipset that doesn't supportjhb2010-10-221-1/+31
* Clarify a misleading comment. The test in pci_reserve_map() was meant tojhb2010-10-211-9/+9
* Update PCI power management registers per PCI Bus Power Management Interfacejkim2010-10-201-1/+1
* Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets youjkim2010-10-201-1/+9
* Remove PCI header type 0 restriction from power state changes. PCI config.jkim2010-10-191-3/+1
* Do not apply do_power_resume for suspending case. When do_powerstate wasjkim2010-10-191-4/+3
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