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path: root/sys/dev/hwpmc/hwpmc_core.c
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* Remove slightly used const values that can be replaced with nitems().pfg2016-04-211-4/+2
* If full width writes to the performance monitoring counters arekib2016-02-121-11/+25
* More fixes in the various intel processors, fixing missingrrs2015-12-111-76/+75
* Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's ...rrs2015-11-301-240/+337
* Fix two bugs that could result in PMC sampling effectively stopping.jhb2015-05-191-0/+8
* Use the proper mask when reloading sampling PMCs for Core CPUs.jhb2015-05-191-1/+1
* Convert hwpmc(4) debug printfs over to KTR.jhb2015-05-081-32/+32
* hwpmc: add initial Intel Broadwell support.rpaulo2015-04-051-1/+6
* Remove whitespace.rpaulo2015-04-051-9/+9
* hwpmc: Fix event number to match enum namerstone2015-03-121-2/+2
* Add missing counter definitionsrstone2015-03-101-1/+6
* Fix Ivy Bridge+ MEM_UOPS_RETIRED countersrstone2015-03-101-22/+14
* Fix Sandy Bridge+ hwpmc branch countersrstone2015-03-101-28/+39
* Fix pmc unit restrictions to match documentationrstone2015-03-101-2/+2
* style(9) cleanuprstone2015-01-221-13/+24
* Update the hwpmc driver to have the new type HASWELL_XEON. Alsorrs2015-01-141-230/+264
* Since introducing the extra mapping in r250103 for architectural performancebz2014-10-071-1/+1
* For Xeon 7500 and 48XX (Nehalem EX and Westmere EX) variants of thekib2014-06-041-1/+5
* Update hwpmc to support core events for Atom Silvermont microarchitecture.hiren2014-03-201-37/+87
* Fix pointer type in call to malloceadler2014-03-131-1/+1
* Move <machine/apicvar.h> to <x86/apicvar.h>.jhb2014-01-231-1/+1
* o Remove assertions on ipa_version as sometimes the version detectionattilio2013-12-201-13/+7
* Fix a >80 character long line, introduced in my previous commit.adrian2013-08-251-1/+2
* Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandyadrian2013-08-251-12/+14
* Add in missing events for Sandy Bridge Xeon.adrian2013-08-181-5/+11
* Suppress a GCC warning. This warning is actually bogus and newer GCCdavide2013-05-021-1/+1
* The Intel PMC architectural events have encodings which are identical todavide2013-04-301-17/+34
* Fixup Westmere hwpmc(4) support: add missing CPU flag so thatdavide2013-04-301-3/+3
* Improve/correct a comment. We now support a lot more cpu types.hiren2013-04-141-1/+1
* Cosmetic change: make a comment reference Sandy Bridge *Xeon*rstone2013-04-121-1/+1
* Trailing whitespace cleanup along with 80 column enforcemnt.sbruno2013-04-031-64/+68
* Update hwpmc to support Haswell class processors.sbruno2013-03-281-163/+204
* Update hwpmc to support the Xeon class of Ivybridge processors.sbruno2013-01-311-191/+218
* Update hwpmc to support the Xeon class of Sandybridge processors.sbruno2012-10-191-211/+305
* Complete and merge the list between Sandy/Ivy bridge of eventsfabient2012-09-071-28/+18
* Add Intel Ivy Bridge support to hwpmc(9).fabient2012-09-061-173/+223
* Fix so that ,usr and ,os work correctly with fixed function (IAF)gnn2012-05-021-1/+2
* Add software PMC support.fabient2012-03-281-3/+3
* Fix crash on VirtualBox (and probably on some real hardware):gonzo2012-03-271-1/+5
* Properly mask off bits that are not supported in the IAP counters.gnn2012-03-061-1/+1
* - Add support for the Intel Sandy Bridge microarchitecture (both core and unc...davide2012-03-011-153/+342
* Update PMC events from October 2011 Intel documentation.fabient2012-01-041-6/+5
* - Remove extra spaceeadler2011-12-211-1/+1
* There's a small set of events on Nehalem, that are not supported infabient2011-12-121-1/+12
* Update Westmere uncore event exception list.fabient2011-12-021-0/+8
* Fix invalid class removal when IAF is not the last class.fabient2010-09-051-15/+2
* Make sure that we clear the correct bits when we turn offgnn2010-07-291-21/+28
* Fix a panic brought about by writing an MSR without a proper mask.gnn2010-07-131-13/+32
* - Fix a typo OFFCORE_REQUESTS.ANY.RFO is B0H10H and not 80H10H.fabient2010-04-151-1/+2
* - Support for uncore counting events: one fixed PMC with the uncorefabient2010-04-021-408/+638
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