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* Revert r132291.mav2010-09-301-2/+1
* Add missing le32toh(), same as recently done in ata-siliconimage.c.mav2010-09-241-1/+1
* Add missing byteswap, works on big endian systems now (tested on Netlogicjchandra2010-09-231-1/+1
* Fix a problem where device detection would work unreliably on Serverworksnwhitehorn2010-09-091-18/+25
* Add fix for SiI3114 and SiI3512 chips bug, which caused sending R_ERR inmav2010-09-021-0/+8
* SATA1.x SiliconImage controllers on power-on reset TFD Status register intomav2010-09-021-0/+1
* Increase device reset timeout from 10 to 15 seconds, same as in ahci(4).mav2010-09-011-1/+1
* Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existingmav2010-08-281-16/+20
* If ata_sata_phy_reset() failed and ata_generic_reset() is not called, markmav2010-07-107-1/+24
* Make hw.ata.ata_dma_check_80pin tunable affect not only device side, butmav2010-07-1010-14/+21
* Following r209299, level interrupts are low by default on PPC, so removenwhitehorn2010-06-181-7/+0
* Some revisions of the Serverworks K2 SATA controller have a datanwhitehorn2010-06-061-0/+10
* Correct the comment. We now use level low instead of edge high for thisnwhitehorn2010-06-051-1/+1
* Partially revert r208162 while waiting for review on a more comprehensivenwhitehorn2010-06-051-0/+7
* Fix use after free on error.mav2010-06-051-0/+1
* Fix PCH chipset IDs. They are 0x3bxx, not 0x3axx.mav2010-06-041-16/+16
* Relocate interrupt sense setting for K2 SATA from the ATA driver to thenwhitehorn2010-05-161-7/+0
* For early ALI chips do not announce I/O sizes that require unsupportedmav2010-04-141-1/+4
* - Add ALI M5228 PATA ID.mav2010-03-011-1/+2
* Oops! Wrong word order. :(mav2010-02-221-16/+16
* Add Intel PCH SATA controller IDs.mav2010-02-221-0/+16
* Report SATA300 chips also as SATA.mav2010-02-051-1/+2
* NetCell is a PCI hardware RAID without cable and mode setting.mav2010-02-011-1/+11
* Add one more type cast, missed in r203043.mav2010-01-271-1/+1
* Do not place fake interrupt register on chip.mav2010-01-261-26/+7
* Restore SATA speed reporting, broken by ATA_CAM changes.mav2010-01-261-1/+18
* Clear ch->devices, if hard-reset failed.mav2010-01-261-1/+2
* Add support for SATA part of Marvell 88SE912x controllers to ahci(4).mav2010-01-261-2/+17
* Report which of IXP700 legacy ATA channels is SATA.mav2010-01-101-2/+23
* Remove extraneous semicolons, no functional changes.mbr2010-01-072-6/+6
* Add support for Intel SCH PATA controller.mav2009-12-221-2/+39
* Spell AMD properly.mav2009-12-211-1/+1
* Add VIA CX700/VX800 chipsets SATA/PATA support.mav2009-12-201-7/+56
* Fairly set master/slave shared PIO/WDMA timings on ITE 821x controllers.mav2009-12-201-4/+6
* Serverworks OSB4 has no 0x4a (piomode) register, do not touch it.mav2009-12-171-2/+4
* Large I/Os on Promise controllers reported to cause UDMA ICRC errors andmav2009-12-161-0/+1
* Set ATA_CHECKS_CABLE when appropriate.marius2009-12-141-1/+17
* Only set ATA_CHECKS_CABLE for chip versions that actually supportmarius2009-12-131-1/+2
* Properly support M5229 revision 0xc7 and 0xc8:marius2009-12-131-5/+8
* Unbreak the ata_atapi() usage. Since r200171 the mode setting functionsmarius2009-12-131-2/+2
* MFp4:mav2009-12-0622-997/+778
* On Soft Reset, read device signature from FIS receive area, instead ofmav2009-12-051-3/+5
* Release over-agressive WDMA0 mode timings as close to spec as chip can.mav2009-11-221-1/+1
* Fix Intel PATA UDMA timings setting, affecting write performance.mav2009-11-221-2/+2
* Change the way in which AHCI+PATA combined controllers, such as JMicronmav2009-11-163-179/+136
* Disable PMP probing for Marvell AHCI controllers.mav2009-11-141-3/+6
* Add support for SATA ports on SATA+PATA Marvell controllers.mav2009-11-131-25/+69
* Add more ICH10 chip IDs.mav2009-11-091-0/+4
* Add IDs for nVidia MCP65/77/79/89 SATA conntrollers.mav2009-11-021-0/+44
* MFp4:mav2009-11-011-0/+1
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