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* Fixes for ARM9/ARM10 :cognet2007-11-281-1/+4
* Correct the logic : we can just invalidate the cache lines, and notcognet2007-11-281-1/+1
* In atomic_fetchadd_32(), do not blindly increase the value of %3.cognet2007-11-271-2/+3
* Remove the 'needbounce' variable from the _bus_dmamap_load_buffer()jhb2007-11-271-10/+4
* Prevent the leakage of wired pages in the following circumstances:alc2007-11-171-0/+21
* Add a kernel config file for the Hot-e HL200 (AT91RM92 based).cognet2007-11-171-0/+151
* o Rename cpu_thread_setup() to cpu_thread_alloc() to bettermarcel2007-11-141-2/+7
* generally we are interested in what thread did something asjulian2007-11-141-4/+4
* Add entries for the L2 cache-related functions for armv5.cognet2007-11-081-0/+5
* Fix for the panic("vm_thread_new: kstack allocation failed") andkib2007-11-057-7/+8
* Remove a staled comment, NPE-C should work fine.cognet2007-11-041-1/+0
* __CPU_XSCALE_PXA2XX -> CPU_XSCALE_PXA2X0kevlo2007-11-011-1/+1
* Don't define get_cachetype() for CPU_ARM9E unless it's going to be used.kevlo2007-10-311-1/+1
* kill commented out line of code.imp2007-10-291-1/+0
* Add an option to be able to override the value of the AT91 master clockcognet2007-10-251-0/+2
* Move some KB920x-specific options into the KB920x file.cognet2007-10-252-4/+4
* Oooops, get the end of the memory right.cognet2007-10-251-1/+1
* KERNBASE should really be KERNVIRTADDR there too.cognet2007-10-241-2/+2
* In ate_get_mac(), try to get the mac address in the right order, at leastcognet2007-10-241-6/+6
* Handle the case where PHYSADDR != KERNPHYSADDR (ie we do not load the kernelcognet2007-10-241-7/+11
* Correct a comment, this was not true anymore.cognet2007-10-241-2/+2
* correct guard variable names.imp2007-10-181-3/+3
* Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Notimp2007-10-187-22/+834
* Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (whichimp2007-10-181-2/+14
* Use the direct mapping, if available, for pmap_zero_page_xscale() as well.cognet2007-10-161-0/+15
* Do not use __XSCALE__ to detect if pld/strd/ldrd is available, usecognet2007-10-135-25/+25
* Define _ARM_ARCH_5E too, so that we know if pld/strd/ldrd are available.cognet2007-10-131-1/+6
* Spelling fix for interupt -> interruptkevlo2007-10-121-2/+2
* Make the PCI code aware of PCI domains (aka PCI segments) so we canmarius2007-09-303-2/+15
* Ok I hope I got it right this time.cognet2007-09-275-25692/+40
* Now that Intel changed the license for the NPE firmware, import it directlycognet2007-09-275-46/+25693
* Fix a comment to reflect the truth.cognet2007-09-271-1/+1
* Change the management of cached pages (PQ_CACHE) in two fundamentalalc2007-09-251-2/+3
* Make sure we do not call _arm_bzero() or _arm_memcpy() if the size is not atcognet2007-09-221-3/+3
* Add various macros for the ADMA unit.cognet2007-09-221-0/+39
* Add a driver for the 7seg found on the CRB board, largely based on thecognet2007-09-228-0/+470
* Twist the RAS logic a bit to avoid branching.cognet2007-09-221-12/+9
* Remove dead code.cognet2007-09-191-1/+0
* Kill bogus printf debugs.imp2007-09-161-7/+0
* Kill overly verbose messages about setting bus width.imp2007-09-161-5/+2
* It has been observed on the mailing lists that the different categoriesalc2007-09-151-4/+4
* It's probably time I learn C.cognet2007-09-121-2/+2
* In __bswap16_var(), make sure the 16 upper bits are cleared; whilecognet2007-09-091-2/+4
* There's no need to re-read PCIR_COMMAND once we set it.cognet2007-09-041-2/+0
* Just wbinv if both PREREAD and PREWRITE are set.cognet2007-08-181-3/+9
* Ooops, we need to define TD_LOCK here.cognet2007-08-081-0/+1
* Add cast to silent gcc warnings.cognet2007-08-071-24/+24
* Use the third argument of cpu_switch(), as done for i386/amd63, as it iscognet2007-08-071-6/+20
* Add in all the USB devices and all the wireless goo. The KB9202 hasimp2007-07-311-0/+44
* Make USB work on the KB9202{,A,B} boards. This has been in p4 for aboutimp2007-07-313-3/+36
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