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* Use the standard __used macro instead of a bare __attribute__.ian2014-03-031-2/+1
* Add EMAC and SRAM controller entries to FDT.ganbold2014-03-034-0/+8
* Add EMAC 10/100 Ethernet controller driver for A10/A20.ganbold2014-03-032-0/+1391
* Add Static Random Access Memory controller driver for A10/A20.ganbold2014-03-032-0/+168
* Add gpio and clock bits for A10/A20's EMAC ethernet controller driver, such as:ganbold2014-03-034-2/+76
* Add __attribute__((used)) so that the delay implementation doesn't getian2014-03-021-0/+1
* Add a tunable to set the number of active cores, and enable SMP by default.ian2014-03-022-3/+11
* tcb device for fdtimp2014-02-281-0/+105
* shdwc device for fdtimp2014-02-281-0/+105
* Add device node for SDRAMC device. Currently just claims device'simp2014-02-281-0/+105
* Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementationian2014-02-283-1/+8
* Add some rudimentary voltage control to go with the rudimentary frequencyian2014-02-281-2/+77
* Supply a DELAY() implementation via weak linkage, so that SoC-specifician2014-02-281-6/+14
* All our current ARM multi-core systems have all cores in one package withian2014-02-281-1/+1
* Initialize the Low Power Mode bits to keep the ARM cores running during WFI.ian2014-02-272-7/+35
* Do not setup interrupt handler (polling is used).br2014-02-271-33/+6
* Add driver for Inter-Integrated Circuit (I2C).br2014-02-273-2/+501
* Style(9) nit: Use tab here.imp2014-02-271-1/+1
* Replace many pasted identical definitions of cpu_initclocks() with a commonian2014-02-2610-71/+25
* Minor tweaks to the imx GPT timer...ian2014-02-261-6/+6
* - Pin configuration is a complete iomux register now and includesbr2014-02-252-34/+49
* Invalidate the SCU cache tag ram on all 4 cores, not just 1-3. I misreadian2014-02-251-7/+11
* Add support for Quartz Module.br2014-02-241-0/+26
* Add the bits needed to run SMP on imx6.ian2014-02-243-0/+170
* Invalidate caches immediately upon entry to init_secondary(). Also setian2014-02-241-2/+4
* Add a new cache maintenance function, idcache_inv_all, to the table, andian2014-02-245-0/+77
* Add an ident line.ian2014-02-241-0/+1
* Actually set the proper bit to indicate TTB shared memory.ian2014-02-231-1/+1
* If the L2 cache type is PIPT, pass a physical address for a flush.ian2014-02-231-0/+4
* Move the declaration for mpentry() into a header file instead of pastingian2014-02-234-7/+1
* Eliminate an unused-var warning by wrapping #if 0 around some tables ofian2014-02-231-0/+2
* Fix a typo _IMX51_TZICRREG_H_ -> _IMX51_TZICREG_H_ (extra R)ian2014-02-231-1/+1
* Don't force bootverbose on anymore, it can be set from ubldr now.ian2014-02-231-3/+0
* Create a generic IMX6 kernel config. This is based on the existingian2014-02-231-0/+155
* Add the FREEBSD_BOOT_LOADER option so that a loaded DTB passed in fromian2014-02-231-0/+2
* Add basic cpu frequency control and temperature monitoring to imx6_anatop.ian2014-02-213-26/+438
* Remove bogus blank line.imp2014-02-211-1/+0
* Add early printf support, wrapped in #if 0 because it's only rarely needed.ian2014-02-201-0/+24
* Give the fdt helper routines static linkage since no global definitionian2014-02-171-2/+2
* Make it possible to use the env kernel config file option for AVILAjhay2014-02-171-0/+2
* - Decrease buffer size.br2014-02-161-3/+6
* Add driver for Synchronous Audio Interface (SAI).br2014-02-162-0/+803
* Oops, remove some dregs of debugging.ian2014-02-161-1/+1
* Make it possible to access the ocotp registers before the ocotp deviceian2014-02-162-15/+71
* Sweep up a couple crumbs left over from the imx6->fsl renaming.ian2014-02-151-2/+3
* It turns out Freescale cleverly made the ocotp device compatible acrossian2014-02-155-94/+92
* Convert the "R1B fix" from a busy-loop in the interrupt handler to a callout.ian2014-02-151-26/+98
* Add a driver to provide access to imx6 on-chip one-time-programmble data.ian2014-02-154-0/+272
* Handle pmap_enter() on already promoted mappings for ARMv6/v7zbb2014-02-151-2/+8
* Remove spurious assertion from pmap_extract_locked() on ARMzbb2014-02-151-4/+0
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