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* Spelling fix for interupt -> interruptkevlo2007-10-121-2/+2
* Make the PCI code aware of PCI domains (aka PCI segments) so we canmarius2007-09-303-2/+15
* Ok I hope I got it right this time.cognet2007-09-275-25692/+40
* Now that Intel changed the license for the NPE firmware, import it directlycognet2007-09-275-46/+25693
* Fix a comment to reflect the truth.cognet2007-09-271-1/+1
* Change the management of cached pages (PQ_CACHE) in two fundamentalalc2007-09-251-2/+3
* Make sure we do not call _arm_bzero() or _arm_memcpy() if the size is not atcognet2007-09-221-3/+3
* Add various macros for the ADMA unit.cognet2007-09-221-0/+39
* Add a driver for the 7seg found on the CRB board, largely based on thecognet2007-09-228-0/+470
* Twist the RAS logic a bit to avoid branching.cognet2007-09-221-12/+9
* Remove dead code.cognet2007-09-191-1/+0
* Kill bogus printf debugs.imp2007-09-161-7/+0
* Kill overly verbose messages about setting bus width.imp2007-09-161-5/+2
* It has been observed on the mailing lists that the different categoriesalc2007-09-151-4/+4
* It's probably time I learn C.cognet2007-09-121-2/+2
* In __bswap16_var(), make sure the 16 upper bits are cleared; whilecognet2007-09-091-2/+4
* There's no need to re-read PCIR_COMMAND once we set it.cognet2007-09-041-2/+0
* Just wbinv if both PREREAD and PREWRITE are set.cognet2007-08-181-3/+9
* Ooops, we need to define TD_LOCK here.cognet2007-08-081-0/+1
* Add cast to silent gcc warnings.cognet2007-08-071-24/+24
* Use the third argument of cpu_switch(), as done for i386/amd63, as it iscognet2007-08-071-6/+20
* Add in all the USB devices and all the wireless goo. The KB9202 hasimp2007-07-311-0/+44
* Make USB work on the KB9202{,A,B} boards. This has been in p4 for aboutimp2007-07-313-3/+36
* MFppc:cognet2007-07-311-1/+1
* CRB config file.cognet2007-07-271-0/+114
* XScale core 3 definitions.cognet2007-07-271-0/+5
* Cleanupcognet2007-07-272-8/+2
* Do not define NIRQ, it is already defined in include/intr.hcognet2007-07-271-5/+0
* Share the timer and watchdog drivers with the i81342. It's the same,cognet2007-07-272-7/+70
* Add initial IOP342 support.cognet2007-07-2716-0/+2869
* Say if the L2 cache is enabled or disabled as well.cognet2007-07-271-0/+6
* Handle supersections and L2 cache.cognet2007-07-271-30/+36
* Use supersection instead of standard sections to map the whole memorycognet2007-07-271-11/+29
* Fix the cache mode description.cognet2007-07-271-5/+5
* Properly handle supersections.cognet2007-07-272-14/+46
* Bring in two bandaids to get the elf trampoline to work again, until I findcognet2007-07-271-5/+15
* Add a new set of functions to handle L2 cache. Make them no-op for everycognet2007-07-272-16/+67
* Import xscale core 3 cache management functions.cognet2007-07-271-0/+397
* INTR_FILTER bits for armcognet2007-07-271-2/+44
* The iop34x has 128 interrupts.cognet2007-06-161-1/+3
* Introduce pmap_kenter_supersection(), which maps 16MB super-sections intocognet2007-06-113-2/+97
* Fix a spacing nit.imp2007-06-111-1/+0
* Initialize the dma tag's bounce_zone to NULL if we didn't allocate it.cognet2007-06-101-1/+2
* Add kdb_cpu_sync_icache(), intended to synchronize instructionmarcel2007-06-091-0/+5
* There's no nobounce_dmamap on arm.cognet2007-06-071-4/+3
* - PCPU_ADD is no longer spelled with LAZY_ in the middle.jeff2007-06-061-1/+1
* - Change comments and asserts to reflect the removal of the globaljeff2007-06-041-2/+2
* Rework the PCPU_* (MD) interface:attilio2007-06-044-6/+7
* Revert to the previous version where the return value of uart_getenv()marcel2007-06-041-1/+2
* Add the machine-specific definitions for configuring the new physicalalc2007-06-041-0/+15
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