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* Optimise reading of pending interrupt registers. If there are nohselasky2014-05-201-19/+27
* Allow us to compile the Ti iic driver for both OMAP4 and AM335x.andrew2014-05-171-7/+23
* Move the Ti SoCs to use the ARM platform. This should help allowing aandrew2014-05-173-25/+41
* Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to useandrew2014-05-171-15/+18
* Fix a comment s/initarm_/platform_/andrew2014-05-171-1/+1
* Add the start of the ARM platform code. This is based on the PowerPCandrew2014-05-1721-122/+543
* Fix spelling mistake in comment.gavin2014-05-161-1/+1
* Fix return value. Should be logic one or zero.br2014-05-151-1/+1
* Give suitably-endowed ARMs a register similar to the x86 TSC register.markm2014-05-142-1/+53
* Fix typo.br2014-05-141-1/+1
* Remove extra newlines.ray2014-05-141-8/+0
* Cleanup some style nits.ian2014-05-121-8/+4
* Interrupts need to be disabled on entry to cpu_sleep() for ARM. Givenian2014-05-121-2/+2
* Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().ian2014-05-114-1/+39
* Enable SMP for Exynos-based platforms (i.e. Chromebook)grehan2014-05-111-1/+1
* Make the hardware memory and instruction barrier functions work on armv4ian2014-05-111-3/+3
* Rename platform_gpio_init to be SoC specificandrew2014-05-103-3/+3
* Rename platform_gpio_init to be platform specific, and make it static asandrew2014-05-102-4/+4
* Rename platform_gpio_init to be SoC specific, and make it static as it'sandrew2014-05-101-4/+4
* When mapping device memory, use PTE_DEVICE rather than PTE_NOCACHE.ian2014-05-1012-55/+55
* Call idcache_inv_all from the AP core entry code before turning on the MMU.ian2014-05-092-9/+16
* Add the codes for enabling CPU cores of Rockchip RK3188 SoC.ganbold2014-05-094-0/+195
* Consolitate all the AP core startup stuff under a single #ifdef SMP block.ian2014-05-081-16/+6
* Move the mptramp code which is specific to the Marvell ArmadaXP SoC out ofian2014-05-083-47/+58
* Use edge-triggered interrupts rather than polling loops to avoid missingian2014-05-081-15/+28
* Enable PL310 power-saving modes and tune the cache ram latencies for imx6.ian2014-05-061-0/+13
* Add a public routine to set the L2 cache ram latencies. This can beian2014-05-062-0/+42
* Add defines for the bits in the PL310 debug control register.ian2014-05-061-0/+2
* Call platform_pl310_init() before enabling the controller, and handle theian2014-05-061-33/+36
* Break out the code that figures out the L2 cache geometry to its ownian2014-05-061-10/+20
* Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minorian2014-05-061-4/+7
* Fix the tinderbox armv6/arm build failure.loos2014-05-031-0/+2
* Switch to use arm_devmap_add_entry() to setup static device mapping.ganbold2014-05-021-19/+3
* This was copied to IMX6, which has since evolved further. Remove thisimp2014-04-301-159/+0
* Omit from the universe build all config files tagged withimp2014-04-3019-4/+40
* Convert the Zynq SoC support to the new routines for static device mapping.ian2014-04-302-35/+8
* Make this declaration into a proper function prototype.ian2014-04-291-1/+1
* Add SMP support for Zedboard.ian2014-04-294-0/+103
* Don't use multiprocessing-extensions instruction on processors that don'tian2014-04-281-0/+4
* Move duplicated code to print l2 cache config into the common code.ian2014-04-274-68/+45
* Explain why wbinv_all is SMP-safe in this case, and add a missing l2 cacheian2014-04-271-1/+7
* Flush and invalidate caches on each CPU as part of handling IPI_STOP.ian2014-04-272-1/+23
* There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, soian2014-04-272-2/+1
* Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.ian2014-04-271-2/+0
* Provide a proper armv7 implementation of icache_sync_all rather thanian2014-04-274-4/+22
* Call cpu_icache_sync_range() rather than sync_all since we know the rangeian2014-04-261-1/+1
* Retire smp_active. It was racey and caused demonstrated problems withscottl2014-04-261-1/+0
* Stop calling imx51_ccm_foo() clock functions from imx6 code. Insteadian2014-04-268-46/+117
* Remove uncessary cache and TLB maintenance ops.ian2014-04-201-10/+0
* Updates to i.MX53:rpaulo2014-04-085-67/+114
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