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* Cleanup unnecessary semicolons from the kernel.pfg2016-04-1016-40/+40
| | | | Found with devel/coccinelle.
* Enable PHY regulator when the optional "phy-supply" property is present.jmcneill2016-04-091-0/+11
| | | | Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
* Fix incorrect pin definitions for Allwinner A31.jmcneill2016-04-081-20/+20
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* Attach hwreset resources at the same time as clock resources.jmcneill2016-04-081-1/+2
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* Add function for mapping SRAM-D area to USB0 (OTG) controller. Use a lowerjmcneill2016-04-082-1/+21
| | | | | pass number to ensure that this driver is loaded before EMAC or OTG, regardless of the order of nodes in the DT.
* Match on compatible string "allwinner,sun4i-a10-sram-controller" instead ofjmcneill2016-04-081-1/+1
| | | | "allwinner,sun4i-sramc", to match upstream DTS.
* Remove unecessary locking, mostly from places where a read is done of aian2016-04-071-13/+12
| | | | | | | | | value that can't ever be in an inconsistant intermediate state even when some other thread is in the middle of writing the value/register. Locking of the hardware remains in the few places that do r-m-w operations. Locking of metadata access is restricted to places using memcpy or sprintf to modify the metadata.
* Code cleanup: stop searching for a pin in the array and just use the pinian2016-04-071-51/+15
| | | | | number directly as an index. We create the array ourselves and nothing can change the order of items in it, it's a simple 1:1 mapping.
* Fix a copyright glitch before it gets copy-pasted again. I think this mustian2016-04-072-2/+2
| | | | | have started as collateral damage in a global search-replace, then it got copied around when I cloned a file to begin creating a new file.
* Comestic changes; when INTRNG support was added, some functions becameian2016-04-071-40/+40
| | | | | | oddly separated from related functionality. This just moves some blocks of code around so that setup_intr and teardown_intr are near each other again, and likewise for enable/disable_intr. No functional changes.
* Properly initialize isrc_cpu field of ISRC which is setup for an IPI.skra2016-04-071-1/+6
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* Implement intr_isrc_init_on_cpu() and use it to replace very sameskra2016-04-072-42/+10
| | | | | | code implemented in every interrupt controller driver running SMP. This function returns true, if provided ISRC should be enabled on given cpu.
* Convert Allwinner port to extres clk/hwreset/regulator APIs.jmcneill2016-04-0634-1901/+5489
| | | | | | Reviewed by: andrew, gonzo, Emmanuel Vadot <manu@bidouilliste.com> Approved by: gonzo (mentor) Differential Revision: https://reviews.freebsd.org/D5752
* Fix typo. No functional change.skra2016-04-051-2/+2
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* Rework BCM283x gpio interrupt controller for INTRNG. It's used on RPI-Bskra2016-04-051-5/+378
| | | | | | and RPI2 where INTRNG is already enabled by default. Differential Revision: https://reviews.freebsd.org/D5810
* Implement bcm2836 interrupt controller for INTRNG and enable itskra2016-04-054-1/+718
| | | | | | on RPI2 by default. Differential Revision: https://reviews.freebsd.org/D5822
* Rework bcm283x interrupt controller for INTRNG and enable itskra2016-04-052-1/+291
| | | | | | | on RPI-B by default. Reviewed by: gonzo Differential Revision: https://reviews.freebsd.org/D5809
* ehci_interrupt is MPSAFE code. Most drivers in tree calls bus_setup_intrmmel2016-04-051-2/+2
| | | | | | | with MPSAFE, some are not. Fix those. Submitted by: Howard Su <howard0su@gmail.com> Differential Revision: https://reviews.freebsd.org/D5755
* TEGRA: Fix CPU frequency switching.mmel2016-04-053-16/+25
| | | | | | | The PLL_X, base CPU frequency source, doesn't have a bypass switch and thus we must use another frequency source for CPU while changing its frequency. PLL_P is ideal for this, it runs at 480MHz and CPU can be clocked at this frequency at any CPU voltage.
* Add a table to map from the FreeBSD CPUID space to the GIC CPUID space. Onandrew2016-04-041-16/+39
| | | | | | | | | many SoCs these two are the same, however there is no requirement for this to be the case, e.g. on the ARM Juno we boot on what the GIC thinks of as CPU 2, but FreeBSD numbers it CPU 0. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
* Define local-intc for BCM2836 platform (RPI2) and make BCM2835 intcskra2016-04-041-8/+15
| | | | | | | | a child of it. This is done in conformity with Linux dts files and as preparation for rework of BCM2836 interrupt controller for INTRNG. Reviewed by: gonzo Differential Revision: https://reviews.freebsd.org/D5807
* Rework TI gpio interrupt controller for INTRNG. It's used on PANDABOARDskra2016-04-043-15/+345
| | | | | | | and BEAGLEBONE where INTRNG is already enabled by default. Reviewed by: gonzo Differential Revision: https://reviews.freebsd.org/D5806
* Rework am33xx interrupt controller for INTRNG and enable itskra2016-04-042-1/+179
| | | | | | | on BEAGLEBONE by default. Reviewed by: gonzo Differential Revision: https://reviews.freebsd.org/D5805
* Remove FDT specific parts from INTRNG. Change its interface to make itskra2016-04-048-508/+628
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | universal. (1) New struct intr_map_data is defined as a container for arbitrary description of an interrupt used by a device. Typically, an interrupt number and configuration relevant to an interrupt controller is encoded in such description. However, any additional information may be encoded too like a set of cpus on which an interrupt should be enabled or vendor specific data needed for setup of an interrupt in controller. The struct intr_map_data itself is meant to be opaque for INTRNG. (2) An intr_map_irq() function is created which takes an interrupt controller identification and struct intr_map_data as arguments and returns global interrupt number which identifies an interrupt. (3) A set of functions to be used by bus drivers is created as well as a corresponding set of methods for interrupt controller drivers. These sets take both struct resource and struct intr_map_data as one of the arguments. There is a goal to keep struct intr_map_data in struct resource, however, this way a final solution is not limited to that. (4) Other small changes are done to reflect new situation. This is only first step aiming to create stable interface for interrupt controller drivers. Thus, some temporary solution is taken. Interrupt descriptions for devices are stored in INTRNG and two specific mapping function are created to be temporary used by bus drivers. That's why the struct intr_map_data is not opaque for INTRNG now. This temporary solution will be replaced by final one in next step. Differential Revision: https://reviews.freebsd.org/D5730
* Improve HDMI display detection by searching the CEA-861 extension block forjmcneill2016-04-021-1/+48
| | | | | | | an HDMI vendor-specific data block (VSDB) containing the HDMI 24-bit IEEE registration ID (0x000C03). Approved by: gonzo (mentor)
* Move support for Synopsys Designware APB UART out of ns8250 and into ajmcneill2016-04-015-4/+5
| | | | | | | | | separate driver. Add support for activating clock and hwreset resources for these devices when the EXT_RESOURCES option is present. Reviewed by: andrew, mmel, Emmanuel Vadot <manu@bidouilliste.com> Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D5749
* Enable SPI1 on Beaglebone Black.loos2016-03-301-0/+4
| | | | | | SPI1 was chosen because SPI0 shares the gpio pins with I2C1. Sponsored by: Rubicon Communications (Netgate)
* Bump up the read and write timeouts. The old value was too small for lowloos2016-03-301-2/+2
| | | | | | speed transfers. Sponsored by: Rubicon Communications (Netgate)
* Add the SPI driver for am335x.loos2016-03-297-0/+768
| | | | | | | | | | | | This driver works in PIO mode for now, interrupts are available only when FIFO is enabled. The FIFO cannot be used with arbitrary sizes which defeat its general use. At some point we can add DMA transfers where the FIFO can be more useful. Tested on uBMC (microBMC) and BBB. Sponsored by: Rubicon Communications (Netgate)
* Read the CPU ID for the current CPU from the GIC. The GIC may have aandrew2016-03-291-3/+21
| | | | | | | | | | different ID space than the kernel. Because of this we need to read the ID from the hardware. The hardware will provide this value to the CPU by reading any of the first 8 Interrupt Processor Targets Registers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D5706
* Only define the platform methods for the Allwinner platforms we areandrew2016-03-261-5/+12
| | | | | | building for. Sponsored by: ABT Systems Ltd
* ARM: Fix bug introduced in r297286.mmel2016-03-261-7/+4
| | | | | - don't put command line without guard to kernel environment. - kernel environment delivered from ubldr must have absolute precedence.
* TEGRA: Fixes for UART driver:mmel2016-03-261-4/+3
| | | | | | | - add mising 'or' in tegra_uart_attach() Pointed by: kan - fix indentation of tegra_softc - remove forgoten debug printf
* ARM: Parse command line delivered by U-Boot:mmel2016-03-261-8/+61
| | | | | | | | | | | | | - in atags - in DT blob (by using 'fdt chosen' U-Boot command) The command line must start with guard's string 'FreeBSD:' and can contain list of comma separated kenv strings. Also, boot modifier strings from boot.h are recognised and parsed into boothowto. The command line must be passed from U-Boot by setting of bootargs variable: 'setenv bootargs FreeBSD:boot_single=1,vfs.root.mountfrom=ufs:/dev/ada0s1a' followed by 'fdt chosen' (only for DT based boot)
* ARM: Fix ATAG handling in LINUX_BOOT_API:mmel2016-03-262-7/+12
| | | | | | - Don't convert atags address passed from U-Boot. It's real physical address (and we have 1:1 mapping). - Size of tags is encoded in words, not in bytes
* ARM: Teach LINUX_BOOT_ABI to recognize DT blob.mmel2016-03-264-9/+38
| | | | | | | This allow us to boot FreeBSD kernel (using uImage encapsulation) directly from U-boot using 'bootm' command or by Android fastboot loader. For now, kernel uImage must be marked as Linux, but we can add support for FreeBSD into U-Boot later.
* Generalize IPI support for ARM intrng and use it for interruptskra2016-03-245-94/+120
| | | | | | | | | | | | | | | controller IPI provider. New struct intr_ipi is defined which keeps all info about an IPI: its name, counter, send and dispatch methods. Generic intr_ipi_setup(), intr_ipi_send() and intr_ipi_dispatch() functions are implemented. An IPI provider must implement two functions: (1) an intr_ipi_send_t function which is able to send an IPI, (2) a setup function which initializes itself for an IPI and calls intr_ipi_setup() with appropriate arguments. Differential Revision: https://reviews.freebsd.org/D5700
* Fix the resource_list_print_type() calls to use uintmax_t.jhibbits2016-03-226-14/+14
| | | | Missed a bunch from r297000.
* Use the internal references for ADC, this fixes the ADC readings on uBMC.loos2016-03-211-9/+5
| | | | | | Tested on BBB and uBMC. Sponsored by: Rubicon Communications (Netgate)
* Enable multicast addresses on vlan ports. Fixes the reception of broadcastloos2016-03-212-7/+11
| | | | | | packets on vlan aware mode. Sponsored by: Rubicon Communications (Netgate)
* Remove urtwn/urtwnfw; it's built as a module now.adrian2016-03-211-2/+0
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* Fix fallout from r292180 (Dec 2015)... ensure that every driver which hasian2016-03-218-0/+8
| | | | | | | | | a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This is because the kernel linker only searches for symbols in dependent modules, so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc was not compiled into the kernel (even if you hand-loaded mmc first). (Thanks to jilles@ for providing the vital clue about the kernel linker.)
* Remove FREEBSD_BOOT_LOADER that already exists in std.armv6 config file.ian2016-03-201-1/+0
| | | | | PR: 207728 Submitted by: Jia-Shiun Li <jiashiun@gmail.com>
* Count the input and output packets.loos2016-03-182-0/+6
| | | | Sponsored by: Rubicon Communications (Netgate)
* Increase the arbitrary limit of TX segments.loos2016-03-181-1/+1
| | | | Sponsored by: Rubicon Communications (Netgate)
* Set the destination port in all TX segments.loos2016-03-181-8/+9
| | | | Sponsored by: Rubicon Communications (Netgate)
* TEGRA: Connect TEGRA124 to universe build.mmel2016-03-182-1/+3
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* TEGRA: Fix tegra_pcie driver after rman_res_t size change.mmel2016-03-181-8/+7
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* Use uintmax_t (typedef'd to rman_res_t type) for rman ranges.jhibbits2016-03-183-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
* Add support for dual emac mode.loos2016-03-173-705/+1087
| | | | | | | | | | | | | | | | | | | | | | | | In dual emac mode, the CPSW subsystem provides two independent ethernets. This is implemented (as recommended by TI's TRM) with a mixture of switch settings (vlans) and specific features of CPSW subsystem. The driver was splitted to accommodate the shared parts (RX and TX rings for example) while it still provides two independent ethernets. Each of the ethernet ports driver has it's own set of MDIO registers among the other private settings. Previously this driver always operate in promisc mode, now the Switch ALE (address table entry) is properly initialized and enabled. The driver is also tested (and known to work) with both ports operating in single port mode (active_slave 0 or 1). Tested on uBMC (dual emac mode, both ports in single mode, giga and fast ethernet) and BBB (single port, fast ethernet). Sponsored by: Rubicon Communications (Netgate)
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