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* Backout previous commit, Warner committed at91_pio.c...cognet2006-06-231-1/+1
* There's no need to allocate that much phdr/shdr from the stack.cognet2006-06-231-2/+2
* Add the arm9_setup() prototype.cognet2006-06-231-0/+2
* Comment out at91_pio.c, it's not in CVS.cognet2006-06-231-1/+1
* arm9_setup() is now needed even if we're not using a gzipped kernel, so movecognet2006-06-221-1/+1
* Nitsville: the routine is called initarm, not init_arm, correct it inimp2006-06-211-1/+1
* Don't forget to define uart_sa1110_vaddr.cognet2006-06-211-0/+2
* Compute physmem so we can print it correctly on boot.imp2006-06-201-5/+5
* Probe the memory size of the board better. Look at the bus width,imp2006-06-202-2/+60
* Make sure the stack is properly aligned.cognet2006-06-181-10/+32
* comment out twi for now: no iicbus in KB920X: it breaks bootingimp2006-06-171-1/+1
* Carefully note the RMII bit in the config register at attach time.imp2006-06-171-5/+9
* improve reporting of clocksimp2006-06-171-3/+2
* Remove COMPAT_43 from GENERIC (and other kernel configs). For amd64 there'snetchild2006-06-154-4/+0
* Remove mpte optimization from pmap_enter_quick().ups2006-06-151-4/+2
* MFp4:cognet2006-06-122-10/+139
* MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to becognet2006-06-121-1/+1
* Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match thealc2006-06-111-6/+2
* Eliminate spl calls.alc2006-06-111-11/+0
* Add a lock assertion. Remove dead (locking) code. Change some whitealc2006-06-101-36/+4
* Add pmap locking to pmap_extract().alc2006-06-091-4/+8
* Oops it seems I forgot to remove ARM32_NEW_VM_LAYOUT from here.cognet2006-06-073-3/+0
* Add pmap locking to pmap_fault_fixup().alc2006-06-071-16/+7
* Properly synchronize access to the pmap in pmap_extract_and_hold().alc2006-06-071-3/+2
* Now that we use pmap_mapdev_boostrap(), we can get ride of the got_mmucognet2006-06-073-31/+3
* Remove sa1_cache_clean_addr. It isn't needed.imp2006-06-071-2/+0
* Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, andcognet2006-06-062-64/+15
* Remove a bogus, useless, "i++".cognet2006-06-061-1/+0
* Add partial pmap locking.alc2006-06-061-30/+34
* Add partial pmap locking.alc2006-06-062-8/+29
* Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add itcognet2006-06-061-2/+2
* vm_page_alloc_contig() can sleep, so don't even think about using itcognet2006-06-051-8/+9
* Introduce the function pmap_enter_object(). It maps a sequence of residentalc2006-06-051-1/+28
* Don't #error if no CPU is defined but we're not compiling the kernel.cognet2006-06-021-2/+2
* Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.cognet2006-06-011-1/+1
* Introduce pmap_enter_locked() and use it to reimplement pmap_enter_quick().alc2006-06-011-11/+19
* Avoid a LOR by unlocking the vm_page_queue_mtx before calling uma_zalloc,cognet2006-05-311-5/+35
* If our buffer is not aligned on the cache line size, write back/invalidatecognet2006-05-311-7/+10
* Ooops arm10 is armv5, not armv4.cognet2006-05-311-3/+3
* Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,cognet2006-05-311-1/+1
* Protect the mapping used for pmap_copy_page/pmap_zero_page with acognet2006-05-301-2/+15
* To avoid problems, invalidate the data cache and disable the MMU oncecognet2006-05-301-2/+32
* In pmap_is_prefaultable(), assert that the pte isn't NULL ifcognet2006-05-301-0/+1
* The Assabet has 32MB of RAM, not 16.cognet2006-05-301-2/+3
* In pmap_mapdev we correctly round the address off to the nearest pagebenno2006-05-301-1/+1
* Uncomment the call to cpu_idcache_wbinv_all() after the MMU has beencognet2006-05-301-1/+1
* Nuke sa11x0_attach_args. It's a NetBSDIsm, and we have no use for it.cognet2006-05-291-9/+0
* Remove any reference to enable_mmu(), it's been gone for a long time.cognet2006-05-262-2/+0
* Use pmap_devmap_bootstrap(), instead of mapping the SACOM1 registerscognet2006-05-234-6/+42
* Use macros instead of hardcoding the address for SACOM1. Also don'tcognet2006-05-223-4/+7
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