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* Extract the correct bits from the GICD_TYPER register. The interrupt countandrew2016-05-201-1/+1
* Add more useful GICv3 register definitions. While here fixandrew2016-05-201-1/+25
* Filter out BUS_DMASYNC_POSTWRITE sync operations, there is nothing for usandrew2016-05-201-0/+3
* Enable NEW_PCIB on arm64.andrew2016-05-201-0/+1
* Handle PCI_RES_BUS on the generic and ThunderX PCIe drivers. This has beenandrew2016-05-201-0/+14
* Define PCI_RES_BUS for NEW_PCIBandrew2016-05-191-0/+3
* Return the struct intr_pic pointer from intr_pic_register. This will beandrew2016-05-181-2/+2
* Add support for MSI/MSIX deallocation on GICv3-ITSzbb2016-05-182-8/+87
* The GIC (v2 at least) has a bit in the TYPER register to indicate whether the...bz2016-05-172-4/+10
* Add an arm64 kernel config to help testing intrng. It is expected thisandrew2016-05-171-0/+15
* Clean up the GICv3 intrng code:andrew2016-05-171-4/+10
* Add intrng support to the GICv3 driver. It lacks ITS support so won't handleandrew2016-05-163-4/+626
* Move the call to intr_pic_init_secondary to the same place as in theandrew2016-05-161-5/+3
* Add support for intrng to arm64. As the GICv3 drivers will need to beandrew2016-05-164-1/+298
* Teach the ThunderX PCI PEM driver about intrng. This will be used laterandrew2016-05-161-0/+55
* Add a pcib interface for use by interrupt controllers that need toandrew2016-05-165-61/+97
* Add support to the arm64 busdma to handle the cache. For now this isandrew2016-05-132-23/+203
* Rename the internal BUC_DMA_* flags to BF_* so they won't conflict withandrew2016-05-121-20/+20
* Restrict the memory barriers in bus_dmamap_sync to just the operationsandrew2016-05-121-46/+47
* Call busdma_swi from swi_vm as is done from other architectures.andrew2016-05-112-1/+4
* On arm64 always create a bus_dmamap_t object. This will be use to hold theandrew2016-05-111-44/+72
* Add data barriers to the arm64 bus_dmamap_sync function. We need theseandrew2016-05-111-1/+14
* Fix I/O coherence issues on ThunderX when SMP is disabledzbb2016-05-111-4/+0
* Push the logic to talk with the MSI/MSI-X interrupt controller to the FDTandrew2016-05-102-11/+76
* Native PCI-express HotPlug support.jhb2016-05-051-0/+1
* Fix GICv3 build after r299090zbb2016-05-054-7/+6
* Disable ACPI on arm64 ad it has only had minimal testing and is causingandrew2016-04-261-1/+1
* Move arm's devmap to some generic place, so it can be usedbr2016-04-263-93/+4
* Use the yield instruction in the arm64 cpu_spinwait. This instruction isandrew2016-04-251-1/+1
* sys: use our roundup2/rounddown2() macros when param.h is available.pfg2016-04-211-1/+1
* Group the ThunderX PCIe PEM newbus methods to help find them.andrew2016-04-201-3/+6
* Pull out the MSI/MSI-X handling calls to simplify future intrngandrew2016-04-201-5/+48
* arm: for pointers replace 0 with NULL.pfg2016-04-151-1/+1
* Fix the types for the start, end, and count arguments toandrew2016-04-141-1/+1
* Set the upper limit of the DMAP region to the limit of RAM as was found inandrew2016-04-142-10/+19
* arm64: Avoid null dereference in its_init_cpuemaste2016-04-131-1/+1
* Document the memory ranges within the kernel region to help with debuggingandrew2016-04-131-6/+11
* Increase the arm64 kernel address space to 512GB, and the DMAP region toandrew2016-04-133-25/+43
* Cleanup unnecessary semicolons from the kernel.pfg2016-04-101-1/+1
* Fix interrupts delivery on ThunderX for VF IDs beyond 8zbb2016-04-071-3/+1
* Use PHYS_IN_DMAP to check if a physical address is within the DMAP region.andrew2016-04-061-3/+3
* Cleanup the early pagetable creation code in preperation for increasingandrew2016-04-061-20/+22
* Allow vmparam.h to be included from assembly files on arm64.andrew2016-04-065-4/+9
* Make CloudABI's way of doing TLS more friendly to userspace emulators.ed2016-04-061-2/+26
* Implement dtrace_getupcstack in ARM64wma2016-04-061-0/+5
* Add a table to map from the FreeBSD CPUID space to the GIC CPUID space. Onandrew2016-04-041-15/+35
* Reduce the diff for when we switch to intrng. The IPI interrupts will beandrew2016-04-041-20/+63
* arm64: pagezero improvementwma2016-04-044-7/+47
* Add bzero.S to ARM64 machdepwma2016-04-041-0/+206
* arm64: bzero optimizationwma2016-04-042-11/+20
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